kolibrios-nvme-driver/drivers/nvme/nvme.inc

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;;                                                                 ;;
;; Copyright (C) KolibriOS team 2004-2024. All rights reserved.    ;;
;; Distributed under terms of the GNU General Public License       ;;
;;                                                                 ;;
;;          GNU GENERAL PUBLIC LICENSE                             ;;
;;             Version 2, June 1991                                ;;
;;                                                                 ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

; Opcodes for NVM commands
NVM_CMD_FLUSH = 0x00 
NVM_CMD_WRITE = 0x01
NVM_CMD_READ = 0x02
NVM_CMD_WRITE_UNCORRECTABLE = 0x04
NVM_CMD_COMPARE = 0x05
NVM_CMD_WRITE_ZEROES = 0x08
NVM_CMD_DATASET_MANAGEMENT = 0x09
NVM_CMD_VERIFY = 0x0C
NVM_CMD_RESERVATION_REG = 0x0D
NVM_CMD_RESERVATION_REPORT = 0x0E
NVM_CMD_RESERVATION_ACQUIRE = 0x11
NVM_CMD_RESERVATION_RELEASE = 0x15
NVM_CMD_COPY = 0x19

; Opcodes for admin commands
ADM_CMD_DEL_IO_SUBMISSION_QUEUE = 0x00
ADM_CMD_CRE_IO_SUBMISSION_QUEUE = 0x01
ADM_CMD_GET_LOG_PAGE = 0x02
ADM_CMD_DEL_IO_COMPLETION_QUEUE = 0x04
ADM_CMD_CRE_IO_COMPLETION_QUEUE = 0x05
ADM_CMD_IDENTIFY = 0x06
ADM_CMD_ABORT = 0x08
ADM_CMD_SET_FEATURES = 0x09
ADM_CMD_GET_FEATURES = 0x0A

; fuse (fused operation): In a fused operation, a complex command is created by 'fusing' together
;                         two simpler commands. This field specifies whether this command is part
;                         of a fused operation, and if so, which command it is in the sequence:
;                         00b -> Normal operation
;                         01b -> Fused operation, first command
;                         10b -> Fused operation, second command
;                         11b -> Reserved
NO_FUSE = 0
FUSE_OP_FIRST_CMD = 1 shl 8
FUSE_OP_SECOND_CMD = 2 shl 8

; sel (PRP or SGL for data transfer): This field specifies whether PRPs or SGLs are used for any
;                                     data transfer associated with the command. PRPs shall be
;                                     used for all Admin commands for NVMe over PCIe implementations.
;                                     SGLs shall be used for all Admin and I/O commands for NVMe over
;                                     Fabrics implementations (i.e., field set to 01b):
;                                     00b -> PRPs are used for this transfer
;                                     01b -> SGLs are used for this transfer, MPTR will contain address of 
;                                            a single contiguous physical buffer that is byte aligned
;                                     10b -> SGLs are used for this transfer. MPTR will contain address of
;                                            an SGL segment containing exactly one SGL descriptor that is
;                                            QWORD aligned
;                                     11b -> Reserved
SEL_PRP = 0
SEL_SGL = 1 shl 14

; Controller or Namespace Structure (CNS) specifies the information to be returned to the host.
CNS_IDNS   = 0x0  ; Namespace data structure (NSID)
CNS_IDCS   = 0x1  ; Controller data structure
CNS_ANIDL  = 0x2  ; Active namespace ID list (NSID)
CNS_NIDL   = 0x3  ; Namespace identification descriptor list (NSID)
CNS_NVM_SL = 0x4  ; NVM Set List 

; Optional Admin Command Support (OACS) values
OACS_SEC_SEN_RECV_SUPPORTED = 1 shl 0
OACS_FMT_NVM_SUPPORTED = 1 shl 1
OACS_FIRM_COMDL_SUPPORTED = 1 shl 2
OACS_NSMAN_SUPPORTED = 1 shl 3

; scope is all attached namespaces or all namespaces in NVM subsystem
NSID_BROADCAST = 0xFFFFFFFF

NSSRC_RESET = 0x4E564D65 ; "NVMe" (initiates a NVMe subsystem reset)

; NVMe Capabilities
CAP_MQES = 0xff
CAP_CQR = 1 shl 16
CAP_AMS = (1 shl 17) or (1 shl 18)
CAP_TO = 0xff000000
CAP_DSTRD = 1 or (1 shl 1) or (1 shl 2) or (1 shl 3)
CAP_NSSRS = 1 shl 4
CAP_CSS_NVM_CMDSET = 1 shl 5
CAP_CSS_OMCS = 1 shl 11
CAP_CSS_NOIO = 1 shl 12
CAP_BPS = 1 shl 14
CAP_CPS_COSCOP = 1 shl 15
CAP_CPS_DOSCOP = 1 shl 16
CAP_CPS_NVMSCOP = CAP_CPS_COSCOP or CAP_CPS_DOSCOP
CAP_MPSMIN = (1 shl 17) or (1 shl 18) or (1 shl 19) or (1 shl 20)
CAP_MPSMAX = (1 shl 21) or (1 shl 22) or (1 shl 23) or (1 shl 24)
CAP_PMRS = 1 shl 25
CAP_CMBS = 1 shl 26
CAP_NSSS = 1 shl 27
CAP_CRMS_CRWMS = 1 shl 28
CAP_CRMS_CRIMS = 1 shl 29

; Controller Configuration Bits
CC_ENABLE = 1
CC_CSS = (1 shl 4) or (1 shl 5) or (1 shl 6)
CC_MPS = (1 shl 7) or (1 shl 8) or (1 shl 9) or (1 shl 10)
CC_AMS = (1 shl 11) or (1 shl 12) or (1 shl 13)
CC_SHN = (1 shl 14) or (1 shl 15)
CC_IOSQES = (1 shl 16) or (1 shl 17) or (1 shl 18) or (1 shl 19)
CC_IOCQES = (1 shl 20) or (1 shl 21) or (1 shl 22) or (1 shl 23)
CC_CRIME = 1 shl 24

CC_DEFAULT_IOSQES = 6 shl 16
CC_DEFAULT_IOCQES = 4 shl 16

struct NVME_REG_MAP 
	CAP      rq 1 ; Controller Capabilities
	VS       rd 1 ; Version
	INTMS    rd 1 ; Interrupt Mask Set
	INTMC    rd 1 ; Interrupt Mask Clear
	CC       rd 1 ; Controller Configuration
	         rd 1 ; Reserved
	CSTS     rd 1 ; Controller Status
	NSSR     rd 1 ; NVM Subsystem Reset
	AQA      rd 1 ; Admin Queue Attributes
	ASQ      rq 1 ; Admin Submission Queue Base Address
	ACQ      rq 1 ; Admin Completion Queue Base Address
	CMBLOC   rd 1 ; Controller Memory Buffer Location
ends

; Submission Queue Entry (64 bytes)
struct SQ_ENTRY
	cdw0 			rd 1
	nsid 			rd 1
	cdw2            rd 1
	cdw3            rd 1
	mptr			rq 1
	dptr			rq 1
	cdw10			rd 1
	cdw11			rd 1
	cdw12			rd 1
	cdw13			rd 1
	cdw14			rd 1
	cdw15			rd 1
ends

; Completion Queue Entry ()

struc nvme_dev {
	.pci_bus 		dd ?
	.pci_devfn 		dd ?
	.bar0 			dd ?
	.serial			db 20
	.model 			db 40
}

struct NVME_IDENT_CONTROLLER

	pci_vid	   rw 1
	pci_ssvid  rw 1
	serial     rb 20
	model      rb 40
	firm_rev   rq 1
	rab        rb 1
	ieee       rb 3
	cmic       rb 1
	mdts       rb 1
	ctrlid     rw 1
	ver        rb 3
	rtd3r      rd 1
	rtd3e      rd 1
	ctrlatt    rd 1
	rrls       rw 1
	reserved   rb 9
	ctrltyp    rb 1
	fguid      rq 2
	crdt1      rw 1
	ctdt2      rw 1
	crdt3      rw 1
	           rb 106     ; reserved
	           rb 13      ; reserved (NVMMI)
	nvmsr      rb 1
	vmci       rb 1
	mec        rb 1
	oacs       rw 1
	acl        rb 1
	aerl       rb 1
	frmw       rb 1
	lpa        rb 1
	elpe       rb 1
	npss       rb 1
	avscc      rb 1
	apsta      rb 1
	wctemp     rw 1
	cctemp     rw 1
	mtfa       rw 1
	hmpre      rd 1
	hmmin      rd 1
	tnvmcap    rq 2
	unvmcap    rq 2
	rpmbs      rd 1
	edstt      rw 1
	dsto       rb 1
	fwug       rb 1
	kas        rw 1
	hctma      rw 1
	mntmt      rw 1
	mxtmt      rw 1
	sanicap    rd 1
	hmminds    rd 1
	hmmaxd     rw 1
	nsetidmax  rw 1
	endgidmax  rw 1
	anatt      rb 1
	anacap     rb 1
	anagrpmax  rd 1
	nanagrpid  rd 1
	pels       rd 1
	domid      rw 1
	           rb 10      ; reserved
	megcap     rq 2
	           rb 128     ; reserved
	sqes       rb 1
	cqes       rb 1
	maxcmd     rw 1
	nn         rd 1
	oncs       rw 1
	fuses      rw 1
	fna        rb 1
	vwc        rb 1
	awun       rw 1
	awupf      rw 1
	icsvscc    rb 1
	nwpc       rb 1
	acwu       rw 1
	ocfs       rw 1
	sgls       rd 1
	mnan       rd 1
	maxdna     rq 2
	maxcna     rd 1
	           rb 204     ; reserved
	subnqn     rb 256
	           rb 768     ; reserved
	ioccsz     rd 1
	iorcsz     rd 1
	icdoff     rw 1
	fcatt      rb 1
	msdbd      rb 1
	ofcs       rw 1
	           rb 242     ; reserved
	psd0       rb 32
	psd1       rb 32
	psd2       rb 32
	psd3       rb 32
	psd4       rb 32
	psd5       rb 32
	psd6       rb 32
	psd7       rb 32
	psd8       rb 32
	psd9       rb 32
	psd10      rb 32
	psd11      rb 32
	psd12      rb 32
	psd13      rb 32
	psd14      rb 32
	psd15      rb 32
	psd16      rb 32
	psd17      rb 32
	psd18      rb 32
	psd19      rb 32
	psd20      rb 32
	psd21      rb 32
	psd22      rb 32
	psd23      rb 32
	psd24      rb 32
	psd25      rb 32
	psd26      rb 32
	psd27      rb 32
	psd28      rb 32
	psd29      rb 32
	psd30      rb 32
	psd31      rb 32
	venspec    rb 1024

ends