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https://git.missingno.dev/kolibrios-nvme-driver/
synced 2024-12-23 06:18:47 +01:00
fix errors
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parent
ab0e73b2b5
commit
43a3db6f1e
@ -63,42 +63,41 @@ proc service_proc stdcall, ioctl:dword
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ret
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ret
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endp
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endp
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; todo complete
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proc ns_management_supported stdcall
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mov eax, [p_ident + id_controller.oacs]
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test eax, OACS_NSMAN_SUPPORTED
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ret
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endp
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proc memset stdcall, p_data:dword, val:byte, sz:dword
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proc memset stdcall, p_data:dword, val:byte, sz:dword
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mov ah, byte [val]
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mov bh, byte [val]
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xor ebx, ebx
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xor eax, eax
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@@:
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@@:
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mov byte [p_data + ebx], ah
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mov byte [p_data + eax], bh
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inc ebx
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inc eax
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cmp ebx, dword [sz]
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cmp eax, dword [sz]
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jne @b
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jne @b
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ret
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ret
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endp
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endp
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; Submit a Command in the Admin Submission Queue
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; Submit a Command in the Admin Submission Queue
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proc submit_asq stdcall, p_sq:dword
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proc submit_asq stdcall, p_sq:dword
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mov eax, dword [p_sq]
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mov ebx, dword [bar0]
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add ebx, NVME_REG_ASQ
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xor eax, eax
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ret
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endp
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endp
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proc nvme_identify stdcall, nsid:dword, dptr:dword, cns:byte
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proc nvme_identify stdcall, nsid:dword, dptr:dword, cns:byte
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sub esp, sizeof.sq_entry
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sub esp, sizeof.SQ_ENTRY
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stdcall memset, esp, 0, sizeof.cq_entry
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stdcall memset, esp, 0, sizeof.SQ_ENTRY
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mov eax, dword [nsid]
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mov eax, dword [nsid]
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mov [esp + sq_entry.nsid], eax
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mov [esp + SQ_ENTRY.nsid], eax
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mov eax, dword [dptr]
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mov eax, dword [dptr]
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mov [esp + sq_entry.dptr], eax
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mov dword [esp + SQ_ENTRY.dptr], eax
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; TODO: setting CID to 1 for now but later on keep a list of unique list of identifiers
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; TODO: setting CID to 1 for now but later on keep a list of unique list of identifiers
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mov dword [esp + sq_entry.cdw0], ADM_CMD_IDENTIFY or (1 shl 16)
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mov dword [esp + SQ_ENTRY.cdw0], ADM_CMD_IDENTIFY or (1 shl 16)
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mov ah, byte [cns]
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mov ah, byte [cns]
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mov byte [esp + sq_entry.cdw10], ah
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mov byte [esp + SQ_ENTRY.cdw10], ah
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add esp, sizeof.sq_entry
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stdcall submit_asq, esp
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add esp, sizeof.SQ_ENTRY
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xor eax, eax
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ret
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endp
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endp
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proc detect
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proc detect
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@ -147,15 +146,16 @@ proc detect
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invoke PciRead32, [pcidev_bus], [pcidev_devfn], PCI_header00.base_addr_0
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invoke PciRead32, [pcidev_bus], [pcidev_devfn], PCI_header00.base_addr_0
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mov [bar0], eax
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mov [bar0], eax
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invoke Kmalloc, sizeof.id_controller
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invoke Kmalloc, sizeof.NVME_IDENT_CONTROLLER
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test eax, eax
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test eax, eax
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jz .alloc_id_controller_fail
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jz .alloc_ident_controller_fail
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DEBUGF DBG_INFO,"Successfully allocated %u bytes for 'id_controller'\n",sizeof.id_controller
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DEBUGF DBG_INFO,"Successfully allocated %u bytes for 'NVME_IDENT_CONTROLLER'\n",sizeof.NVME_IDENT_CONTROLLER
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mov [p_ident], eax
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mov [p_ident], eax
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stdcall nvme_identify, 0, dword [p_ident], CNS_IDCS
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stdcall nvme_identify, 0, dword [p_ident], CNS_IDCS
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mov ecx, dword [p_ident]
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mov ecx, dword [p_ident]
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DEBUGF DBG_INFO,"Total NVMe SSD capacity: %ub\n",dword [ecx + id_controller.tnvmcap]
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mov edx, dword [ecx + NVME_IDENT_CONTROLLER.tnvmcap]
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DEBUGF DBG_INFO,"Total NVMe SSD capacity: %ub\n", edx
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; return successfully
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; return successfully
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call nvme_cleanup
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call nvme_cleanup
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@ -165,8 +165,8 @@ proc detect
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inc eax
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inc eax
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ret
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ret
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.alloc_id_controller_fail:
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.alloc_ident_controller_fail:
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DEBUGF DBG_INFO,"ERROR: failed to allocate %u bytes for 'id_controller'\n", sizeof.id_controller
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DEBUGF DBG_INFO,"ERROR: failed to allocate %u bytes for 'NVME_IDENT_CONTROLLER'\n", sizeof.NVME_IDENT_CONTROLLER
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pop eax
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pop eax
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pop ebx
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pop ebx
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xor eax, eax
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xor eax, eax
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@ -91,20 +91,20 @@ OACS_NSMAN_SUPPORTED = 1 shl 3
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NSID_BROADCAST = 0xFFFFFFFF
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NSID_BROADCAST = 0xFFFFFFFF
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; Submission Queue Entry (64 bytes)
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; Submission Queue Entry (64 bytes)
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struc sq_entry {
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struct SQ_ENTRY
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.cdw0 dd ?
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cdw0 rd 1
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.nsid dd ?
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nsid rd 1
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.cdw2 dd ?
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cdw2 rd 1
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.cdw3 dd ?
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cdw3 rd 1
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.mptr dq ?
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mptr rq 1
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.dptr dq ?
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dptr rq 1
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.cdw10 dd ?
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cdw10 rd 1
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.cdw11 dd ?
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cdw11 rd 1
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.cdw12 dd ?
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cdw12 rd 1
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.cdw13 dd ?
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cdw13 rd 1
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.cdw14 dd ?
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cdw14 rd 1
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.cdw15 dd ?
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cdw15 rd 1
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}
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ends
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struc nvme_dev {
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struc nvme_dev {
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.pci_bus dd ?
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.pci_bus dd ?
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@ -114,133 +114,132 @@ struc nvme_dev {
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.model db 40
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.model db 40
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}
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}
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struct id_controller
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struct NVME_IDENT_CONTROLLER
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pci_vid dw ?
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pci_vid rw 1
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pci_ssvid dw ?
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pci_ssvid rw 1
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serial db 20
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serial rb 20
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model db 40
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model rb 40
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firm_rev dq ?
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firm_rev rq 1
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rab db ?
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rab rb 1
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ieee db 3
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ieee rb 3
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cmic db ?
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cmic rb 1
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mdts db ?
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mdts rb 1
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ctrlid dw ?
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ctrlid rw 1
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ver db 3
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ver rb 3
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rtd3r dd ?
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rtd3r rd 1
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rtd3e dd ?
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rtd3e rd 1
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ctrlatt dd ?
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ctrlatt rd 1
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rrls dw ?
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rrls rw 1
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reserved db 9
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reserved rb 9
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ctrltyp db ?
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ctrltyp rb 1
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fguid dq 2
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fguid rq 2
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crdt1 dw ?
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crdt1 rw 1
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ctdt2 dw ?
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ctdt2 rw 1
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crdt3 dw ?
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crdt3 rw 1
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rb 106 ; reserved
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rb 106 ; reserved
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rb 13 ; reserved (NVMMI)
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rb 13 ; reserved (NVMMI)
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nvmsr db ?
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nvmsr rb 1
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vmci db ?
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vmci rb 1
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mec db ?
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mec rb 1
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oacs dw ?
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oacs rw 1
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acl db ?
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acl rb 1
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aerl db ?
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aerl rb 1
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frmw db ?
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frmw rb 1
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lpa db ?
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lpa rb 1
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elpe db ?
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elpe rb 1
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npss db ?
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npss rb 1
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avscc db ?
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avscc rb 1
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apsta db ?
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apsta rb 1
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wctemp dw ?
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wctemp rw 1
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cctemp dw ?
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cctemp rw 1
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mtfa dw ?
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mtfa rw 1
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hmpre dd ?
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hmpre rd 1
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hmmin dd ?
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hmmin rd 1
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tnvmcap dq 2
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tnvmcap rq 2
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unvmcap dq 2
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unvmcap rq 2
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rpmbs dd ?
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rpmbs rd 1
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edstt dw ?
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edstt rw 1
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dsto db ?
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dsto rb 1
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fwug db ?
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fwug rb 1
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kas dw ?
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kas rw 1
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hctma dw ?
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hctma rw 1
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mntmt dw ?
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mntmt rw 1
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mxtmt dw ?
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mxtmt rw 1
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sanicap dd ?
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sanicap rd 1
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hmminds dd ?
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hmminds rd 1
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hmmaxd dw ?
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hmmaxd rw 1
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nsetidmax dw ?
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nsetidmax rw 1
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endgidmax dw ?
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endgidmax rw 1
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anatt db ?
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anatt rb 1
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anacap db ?
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anacap rb 1
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anagrpmax dd ?
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anagrpmax rd 1
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nanagrpid dd ?
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nanagrpid rd 1
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pels dd ?
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pels rd 1
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domid dw ?
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domid rw 1
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rb 10 ; reserved
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rb 10 ; reserved
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megcap dq 2
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megcap rq 2
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rb 128 ; reserved
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rb 128 ; reserved
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sqes db ?
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sqes rb 1
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cqes db ?
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cqes rb 1
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maxcmd dw ?
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maxcmd rw 1
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nn dd ?
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nn rd 1
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oncs dw ?
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oncs rw 1
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fuses dw ?
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fuses rw 1
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fna db ?
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fna rb 1
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vwc db ?
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vwc rb 1
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awun dw ?
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awun rw 1
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awupf dw ?
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awupf rw 1
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icsvscc db ?
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icsvscc rb 1
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nwpc db ?
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nwpc rb 1
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acwu dw ?
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acwu rw 1
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ocfs dw ?
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ocfs rw 1
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sgls dd ?
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sgls rd 1
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mnan dd ?
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mnan rd 1
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maxdna dq 2
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maxdna rq 2
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maxcna dd ?
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maxcna rd 1
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rb 204 ; reserved
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rb 204 ; reserved
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subnqn db 256
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subnqn rb 256
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rb 768 ; reserved
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rb 768 ; reserved
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ioccsz dd ?
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ioccsz rd 1
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iorcsz dd ?
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iorcsz rd 1
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icdoff dw ?
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icdoff rw 1
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fcatt db ?
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fcatt rb 1
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msdbd db ?
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msdbd rb 1
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ofcs dw ?
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ofcs rw 1
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rb 242 ; reserved
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rb 242 ; reserved
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psd0 db 32
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psd0 rb 32
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psd1 db 32
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psd1 rb 32
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psd2 db 32
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psd2 rb 32
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psd3 db 32
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psd3 rb 32
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psd4 db 32
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psd4 rb 32
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psd5 db 32
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psd5 rb 32
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psd6 db 32
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psd6 rb 32
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psd7 db 32
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psd7 rb 32
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psd8 db 32
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psd8 rb 32
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psd9 db 32
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psd9 rb 32
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psd10 db 32
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psd10 rb 32
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psd11 db 32
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psd11 rb 32
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psd12 db 32
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psd12 rb 32
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psd13 db 32
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psd13 rb 32
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psd14 db 32
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psd14 rb 32
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psd15 db 32
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psd15 rb 32
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psd16 db 32
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psd16 rb 32
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psd17 db 32
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psd17 rb 32
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psd18 db 32
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psd18 rb 32
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psd19 db 32
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psd19 rb 32
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psd20 db 32
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psd20 rb 32
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psd21 db 32
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psd21 rb 32
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psd22 db 32
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psd22 rb 32
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psd23 db 32
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psd23 rb 32
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psd24 db 32
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psd24 rb 32
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psd25 db 32
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psd25 rb 32
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psd26 db 32
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psd26 rb 32
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psd27 db 32
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psd27 rb 32
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psd28 db 32
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psd28 rb 32
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psd29 db 32
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psd29 rb 32
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psd30 db 32
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psd30 rb 32
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psd31 db 32
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psd31 rb 32
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venspec db 1024
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venspec rb 1024
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ends
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ends
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