mirror of
https://git.missingno.dev/kolibrios-nvme-driver/
synced 2024-12-22 22:08:47 +01:00
fix lots of nasty bugs!
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e2e1e50490
commit
78af4fb996
@ -42,13 +42,13 @@ proc START c, reason:dword
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test eax, eax
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jz .err
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xor ecx, ecx
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mov ebx, eax
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.loop:
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stdcall device_is_compat, dword [ebx + ecx * sizeof.pcidev]
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mov ebx, dword [p_nvme_devices]
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stdcall device_is_compat, ebx
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test eax, eax
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jz @f
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stdcall nvme_init, dword [ebx + ecx * sizeof.pcidev]
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stdcall nvme_init, ebx
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@@:
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inc ecx
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@ -157,20 +157,23 @@ proc detect_nvme
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mov ebx, dword [p_nvme_devices]
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test ebx, ebx
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jnz @f
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invoke KernelAlloc, TOTAL_PCIDEVS_MALLOC_SZ
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invoke KernelAlloc, sizeof.pcidev
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test eax, eax
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jz .err_no_mem
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mov dword [p_nvme_devices], eax
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DEBUGF DBG_INFO, "(NVMe) Allocated pcidev struct at 0x%x\n", [p_nvme_devices]
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@@:
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mov ebx, dword [p_nvme_devices]
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mov ecx, dword [pcidevs_len]
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dec ecx
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pop eax
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mov ebx, dword [p_nvme_devices]
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movzx edx, byte [eax + PCIDEV.bus]
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mov byte [ebx + ecx * sizeof.pcidev + pcidev.bus], dl
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mov byte [ebx + pcidev.bus], dl
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movzx edx, byte [eax + PCIDEV.devfn]
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mov byte [ebx + ecx * sizeof.pcidev + pcidev.devfn], dl
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mov byte [ebx + pcidev.devfn], dl
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pop edx
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jmp .next_dev
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@ -188,44 +191,30 @@ endp
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proc device_is_compat stdcall, pci:dword
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push ebx
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invoke PciRead32, dword [pci + pcidev.bus], dword [pci + pcidev.devfn], PCI_header00.base_addr_0
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push ebx
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mov ebx, [pci]
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invoke PciRead32, dword [ebx + pcidev.bus], dword [ebx + pcidev.devfn], PCI_header00.base_addr_0
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and eax, 0xfffffff0
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test eax, eax
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jz .failure
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invoke MapIoMem, eax, sizeof.NVME_REG_MAP, PG_SW+PG_NOCACHE
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invoke MapIoMem, eax, sizeof.NVME_MMIO, PG_SW+PG_NOCACHE
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test eax, eax
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jz .failure
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mov dword [pci + pcidev.mmio_ptr], eax
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mov ebx, dword [eax + NVME_REG_MAP.VS]
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if __DEBUG__
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push ecx
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mov ecx, ebx
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shr ecx, 16
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PDEBUGF DBG_INFO, "PCI(%u.%u.%u): NVMe controller version: %u.%u.%u\n", byte [pci + pcidev.bus], byte [pci + pcidev.devfn], ecx, bh, bl
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pop ecx
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end if
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if 0
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cmp ebx, NVM_SUPPORTED_CONTROLLER_VERSION
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jne .unsupported
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PDEBUGF DBG_INFO, "PCI(%u.%u.%u): NVMe controller version is supported\n", byte [pci + pcidev.bus], byte [pci + pcidev.devfn]
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end if
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DEBUGF DBG_INFO, "(NVMe) MMIO allocated at: 0x%x\n", eax
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mov ebx, [pci]
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mov dword [ebx + pcidev.mmio_ptr], eax
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mov eax, dword [eax + NVME_MMIO.VS]
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DEBUGF DBG_INFO, "(NVMe) controller version: 0x%x\n", eax
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pop ebx
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xor eax, eax
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inc eax
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pop ebx
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ret
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.unsupported:
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PDEBUGF DBG_INFO, "PCI(%u.%u.%u): unsupported controller version\n", byte [pci + pcidev.bus], byte [pci + pcidev.devfn]
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.failure:
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PDEBUGF DBG_INFO, "PCI(%u.%u.%u): something went wrong checking NVMe device compatibility\n", byte [pci + pcidev.bus], byte [pci + pcidev.devfn]
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xor eax, eax
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PDEBUGF DBG_INFO, "PCI(%u.%u.%u): something went wrong checking NVMe device compatibility\n", byte [ebx + pcidev.bus], byte [ebx + pcidev.devfn]
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pop ebx
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xor eax, eax
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ret
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endp
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@ -233,81 +222,69 @@ endp
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; nvme_init: Initializes the NVMe controller
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proc nvme_init stdcall, pci:dword
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push ebx ecx
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mov eax, dword [pci + pcidev.mmio_ptr]
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mov bx, word [eax + NVME_REG_MAP.CAP]
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PDEBUGF DBG_INFO, "PCI(%u.%u.%u): NVMe maximum queue entries supported: %u\n", byte [pci + pcidev.bus], byte [pci + pcidev.devfn], bx
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push ebx
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mov eax, dword [pci]
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mov eax, dword [eax + pcidev.mmio_ptr]
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mov ebx, dword [eax + NVME_MMIO.CAP]
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test ebx, CAP_CQR
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jz .cqr_not_req
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PDEBUGF DBG_INFO, "PCI(%u.%u.%u): NVMe contiguous queues required\n", byte [pci + pcidev.bus], byte [pci + pcidev.devfn]
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.cqr_not_req:
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; For some reason, bit 7 (No I/O command set supported) is also set to 1 despite bit 0 (NVM command set)
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; being set to 1.. so I am not sure if bit 7 should be checked at all.. investigate later.
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mov ebx, dword [eax + NVME_REG_MAP.CAP + 4]
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mov ebx, dword [eax + NVME_MMIO.CAP + 4]
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test ebx, CAP_CSS_NVM_CMDSET
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jz .exit_fail
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if __DEBUG__
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mov ecx, ebx
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and ebx, CAP_MPSMIN
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and ecx, CAP_MPSMAX
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shr ebx, 16
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shr ecx, 16
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PDEBUGF DBG_INFO, "PCI(%u.%u.%u): NVMe memory page size minimum: %u\n", byte [pci + pcidev.bus], byte [pci + pcidev.devfn], ebx
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PDEBUGF DBG_INFO, "PCI(%u.%u.%u): NVMe memory page size maximum: %u\n", byte [pci + pcidev.bus], byte [pci + pcidev.devfn], ecx
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end if
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; Reset controller
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mov ebx, dword [eax + NVME_REG_MAP.CC]
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stdcall nvme_controller_reset, [pci]
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stdcall nvme_controller_reset, [pci]
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xor eax, eax
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inc eax
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pop ecx ebx
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pop ebx
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ret
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.exit_fail:
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PDEBUGF DBG_INFO, "PCI(%u.%u.%u): failed to initialize NVMe controller\n", byte [pci + pcidev.bus], byte [pci + pcidev.devfn]
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xor eax, eax
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pop ecx ebx
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pop ebx
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ret
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endp
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proc nvme_controller_reset stdcall, pci:dword
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DEBUGF DBG_INFO, "(NVMe) Resetting Controller...\n"
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push ebx
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PDEBUGF DBG_INFO, "PCI(%u.%u.%u): Resetting NVMe controller\n", byte [pci + pcidev.bus], byte [pci + pcidev.devfn]
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mov eax, dword [pci + pcidev.mmio_ptr]
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mov ebx, dword [eax + NVME_REG_MAP.CSTS]
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mov ebx, dword [pci]
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mov ebx, dword [ebx + pcidev.mmio_ptr]
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mov eax, dword [ebx + NVME_MMIO.CC]
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and eax, 0xfffffffe ; CC.EN = 0
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mov dword [ebx + NVME_MMIO.CC], eax
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stdcall nvme_wait, [pci]
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; Wait for controller to be brought to idle state, CSTS.RDY should be cleared to 0 when this happens
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.wait:
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test ebx, CSTS_RDY
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mov eax, dword [ebx + NVME_MMIO.CSTS]
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test eax, CSTS_RDY
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jnz .wait
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mov ebx, dword [eax + NVME_REG_MAP.CC]
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PDEBUGF DBG_INFO, "PCI(%u.%u.%u): NVMe.CC = 0x%x\n", byte [pci + pcidev.bus], byte [pci + pcidev.devfn], ebx
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and ebx, 0xfffffffe
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mov dword [eax + NVME_REG_MAP.CC], ebx
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stdcall nvme_wait, [pci]
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DEBUGF DBG_INFO, "(NVMe) Successfully reset controller...\n"
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pop ebx
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ret
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endp
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; Should be called only after the value of CC.EN has changed
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proc nvme_wait stdcall, pci:dword
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push esi
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mov eax, dword [pci + pcidev.mmio_ptr]
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mov eax, dword [eax + NVME_REG_MAP.CAP]
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mov eax, [pci]
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mov eax, [eax + pcidev.mmio_ptr]
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mov eax, dword [eax + NVME_MMIO.CAP]
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and eax, CAP_TO
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shr eax, 24
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DEBUGF DBG_INFO, "CSTS.TO = %u\n", eax
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mov esi, eax
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;imul esi, 500
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;invoke Sleep
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pop esi
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imul esi, 50
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invoke Sleep
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ret
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endp
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@ -316,17 +293,17 @@ proc nvme_cleanup
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DEBUGF DBG_INFO, "(NVMe): Cleaning up...\n"
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push ecx
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xor ecx, ecx
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mov eax, dword [p_nvme_devices]
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mov ecx, eax
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test eax, eax
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jnz .loop
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ret
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.loop:
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;invoke KernelFree, dword [p_nvme_devices + ecx * sizeof.pcidev + pcidev.ident_ptr]
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inc ecx
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cmp ecx, dword [pcidevs_len]
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jne .loop
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dec ecx
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test ecx, ecx
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jnz .loop
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invoke KernelFree, dword [p_nvme_devices]
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pop ecx
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ret
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@ -163,41 +163,41 @@ CSTS_SHST = (1 shl 2) or (1 shl 3)
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CSTS_NSSRO = 1 shl 4
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CSTS_PP = 1 shl 5
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struct NVME_REG_MAP
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CAP rq 1 ; Controller Capabilities
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VS rd 1 ; Version
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INTMS rd 1 ; Interrupt Mask Set
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INTMC rd 1 ; Interrupt Mask Clear
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CC rd 1 ; Controller Configuration
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rd 1 ; Reserved
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CSTS rd 1 ; Controller Status
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NSSR rd 1 ; NVM Subsystem Reset
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AQA rd 1 ; Admin Queue Attributes
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ASQ rq 1 ; Admin Submission Queue Base Address
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ACQ rq 1 ; Admin Completion Queue Base Address
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CMBLOC rd 1 ; Controller Memory Buffer Location
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struct NVME_MMIO
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CAP dq ? ; Controller Capabilities
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VS dd ? ; Version
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INTMS dd ? ; Interrupt Mask Set
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INTMC dd ? ; Interrupt Mask Clear
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CC dd ? ; Controller Configuration
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dd ? ; Reserved
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CSTS dd ? ; Controller Status
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NSSR dd ? ; NVM Subsystem Reset
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AQA dd ? ; Admin Queue Attributes
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ASQ dq ? ; Admin Submission Queue Base Address
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ACQ dq ? ; Admin Completion Queue Base Address
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CMBLOC dd ? ; Controller Memory Buffer Location
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ends
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; Submission Queue Entry (64 bytes)
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struct SQ_ENTRY
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cdw0 rd 1
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nsid rd 1
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cdw2 rd 1
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cdw3 rd 1
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mptr rq 1
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dptr rq 1
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cdw10 rd 1
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cdw11 rd 1
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cdw12 rd 1
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cdw13 rd 1
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cdw14 rd 1
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cdw15 rd 1
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cdw0 dd ?
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nsid dd ?
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cdw2 dd ?
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cdw3 dd ?
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mptr dq ?
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dptr dq ?
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cdw10 dd ?
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cdw11 dd ?
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cdw12 dd ?
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cdw13 dd ?
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cdw14 dd ?
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cdw15 dd ?
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ends
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; Completion Queue Entry (16 bytes)
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struct CQ_ENTRY
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cdw0 dd ?
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dd ? ; reserved
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rd 1 ; reserved
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sqhd dw ?
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sqid dw ?
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cid dw ?
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@ -207,7 +207,7 @@ ends
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struct pcidev
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bus db ?
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devfn db ?
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dw ?
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rw 1
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mmio_ptr dd ?
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ends
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TOTAL_PCIDEVS = 4
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