GSoC/kolibrios-nvme-driver
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Code Issues 2 Actions Activity

tidy up queue allocation

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This commit is contained in:
Abdur-Rahman Mansoor 2024-08-05 12:49:28 -04:00
parent e2c2254a5b
commit 8557d0a450
1 changed files with 20 additions and 23 deletions
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43
drivers/nvme/nvme.asm
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@ -664,11 +664,17 @@ proc nvme_init stdcall, pci:dword
end if end if
; check maximum queue entries supported ; check maximum queue entries supported
mov ax, word [edi + NVME_MMIO.CAP] mov eax, dword [edi + NVME_MMIO.CAP]
cmp ax, SQ_ENTRIES cmp ax, SQ_ENTRIES
jb .exit_fail jb .exit_fail
DEBUGF DBG_INFO, "nvme%u: OK... maximum queue entries is %u\n", [esi + pcidev.num], ax DEBUGF DBG_INFO, "nvme%u: OK... maximum queue entries is %u\n", [esi + pcidev.num], ax
if __DEBUG__
test eax, CAP_CQR
setnz al
DEBUGF DBG_INFO, "nvme%u: Contiguous queues required: %u\n", [esi + pcidev.num], al
end if
; For some reason, bit 7 (No I/O command set supported) is also set to 1 despite bit 0 (NVM command set) ; For some reason, bit 7 (No I/O command set supported) is also set to 1 despite bit 0 (NVM command set)
; being set to 1.. so I am not sure if bit 7 should be checked at all.. investigate later. ; being set to 1.. so I am not sure if bit 7 should be checked at all.. investigate later.
mov eax, dword [edi + NVME_MMIO.CAP + 4] mov eax, dword [edi + NVME_MMIO.CAP + 4]
@ -721,34 +727,25 @@ proc nvme_init stdcall, pci:dword
stdcall memsetdz, eax, sizeof.NVM_QUEUE_ENTRY * (LAST_QUEUE_ID + 1) / 4 stdcall memsetdz, eax, sizeof.NVM_QUEUE_ENTRY * (LAST_QUEUE_ID + 1) / 4
; Allocate submission/completion queue pointers ; Allocate submission/completion queue pointers
; TODO: Make these queues physically contiguous xor ebx, ebx
xor ecx, ecx
.init_queues: .init_queues:
push ecx invoke KernelAlloc, PAGE_SIZE * 2
invoke CreateRingBuffer, 0x1000, PG_SW
pop ecx
test eax, eax test eax, eax
jz .exit_fail jz .exit_fail
mov dword [edi + ecx + NVM_QUEUE_ENTRY.sq_ptr], eax mov dword [edi + ebx + NVM_QUEUE_ENTRY.sq_ptr], eax
push ecx add eax, PAGE_SIZE
stdcall memsetdz, eax, sizeof.SQ_ENTRY * SQ_ENTRIES / 4 mov dword [edi + ebx + NVM_QUEUE_ENTRY.cq_ptr], eax
invoke CreateRingBuffer, 0x1000, PG_SW sub eax, PAGE_SIZE
pop ecx stdcall memsetdz, eax, PAGE_SIZE * 2 / 4
test eax, eax
jz .exit_fail
mov dword [edi + ecx + NVM_QUEUE_ENTRY.cq_ptr], eax
push ecx
stdcall memsetdz, eax, sizeof.CQ_ENTRY * CQ_ENTRIES / 4
; Initialize command entries ; Initialize command entries
invoke KernelAlloc, sizeof.NVMQCMD * CQ_ENTRIES invoke KernelAlloc, sizeof.NVMQCMD * CQ_ENTRIES
pop ecx
test eax, eax test eax, eax
jz .exit_fail jz .exit_fail
mov dword [edi + ecx + NVM_QUEUE_ENTRY.cmd_ptr], eax mov dword [edi + ebx + NVM_QUEUE_ENTRY.cmd_ptr], eax
mov esi, eax mov esi, eax
push ecx push ebx
xor ebx, ebx xor ebx, ebx
.init_cmd_entries: .init_cmd_entries:
@ -765,9 +762,9 @@ proc nvme_init stdcall, pci:dword
cmp ebx, CQ_ENTRIES cmp ebx, CQ_ENTRIES
jne .init_cmd_entries jne .init_cmd_entries
pop ecx pop ebx
add ecx, sizeof.NVM_QUEUE_ENTRY add ebx, sizeof.NVM_QUEUE_ENTRY
cmp ecx, (LAST_QUEUE_ID + 1) * sizeof.NVM_QUEUE_ENTRY cmp ebx, (LAST_QUEUE_ID + 1) * sizeof.NVM_QUEUE_ENTRY
jne .init_queues jne .init_queues
; Configure Admin Submission/Completion Queue Base Address ; Configure Admin Submission/Completion Queue Base Address
@ -1126,7 +1123,7 @@ proc sqytdbl_write stdcall, pci:dword, y:word, cmd:dword
shl edx, cl shl edx, cl
imul edx, ebx imul edx, ebx
add edx, 0x1000 add edx, 0x1000
DEBUGF DBG_INFO, "nvme%u: Writing to SQ%u doorbell register 0x%x: %u\n", [esi + pcidev.num], [y], dx, ax ;DEBUGF DBG_INFO, "nvme%u: Writing to SQ%u doorbell register 0x%x: %u\n", [esi + pcidev.num], [y], dx, ax
mov word [edi + NVM_QUEUE_ENTRY.tail], ax mov word [edi + NVM_QUEUE_ENTRY.tail], ax
mov esi, dword [esi + pcidev.io_addr] mov esi, dword [esi + pcidev.io_addr]
mov word [esi + edx], ax mov word [esi + edx], ax