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https://git.missingno.dev/kolibrios-nvme-driver/
synced 2025-02-02 02:20:09 +01:00
lots of fixes
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@ -447,11 +447,6 @@ proc device_is_compat stdcall, pci:dword
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mov dword [esi + pcidev.io_addr], eax
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mov eax, dword [eax + NVME_MMIO.CAP + 4]
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and eax, CAP_DSTRD
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; Stride is (2 ^ (2 + DSTRD)) bytes
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add al, 2
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stdcall pow2, eax
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mov ecx, eax
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mov byte [esi + pcidev.dstrd], al
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; 1003h + ((2y + 1) * (4 << CAP.DSTRD))
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@ -582,8 +577,21 @@ proc nvme_init stdcall, pci:dword
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jz .exit_fail
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mov dword [dptr], eax
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invoke GetPhysAddr
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mov ebx, eax
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stdcall get_new_cid, [pci], 0
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DEBUGF DBG_INFO, "(NVMe) Got Command Identifier: %u\n", eax
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; pci:dword, nsid:dword, dptr:dword, cid:word, cns:byte
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stdcall nvme_identify, [pci], 0, eax, 2, CNS_IDCS
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stdcall nvme_identify, [pci], 0, ebx, eax, CNS_IDCS
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mov esi, dword [esi + pcidev.cq_ptr]
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; Wait until phase tag bit is set
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@@:
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mov al, byte [esi + CQ_ENTRY.status]
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test al, CQ_PHASE_TAG
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jz @b
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mov esi, dword [dptr]
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mov ax, word [esi + IDENTC.vid]
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DEBUGF DBG_INFO, "(NVMe) IDENTC.vid = %x\n", ax
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xor eax, eax
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inc eax
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@ -598,20 +606,23 @@ proc nvme_init stdcall, pci:dword
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endp
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proc get_avl_cmd stdcall, pci:dword, y:dword
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proc get_new_cid stdcall, pci:dword, y:dword
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push esi ebx
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mov esi, [pci]
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mov ecx, [y]
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mov eax, dword [esi + ecx * pcidev.queue_entries + NVM_QUEUE_ENTRY.cid_slots]
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imul ecx, sizeof.NVM_QUEUE_ENTRY
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mov esi, [pci]
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mov esi, dword [esi + pcidev.queue_entries]
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lea esi, dword [esi + ecx]
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mov eax, dword [esi + NVM_QUEUE_ENTRY.cid_slots]
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xor edx, edx
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cmp eax, 0xffffffff
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jne @f
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mov eax, dword [esi + ecx * pcidev.queue_entries + NVM_QUEUE_ENTRY.cid_slots + 4]
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mov eax, dword [esi + NVM_QUEUE_ENTRY.cid_slots + 4]
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add edx, 4
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cmp eax, 0xffffffff
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jne @f
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pop esi
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pop ebx esi
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mov eax, -1
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ret
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@ -626,7 +637,13 @@ proc get_avl_cmd stdcall, pci:dword, y:dword
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or ebx, eax
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mov ecx, [y]
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mov dword [esi + ecx * pcidev.queue_entries + NVM_QUEUE_ENTRY.cid_slots + edx], ebx
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mov dword [esi + edx + NVM_QUEUE_ENTRY.cid_slots], ebx
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bsf eax, eax
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cmp edx, 4
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jne @f
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add eax, 32
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@@:
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pop ebx esi
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ret
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@ -724,12 +741,14 @@ proc cqyhdbl_write stdcall, pci:dword, y:byte, cqh:word
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imul dx, ax
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add dx, 0x1000
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movzx ecx, [y]
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imul ecx, sizeof.NVM_QUEUE_ENTRY
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mov edi, dword [esi + pcidev.queue_entries]
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lea edi, dword [edi + ecx]
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mov esi, dword [esi + pcidev.io_addr]
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mov ax, [cqh]
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DEBUGF DBG_INFO, "(NVMe) Writing to completion queue doorbell register 0x%x: %u\n", dx, ax
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mov word [esi + edx], ax ; Write to CQyHDBL
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mov word [edi + ecx * sizeof.NVM_QUEUE_ENTRY + NVM_QUEUE_ENTRY.head], ax
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mov word [edi + NVM_QUEUE_ENTRY.head], ax
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pop edi esi
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ret
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@ -742,7 +761,6 @@ proc write_admin_cmd stdcall, pci:dword
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mov esi, dword [esi + pcidev.queue_entries]
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mov ax, word [esi + NVM_QUEUE_ENTRY.tail]
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cmp ax, NVM_ASQS
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jl @f
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xor ax, ax
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@@:
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@ -799,8 +817,8 @@ proc irq_handler
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jmp .exit
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@@:
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mov dword [esi + NVME_MMIO.INTMC], 0x1
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stdcall cqyhdbl_write, [p_nvme_devices], 0x0, 0x1
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mov dword [esi + NVME_MMIO.INTMC], 0x1
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.exit:
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; Interrupt handled by driver, return 1
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@ -318,8 +318,7 @@ ends
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struct NVM_QUEUE_ENTRY
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tail dw ?
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head dw ?
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dptr dd ?
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;cid_slots dq ?
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cid_slots dq ?
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ends
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; Identify Controller Data Structure
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