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refactor: dont map MMIO registers twice
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@ -563,29 +563,15 @@ proc device_is_compat stdcall, pci:dword
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test eax, eax
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test eax, eax
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jz .failure
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jz .failure
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mov edx, eax
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mov edx, eax
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push edx
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invoke MapIoMem, eax, sizeof.NVME_MMIO, PG_SW+PG_NOCACHE
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invoke MapIoMem, eax, 0x2000, PG_SW+PG_NOCACHE
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test eax, eax
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test eax, eax
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jz .failure
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jz .failure
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;DEBUGF DBG_INFO, "(NVMe) MMIO allocated at: 0x%x\n", eax
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mov dword [esi + pcidev.io_addr], eax
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mov dword [esi + pcidev.io_addr], eax
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mov eax, dword [eax + NVME_MMIO.CAP + 4]
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mov eax, dword [eax + NVME_MMIO.CAP + 4]
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and eax, CAP_DSTRD
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and eax, CAP_DSTRD
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mov byte [esi + pcidev.dstrd], al
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mov byte [esi + pcidev.dstrd], al
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mov eax, dword [esi + pcidev.io_addr]
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; 1003h + ((2y + 1) * (4 << CAP.DSTRD))
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mov eax, 4
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shl ax, cl
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mov ecx, NVM_ASQS
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shl ecx, 1
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inc ecx
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imul ecx, eax
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add ecx, 0x1003
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pop edx
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invoke MapIoMem, edx, ecx, PG_SW+PG_NOCACHE
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mov dword [esi + pcidev.io_addr], eax
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mov eax, dword [eax + NVME_MMIO.VS]
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mov eax, dword [eax + NVME_MMIO.VS]
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DEBUGF DBG_INFO, "nvme%u: Controller version: 0x%x\n", [esi + pcidev.num], eax
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DEBUGF DBG_INFO, "nvme%u: Controller version: 0x%x\n", [esi + pcidev.num], eax
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mov dword [esi + pcidev.version], eax
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mov dword [esi + pcidev.version], eax
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