mirror of
https://git.missingno.dev/kolibrios-nvme-driver/
synced 2024-12-23 06:18:47 +01:00
877 lines
22 KiB
NASM
877 lines
22 KiB
NASM
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; ;;
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;; Copyright (C) KolibriOS team 2004-2024. All rights reserved. ;;
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;; Distributed under terms of the GNU General Public License ;;
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;; ;;
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;; GNU GENERAL PUBLIC LICENSE ;;
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;; Version 2, June 1991 ;;
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;; ;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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format PE DLL native
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entry START
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API_VERSION equ 0 ;debug
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SRV_GETVERSION equ 0
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__DEBUG__ = 1
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__DEBUG_LEVEL__ = 1
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DRIVER_VERSION = 1
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DBG_INFO = 1
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section ".flat" code readable writable executable
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include "../proc32.inc"
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include "../struct.inc"
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include "../macros.inc"
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include "../fdo.inc"
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include "../pci.inc"
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include "../peimport.inc"
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include "nvme.inc"
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include "macros.inc"
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include "lib.asm"
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proc START c, reason:dword
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cmp [reason], DRV_ENTRY
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jne .err
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.entry:
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DEBUGF DBG_INFO, "Detecting NVMe hardware...\n"
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call detect_nvme
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test eax, eax
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jz .err
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mov eax, dword [p_nvme_devices]
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test eax, eax
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jz .err
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xor ecx, ecx
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.loop:
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mov ebx, dword [p_nvme_devices]
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stdcall device_is_compat, ebx
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test eax, eax
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jz @f
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stdcall nvme_init, ebx
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;@@:
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;inc ecx
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;cmp ecx, dword [pcidevs_len]
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;jne .loop
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invoke RegService, my_service, service_proc
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ret
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.err:
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call nvme_cleanup
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xor eax, eax
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ret
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endp
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proc service_proc stdcall, ioctl:dword
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mov ebx, [ioctl]
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mov eax, [ebx+IOCTL.io_code]
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cmp eax, SRV_GETVERSION
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jne @F
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mov eax, [ebx+IOCTL.output]
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cmp [ebx+IOCTL.out_size], 4
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jne @F
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mov dword [eax], API_VERSION
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xor eax, eax
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ret
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@@:
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or eax, -1
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ret
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endp
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proc set_cdw0 stdcall, opcode:byte, cid:word
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movzx eax, [cid]
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shl eax, 16
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or eax, [opcode]
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ret
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endp
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; See pages 161-205 of the NVMe 1.4 specification for reference
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proc nvme_identify stdcall, pci:dword, nsid:dword, dptr:dword, cid:word, cns:byte
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push esi
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mov esi, [pci]
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; It's important to check if CNS is a valid value here. In revision 1.0
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; CNS is a 1 bit field and a two bit field in revision 1.1, using invalid
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; values results in undefined behavior (see page 162 of NVMe 1.4 spec)
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if __DEBUG__
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push esi
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mov esi, dword [esi + pcidev.io_addr]
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mov eax, dword [esi + NVME_MMIO.VS]
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cmp eax, VS110
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jne @f
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cmp [cns], 11b
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jle .ok
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DEBUGF DBG_INFO, "(NVMe) FATAL ERROR: INVALID CNS VALUE ON v1.1.0 CONTROLLERS\n"
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jmp .err
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@@:
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cmp eax, VS100
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jne .ok
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cmp [cns], 1b
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jle .ok
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DEBUGF DBG_INFO, "(NVMe) FATAL ERROR: INVALID CNS VALUE ON v1.0.0 CONTROLLERS\n"
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jmp .err
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.err:
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jmp @b
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.ok:
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pop esi
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end if
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mov esi, [esi + pcidev.sq_ptr]
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stdcall memset, esi, 0, sizeof.SQ_ENTRY
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mov eax, [nsid]
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mov dword [esi + SQ_ENTRY.nsid], eax
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mov eax, [dptr]
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mov dword [esi + SQ_ENTRY.dptr], eax
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movzx eax, [cid]
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shl eax, 16
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mov dword [esi + SQ_ENTRY.cdw0], ADM_CMD_IDENTIFY
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or dword [esi + SQ_ENTRY.cdw0], eax
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mov al, [cns]
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mov byte [esi + SQ_ENTRY.cdw10], al
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stdcall write_admin_cmd, [pci]
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pop esi
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ret
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endp
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; See pages 348-349 of the NVMe 1.4 specification for information on creating namespaces
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proc create_namespace stdcall, pci:dword, cid:word
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push esi
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invoke AllocPage
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test eax, eax
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jz .fail
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invoke GetPhysAddr
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stdcall nvme_identify, [pci], 0xffffffff, eax, [cid], CNS_IDNS
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.fail:
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pop esi
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ret
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endp
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; See page 101 of the NVMe 1.4 specification for reference
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proc create_io_completion_queue stdcall, pci:dword, prp1:dword, qid:word, ien:byte
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push esi ebx
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mov esi, [pci]
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xor ebx, ebx
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movzx eax, [ien]
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and eax, 10b
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or ebx, eax
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movzx eax, byte [esi + pcidev.pc]
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and eax, 0x1
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or ebx, eax ; CDW.PC
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mov esi, [esi + pcidev.sq_ptr]
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stdcall memset, esi, 0, sizeof.SQ_ENTRY
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stdcall set_cdw0, ADM_CMD_CRE_IO_COMPLETION_QUEUE, 0 ; [TODO: Set CID to valid value]
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mov dword [esi + SQ_ENTRY.cdw0], eax
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; Since we are not using MSI-X or MSI vector (yet), CDW11.IV must be set to 0
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mov dword [esi + SQ_ENTRY.cdw11], ebx
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mov bx, [qid] ; CDW10.QID
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or ebx, (sizeof.CQ_ENTRY shl 16) ; CDW10.QSIZE
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mov dword [esi + SQ_ENTRY.cdw10], ebx
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mov ebx, [prp1]
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mov dword [esi + SQ_ENTRY.dptr], ebx
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stdcall sqytdbl_write, [pci], [qid], 0 ; setting last param to 0 for now, change later
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pop ebx esi
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ret
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endp
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; See page 103-104 of the NVMe 1.4 specification for reference
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proc create_io_submission_queue stdcall, pci:dword, prp1:dword, qid:word, cqid:word
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push esi ebx
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mov esi, [pci]
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movzx ebx, byte [esi + pcidev.pc]
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and ebx, 0x1 ; CDW11.PC
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mov esi, [esi + pcidev.sq_ptr]
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stdcall memset, esi, 0, sizeof.SQ_ENTRY
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stdcall set_cdw0, ADM_CMD_CRE_IO_SUBMISSION_QUEUE, 0 ; [TODO: Set CID to valid value]
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mov dword [esi + SQ_ENTRY.cdw0], eax
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movzx eax, [cqid]
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shl eax, 16
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or ebx, eax ; CDW11.CQID
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; TODO: Set CDW10.QPRIO
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mov dword [esi + SQ_ENTRY.cdw11], ebx
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movzx ebx, sizeof.SQ_ENTRY
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shl ebx, 16 ; CDW10.QSIZE
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or ebx, [qid] ; CDW10.QID
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mov dword [esi + SQ_ENTRY.cdw10], ebx
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mov ebx, [prp1]
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mov dword [esi + SQ_ENTRY.dptr], ebx
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stdcall sqytdbl_write, [pci], [qid], 0 ; setting last param to 0 for now, change later
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pop ebx esi
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ret
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endp
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; See page 95-96 of the NVMe 1.4 specification for reference
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proc abort stdcall, pci:dword, cid:word, sqid:word
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push esi
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mov esi, [pci]
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stdcall memset, esi, 0, sizeof.SQ_ENTRY
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stdcall set_cdw0, ADM_CMD_ABORT, 0 ; [TODO: Set CID to valid value]
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mov dword [esi + SQ_ENTRY.cdw0], eax
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mov eax, [cid]
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shl eax, 16
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or eax, [sqid]
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mov dword [esi + SQ_ENTRY.cdw10], eax
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stdcall sqytdbl_write, [pci], 0, 0
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pop esi
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ret
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endp
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; See page 205 of the NVMe 1.4 specification for reference
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proc set_features stdcall, pci:dword, dptr:dword, fid:byte
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push esi
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mov esi, [pci]
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mov esi, [esi + pcidev.sq_ptr]
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stdcall memset, esi, 0, sizeof.SQ_ENTRY
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stdcall set_cdw0, AMD_CMD_SET_FEATURES, 0 ; [TODO: Set CID to valid value]
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mov eax, [dptr]
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mov dword [esi + SQ_ENTRY.dptr], eax
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mov al, [fid]
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mov byte [esi + SQ_ENTRY.cdw10], al
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; TODO: Set CDW10.SV and CDW14.UUID to valid value
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stdcall sqytdbl_write, [pci], 0, 0
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pop esi
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ret
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endp
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; See page 105 of the NVMe 1.4 specification for reference
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proc delete_io_completion_queue stdcall, pci:dword, qid:word
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push esi
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mov esi, [pci]
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mov esi, [esi + pcidev.sq_ptr]
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stdcall memset, esi, 0, sizeof.SQ_ENTRY
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stdcall set_cdw0, ADM_CMD_DEL_IO_COMPLETION_QUEUE, 0 ; [TODO: Set CID to valid value]
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mov dword [esi + SQ_ENTRY.cdw0], eax
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mov ax, [qid]
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mov word [esi + SQ_ENTRY.cdw10], ax
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stdcall sqytdbl_write, [pci], [qid], 0 ; setting last param to 0 for now, change later
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pop esi
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ret
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endp
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; See page 114-116 of the NVMe 1.4 specification for reference
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proc get_features stdcall, pci:dword, dptr:dword, sel:byte, fid:byte
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push esi ebx
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mov esi, [pci]
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mov esi, [esi + pcidev.sq_ptr]
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stdcall memset, esi, 0, sizeof.SQ_ENTRY
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stdcall set_cdw0, ADM_CMD_GET_FEATURES, 0 ; [TODO: Set CID to valid value]
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mov dword [esi + SQ_ENTRY.cdw0], eax
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movzx eax, [fid] ; CDW10.FID
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movzx ebx, [sel]
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and ebx, 111b
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shl ebx, 8
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or eax, ebx ; CDW10.SEL
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mov dword [esi + SQ_ENTRY.cdw10], eax
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mov eax, [dptr]
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mov dword [esi + SQ_ENTRY.dptr], eax
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; TODO: Implement CDW14.UUID?
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stdcall sqytdbl_write, [pci], 0, 0
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pop ebx esi
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ret
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endp
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; See page 105-106 of the NVMe 1.4 specification for reference
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proc delete_io_submission_queue stdcall, pci:dword, qid:word
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push esi
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mov esi, [pci]
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mov esi, [esi + pcidev.sq_ptr]
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stdcall memset, esi, 0, sizeof.SQ_ENTRY
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stdcall set_cdw0, ADM_CMD_DEL_IO_SUBMISSION_QUEUE, 0 ; [TODO: Set CID to valid value]
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mov dword [esi + SQ_ENTRY.cdw0], eax
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mov ax, [qid]
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mov word [esi + SQ_ENTRY.cdw10], ax
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stdcall sqytdbl_write, [pci], [qid], 0 ; setting last param to 0 for now, change later
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pop esi
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ret
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endp
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; See page 117-118 of the NVMe 1.4 specification for reference
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; INCOMPLETE
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proc get_log_page stdcall, pci:dword, dptr:dword, lid:byte
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push esi
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mov esi, [pci]
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mov esi, [esi + pcidev.sq_ptr]
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stdcall memset, esi, 0, sizeof.SQ_ENTRY
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stdcall set_cdw0, ADM_CMD_GET_LOG_PAGE, 0 ; [TODO: Set CID to valid value]
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mov dword [esi + SQ_ENTRY.cdw0], eax
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mov eax, [dptr]
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mov dword [esi + SQ_ENTRY.dptr], eax
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pop esi
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ret
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endp
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proc detect_nvme
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invoke GetPCIList
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mov edx, eax
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.check_dev:
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mov ebx, dword [eax + PCIDEV.class]
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and ebx, 0x00ffff00 ; retrieve class/subclass code only
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cmp ebx, 0x00010800 ; Mass Storage Controller - Non-Volatile Memory Controller
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je .found_dev
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.next_dev:
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mov eax, dword [eax + PCIDEV.fd]
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cmp eax, edx
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jne .check_dev
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jmp .exit_success
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.found_dev:
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push edx eax
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PDEBUGF DBG_INFO, "PCI(%u.%u.%u): Detected NVMe device...\n", byte [eax + PCIDEV.bus], byte [eax + PCIDEV.devfn]
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cmp dword [pcidevs_len], TOTAL_PCIDEVS
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jne @f
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pop eax edx
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jmp .exit_success
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@@:
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inc dword [pcidevs_len]
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mov ebx, dword [p_nvme_devices]
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test ebx, ebx
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jnz @f
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invoke KernelAlloc, sizeof.pcidev
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test eax, eax
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jz .err_no_mem
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mov dword [p_nvme_devices], eax
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DEBUGF DBG_INFO, "(NVMe) Allocated pcidev struct at 0x%x\n", [p_nvme_devices]
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@@:
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mov ecx, dword [pcidevs_len]
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dec ecx
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pop eax
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mov ebx, dword [p_nvme_devices]
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movzx edx, byte [eax + PCIDEV.bus]
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mov byte [ebx + pcidev.bus], dl
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movzx edx, byte [eax + PCIDEV.devfn]
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mov byte [ebx + pcidev.devfn], dl
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pop edx
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jmp .next_dev
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.err_no_mem:
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pop eax edx
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xor eax, eax
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ret
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.exit_success:
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xor eax, eax
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inc eax
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ret
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endp
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proc device_is_compat stdcall, pci:dword
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push esi edx ecx
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mov esi, [pci]
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invoke PciRead8, dword [esi + pcidev.bus], dword [esi + pcidev.devfn], PCI_header00.interrupt_pin
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test eax, eax
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jz .failure
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mov byte [esi + pcidev.ipin], al
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;invoke PciRead16, dword [esi + pcidev.bus], dword [esi + pcidev.devfn], PCI_header.command
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;test eax, eax
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;jz .failure
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;DEBUGF DBG_INFO, "(NVMe) CMD: %x\n", eax
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invoke PciRead8, dword [esi + pcidev.bus], dword [esi + pcidev.devfn], PCI_header00.interrupt_line
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mov byte [esi + pcidev.iline], al
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invoke PciRead32, dword [esi + pcidev.bus], dword [esi + pcidev.devfn], PCI_header00.base_addr_0
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and eax, 0xfffffff0
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test eax, eax
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jz .failure
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mov edx, eax
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push edx
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invoke MapIoMem, eax, sizeof.NVME_MMIO, PG_SW+PG_NOCACHE
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test eax, eax
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jz .failure
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;DEBUGF DBG_INFO, "(NVMe) MMIO allocated at: 0x%x\n", eax
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mov dword [esi + pcidev.io_addr], eax
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mov eax, dword [eax + NVME_MMIO.CAP + 4]
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and eax, CAP_DSTRD
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mov byte [esi + pcidev.dstrd], al
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; 1003h + ((2y + 1) * (4 << CAP.DSTRD))
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mov eax, 4
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shl ax, cl
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mov ecx, NVM_ASQS
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shl ecx, 1
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inc ecx
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imul ecx, eax
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add ecx, 0x1003
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pop edx
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invoke MapIoMem, edx, ecx, PG_SW+PG_NOCACHE
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mov dword [esi + pcidev.io_addr], eax
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mov eax, dword [eax + NVME_MMIO.VS]
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DEBUGF DBG_INFO, "(NVMe) Controller version: 0x%x\n", eax
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mov dword [esi + pcidev.version], eax
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pop ecx edx esi
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xor eax, eax
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inc eax
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ret
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.failure:
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PDEBUGF DBG_INFO, "PCI(%u.%u.%u): something went wrong checking NVMe device compatibility\n", byte [esi + pcidev.bus], byte [esi + pcidev.devfn]
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pop ecx edx esi
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xor eax, eax
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ret
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endp
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; nvme_init: Initializes the NVMe controller
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proc nvme_init stdcall, pci:dword
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push ebx esi edi
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mov esi, dword [pci]
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mov edi, dword [esi + pcidev.io_addr]
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if 0
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mov eax, dword [edi + NVME_MMIO.CAP]
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DEBUGF DBG_INFO, "(NVMe) CAP (0-31): 0x%x\n", eax
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mov eax, dword [edi + NVME_MMIO.CAP + 4]
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DEBUGF DBG_INFO, "(NVMe) CAP (32-63): 0x%x\n", eax
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mov eax, dword [edi + NVME_MMIO.CC]
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DEBUGF DBG_INFO, "(NVMe) CC: 0x%x\n", eax
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mov eax, dword [edi + NVME_MMIO.CSTS]
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DEBUGF DBG_INFO, "(NVMe) CSTS: 0x%x\n", eax
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end if
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; For some reason, bit 7 (No I/O command set supported) is also set to 1 despite bit 0 (NVM command set)
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; being set to 1.. so I am not sure if bit 7 should be checked at all.. investigate later.
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mov eax, dword [edi + NVME_MMIO.CAP + 4]
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test eax, CAP_CSS_NVM_CMDSET
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jz .exit_fail
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|
; Reset controller before we configure it
|
|
stdcall nvme_controller_reset, edi
|
|
mov eax, dword [edi + NVME_MMIO.CAP + 4]
|
|
and eax, CAP_MPSMIN
|
|
shr eax, 16
|
|
cmp eax, NVM_MPS
|
|
jg .exit_fail
|
|
mov eax, dword [edi + NVME_MMIO.CAP + 4]
|
|
and eax, CAP_MPSMAX
|
|
shr eax, 20
|
|
cmp eax, NVM_MPS
|
|
jl .exit_fail
|
|
|
|
; Configure IOSQES, IOCQES, AMS, MPS, CSS
|
|
mov eax, dword [edi + NVME_MMIO.CC]
|
|
and eax, not (CC_AMS or CC_MPS or CC_CSS)
|
|
; CSS = 0 (NVM Command Set)
|
|
; AMS = 0 (Round Robin)
|
|
; MPS = 0 (4KiB Pages)
|
|
; IOSQES = 6 (64B)
|
|
; IOCQES = 4 (16B)
|
|
or eax, (4 shl 20) or (6 shl 16)
|
|
and dword [edi + NVME_MMIO.CC], eax
|
|
|
|
; Configure Admin Queue Attributes
|
|
mov eax, dword [edi + NVME_MMIO.AQA]
|
|
and eax, not (AQA_ASQS or AQA_ACQS)
|
|
or eax, NVM_ASQS or (NVM_ACQS shl 16)
|
|
mov dword [edi + NVME_MMIO.AQA], eax
|
|
|
|
; Configure Admin Submission/Completion Queue Base Address
|
|
invoke KernelAlloc, 0x1000
|
|
test eax, eax
|
|
jz .exit_fail
|
|
mov dword [esi + pcidev.sq_ptr], eax
|
|
invoke GetPhysAddr
|
|
mov dword [edi + NVME_MMIO.ASQ], eax
|
|
and dword [edi + NVME_MMIO.ASQ + 4], 0
|
|
invoke KernelAlloc, 0x1000
|
|
test eax, eax
|
|
jz .exit_fail
|
|
mov dword [esi + pcidev.cq_ptr], eax
|
|
invoke GetPhysAddr
|
|
mov dword [edi + NVME_MMIO.ACQ], eax
|
|
and dword [edi + NVME_MMIO.ACQ + 4], 0
|
|
|
|
stdcall memset, dword [esi + pcidev.sq_ptr], 0, sizeof.SQ_ENTRY * NVM_ASQS
|
|
stdcall memset, dword [esi + pcidev.cq_ptr], 0, sizeof.CQ_ENTRY * NVM_ACQS
|
|
|
|
; Allocate list of queues
|
|
invoke KernelAlloc, sizeof.NVM_QUEUE_ENTRY * NVM_ASQS
|
|
test eax, eax
|
|
jz .exit_fail
|
|
mov dword [esi + pcidev.queue_entries], eax
|
|
stdcall memset, eax, 0, sizeof.NVM_QUEUE_ENTRY * NVM_ASQS
|
|
|
|
; we want to disable all interrupts for now, since the controller randomly
|
|
; generates interrupts while starting up
|
|
mov dword [edi + NVME_MMIO.INTMS], 0xffffffff
|
|
|
|
; Attach interrupt handler
|
|
movzx eax, byte [esi + pcidev.iline]
|
|
DEBUGF DBG_INFO, "(NVMe) Attaching interrupt handler to IRQ %u\n", eax
|
|
invoke AttachIntHandler, eax, irq_handler, 0
|
|
test eax, eax
|
|
jz .exit_fail
|
|
DEBUGF DBG_INFO, "(NVMe) Successfully attached interrupt handler\n"
|
|
|
|
; Restart the controller
|
|
stdcall nvme_controller_start, edi
|
|
mov dword [edi + NVME_MMIO.INTMC], 0xffffffff ; re-enable interrupts
|
|
|
|
invoke KernelAlloc, 0x1000
|
|
test eax, eax
|
|
jz .exit_fail
|
|
mov dword [dptr], eax
|
|
invoke GetPhysAddr
|
|
mov ebx, eax
|
|
stdcall get_new_cid, [pci], 0
|
|
DEBUGF DBG_INFO, "(NVMe) Got Command Identifier: %u\n", eax
|
|
; pci:dword, nsid:dword, dptr:dword, cid:word, cns:byte
|
|
stdcall nvme_identify, [pci], 0, ebx, eax, CNS_IDCS
|
|
mov ebx, dword [esi + pcidev.cq_ptr]
|
|
|
|
; Wait until phase tag bit is set
|
|
@@:
|
|
test byte [ebx + CQ_ENTRY.status], CQ_PHASE_TAG
|
|
jz @b
|
|
mov edx, dword [dptr]
|
|
lea edx, byte [edx + IDENTC.sn]
|
|
lea eax, byte [esi + pcidev.serial]
|
|
stdcall memcpy, eax, edx, 20
|
|
DEBUGF DBG_INFO, "(NVMe) Serial Number: %s\n", eax
|
|
add edx, 20
|
|
lea eax, byte [esi + pcidev.model]
|
|
stdcall memcpy, eax, edx, 40
|
|
DEBUGF DBG_INFO, "(NVMe) Model: %s\n", eax
|
|
mov ebx, dword [esi + pcidev.version]
|
|
mov esi, dword [dptr]
|
|
|
|
cmp ebx, VS140
|
|
jl @f
|
|
; This is a reserved field in pre-1.4 controllers
|
|
mov al, byte [esi + IDENTC.cntrltype]
|
|
cmp al, CNTRLTYPE_IO_CONTROLLER
|
|
jne .exit_fail
|
|
DEBUGF DBG_INFO, "(NVMe) I/O controller detected...\n"
|
|
|
|
@@:
|
|
mov al, byte [esi + IDENTC.sqes]
|
|
and al, 11110000b
|
|
cmp al, 0x60 ; maximum submission queue size should at least be 64 bytes
|
|
jl .exit_fail
|
|
mov al, byte [esi + IDENTC.cqes]
|
|
and al, 11110000b
|
|
and al, 0x40 ; maximum completion queue entry size should at least be 16 bytes
|
|
jl .exit_fail
|
|
|
|
;DEBUGF DBG_INFO, "(NVMe) Successfully initialized driver!\n"
|
|
xor eax, eax
|
|
inc eax
|
|
pop edi esi ebx
|
|
ret
|
|
|
|
.exit_fail:
|
|
DEBUGF DBG_INFO, "(NVMe) failed to initialize controller\n"
|
|
xor eax, eax
|
|
pop edi esi ebx
|
|
ret
|
|
|
|
endp
|
|
|
|
proc get_new_cid stdcall, pci:dword, y:dword
|
|
|
|
push esi ebx
|
|
mov ecx, [y]
|
|
imul ecx, sizeof.NVM_QUEUE_ENTRY
|
|
mov esi, [pci]
|
|
mov esi, dword [esi + pcidev.queue_entries]
|
|
lea esi, dword [esi + ecx]
|
|
mov eax, dword [esi + NVM_QUEUE_ENTRY.cid_slots]
|
|
xor edx, edx
|
|
cmp eax, 0xffffffff
|
|
jne @f
|
|
mov eax, dword [esi + NVM_QUEUE_ENTRY.cid_slots + 4]
|
|
add edx, 4
|
|
cmp eax, 0xffffffff
|
|
jne @f
|
|
pop ebx esi
|
|
mov eax, -1
|
|
ret
|
|
|
|
@@:
|
|
mov ebx, eax
|
|
|
|
; Equivalant to (~(-X) & ~(X)), retrieves first free bit
|
|
not eax
|
|
mov ecx, eax
|
|
neg ecx
|
|
and eax, ecx
|
|
or ebx, eax
|
|
|
|
mov ecx, [y]
|
|
mov dword [esi + edx + NVM_QUEUE_ENTRY.cid_slots], ebx
|
|
bsf eax, eax
|
|
cmp edx, 4
|
|
jne @f
|
|
add eax, 32
|
|
|
|
@@:
|
|
pop ebx esi
|
|
ret
|
|
|
|
endp
|
|
|
|
proc nvme_controller_reset stdcall, mmio:dword
|
|
|
|
DEBUGF DBG_INFO, "(NVMe) Resetting Controller...\n"
|
|
push edi
|
|
mov edi, dword [mmio]
|
|
and dword [edi + NVME_MMIO.CC], 0xfffffffe ; CC.EN = 0
|
|
stdcall nvme_wait, [mmio]
|
|
|
|
; Wait for controller to be brought to idle state, CSTS.RDY should be cleared to 0 when this happens
|
|
.wait:
|
|
test dword [edi + NVME_MMIO.CSTS], CSTS_RDY
|
|
jnz .wait
|
|
DEBUGF DBG_INFO, "(NVMe) Successfully reset controller...\n"
|
|
pop edi
|
|
ret
|
|
|
|
endp
|
|
|
|
proc nvme_controller_start stdcall, mmio:dword
|
|
|
|
DEBUGF DBG_INFO, "(NVMe) Starting Controller...\n"
|
|
push edi
|
|
mov edi, dword [mmio]
|
|
or dword [edi + NVME_MMIO.CC], 1 ;; CC.EN = 1
|
|
stdcall nvme_wait, [mmio]
|
|
|
|
; Wait for controller to be brought into active state, CSTS.RDY should be set to 1 when this happens
|
|
.wait:
|
|
test dword [edi + NVME_MMIO.CSTS], CSTS_RDY
|
|
jz .wait
|
|
DEBUGF DBG_INFO, "(NVMe) Successfully started controller...\n"
|
|
pop edi
|
|
ret
|
|
|
|
endp
|
|
|
|
; Should be called only after the value of CC.EN has changed
|
|
proc nvme_wait stdcall, mmio:dword
|
|
|
|
push esi
|
|
mov esi, [mmio]
|
|
mov esi, dword [esi + NVME_MMIO.CAP]
|
|
and esi, CAP_TO
|
|
shr esi, 24
|
|
imul esi, 150 ; TODO: bad time delay, set to appropriate value later
|
|
invoke Sleep
|
|
pop esi
|
|
ret
|
|
|
|
endp
|
|
|
|
; Writes to submission queue 'y' tail doorbell
|
|
proc sqytdbl_write stdcall, pci:dword, y:byte, sqt:word
|
|
|
|
push ebx esi
|
|
mov esi, [pci]
|
|
|
|
; 1000h + (2y * (4 << CAP.DSTRD))
|
|
mov ecx, dword [esi + pcidev.dstrd]
|
|
mov eax, 4
|
|
shl eax, cl
|
|
mov cl, [y]
|
|
xor ebx, ebx
|
|
shl ebx, cl
|
|
imul ebx, eax
|
|
add ebx, 0x1000
|
|
DEBUGF DBG_INFO, "(NVMe) Writing to submission queue 0x%x doorbell register\n", ebx
|
|
|
|
mov esi, [esi + pcidev.io_addr]
|
|
mov ax, [sqt]
|
|
mov word [esi + ebx], ax ; Write to register
|
|
pop esi ebx
|
|
ret
|
|
|
|
endp
|
|
|
|
; Writes to completion queue 'y' head doorbell
|
|
proc cqyhdbl_write stdcall, pci:dword, y:byte, cqh:word
|
|
|
|
push esi edi
|
|
mov esi, [pci]
|
|
|
|
; 1000h + ((2y + 1) * (4 << CAP.DSTRD))
|
|
movzx eax, [y]
|
|
shl al, 1
|
|
inc al
|
|
mov edx, 4
|
|
mov cl, byte [esi + pcidev.dstrd]
|
|
shl dx, cl
|
|
imul dx, ax
|
|
add dx, 0x1000
|
|
movzx ecx, [y]
|
|
imul ecx, sizeof.NVM_QUEUE_ENTRY
|
|
mov edi, dword [esi + pcidev.queue_entries]
|
|
lea edi, dword [edi + ecx]
|
|
mov esi, dword [esi + pcidev.io_addr]
|
|
mov ax, [cqh]
|
|
DEBUGF DBG_INFO, "(NVMe) Writing to completion queue doorbell register 0x%x: %u\n", dx, ax
|
|
mov word [esi + edx], ax ; Write to CQyHDBL
|
|
mov word [edi + NVM_QUEUE_ENTRY.head], ax
|
|
pop edi esi
|
|
ret
|
|
|
|
endp
|
|
|
|
proc write_admin_cmd stdcall, pci:dword
|
|
|
|
push esi
|
|
mov esi, [pci]
|
|
mov esi, dword [esi + pcidev.queue_entries]
|
|
mov ax, word [esi + NVM_QUEUE_ENTRY.tail]
|
|
cmp ax, NVM_ASQS
|
|
xor ax, ax
|
|
|
|
@@:
|
|
mov esi, [pci]
|
|
mov esi, dword [esi + pcidev.io_addr]
|
|
inc ax
|
|
mov word [esi + 0x1000], ax
|
|
mov word [esi + NVM_QUEUE_ENTRY.tail], ax
|
|
pop esi
|
|
ret
|
|
|
|
endp
|
|
|
|
; Calculates 2^x
|
|
proc pow2 stdcall, x:byte
|
|
|
|
push ecx
|
|
mov cl, [x]
|
|
xor eax, eax
|
|
inc eax
|
|
test cl, cl
|
|
jnz @f
|
|
pop ecx
|
|
ret
|
|
|
|
@@:
|
|
shl eax, cl
|
|
pop ecx
|
|
ret
|
|
|
|
endp
|
|
|
|
proc irq_handler
|
|
|
|
push esi edi
|
|
mov esi, dword [p_nvme_devices]
|
|
mov edi, esi
|
|
mov esi, dword [esi + pcidev.io_addr]
|
|
mov edi, dword [edi + pcidev.cq_ptr]
|
|
mov dword [esi + NVME_MMIO.INTMS], 0x1
|
|
mov ax, word [edi + CQ_ENTRY.status]
|
|
and ax, not CQ_PHASE_TAG ; ignore phase tag bit
|
|
DEBUGF DBG_INFO, "(NVMe) Status: %x\n", ax
|
|
test al, al ; check status code (0 on success)
|
|
jz @f
|
|
|
|
; error occurred
|
|
|
|
; we have to initiate a controller reset if a admin command encounters
|
|
; a fatal error or if a completion is not received for a deletion
|
|
; of a submission or completion queue (section 10.1 - page 400 of NVMe 1.4 spec)
|
|
stdcall nvme_controller_reset, esi
|
|
stdcall nvme_controller_start, esi
|
|
jmp .exit
|
|
|
|
@@:
|
|
stdcall cqyhdbl_write, [p_nvme_devices], 0x0, 0x1
|
|
mov dword [esi + NVME_MMIO.INTMC], 0x1
|
|
|
|
.exit:
|
|
; Interrupt handled by driver, return 1
|
|
xor eax, eax
|
|
inc eax
|
|
pop edi esi
|
|
ret
|
|
|
|
endp
|
|
|
|
proc nvme_cleanup
|
|
|
|
DEBUGF DBG_INFO, "(NVMe): Cleaning up...\n"
|
|
mov ecx, dword [pcidevs_len]
|
|
mov eax, dword [p_nvme_devices]
|
|
test eax, eax
|
|
jnz .loop
|
|
ret
|
|
|
|
.loop:
|
|
;invoke KernelFree, dword [p_nvme_devices + ecx * sizeof.pcidev + pcidev.ident_ptr]
|
|
dec ecx
|
|
test ecx, ecx
|
|
jnz .loop
|
|
invoke KernelFree, dword [p_nvme_devices]
|
|
|
|
@@:
|
|
ret
|
|
|
|
endp
|
|
|
|
;all initialized data place here
|
|
align 4
|
|
p_nvme_devices dd 0
|
|
pcidevs_len dd 0
|
|
dptr dd ?
|
|
my_service db "NVMe",0 ;max 16 chars include zero
|
|
if __DEBUG__
|
|
include_debug_strings
|
|
end if
|
|
|
|
align 4
|
|
data fixups
|
|
end data
|