301 lines
12 KiB
C
301 lines
12 KiB
C
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#ifndef _INTEL_DRIVER_H_
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#define _INTEL_DRIVER_H_
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#include <stddef.h>
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#include <pthread.h>
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#include <signal.h>
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#include <drm.h>
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#include <i915_drm.h>
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#include <intel_bufmgr.h>
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#include <va/va_backend.h>
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#include "va_backend_compat.h"
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#include "intel_compiler.h"
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#define BATCH_SIZE 0x80000
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#define BATCH_RESERVED 0x10
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#define CMD_MI (0x0 << 29)
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#define CMD_2D (0x2 << 29)
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#define CMD_3D (0x3 << 29)
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#define MI_NOOP (CMD_MI | 0)
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#define MI_BATCH_BUFFER_END (CMD_MI | (0xA << 23))
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#define MI_BATCH_BUFFER_START (CMD_MI | (0x31 << 23))
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#define MI_FLUSH (CMD_MI | (0x4 << 23))
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#define MI_FLUSH_STATE_INSTRUCTION_CACHE_INVALIDATE (0x1 << 0)
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#define MI_FLUSH_DW (CMD_MI | (0x26 << 23) | 0x2)
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#define MI_FLUSH_DW_VIDEO_PIPELINE_CACHE_INVALIDATE (0x1 << 7)
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#define XY_COLOR_BLT_CMD (CMD_2D | (0x50 << 22) | 0x04)
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#define XY_COLOR_BLT_WRITE_ALPHA (1 << 21)
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#define XY_COLOR_BLT_WRITE_RGB (1 << 20)
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#define XY_COLOR_BLT_DST_TILED (1 << 11)
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/* BR13 */
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#define BR13_8 (0x0 << 24)
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#define BR13_565 (0x1 << 24)
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#define BR13_1555 (0x2 << 24)
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#define BR13_8888 (0x3 << 24)
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#define CMD_PIPE_CONTROL (CMD_3D | (3 << 27) | (2 << 24) | (0 << 16))
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#define CMD_PIPE_CONTROL_NOWRITE (0 << 14)
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#define CMD_PIPE_CONTROL_WRITE_QWORD (1 << 14)
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#define CMD_PIPE_CONTROL_WRITE_DEPTH (2 << 14)
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#define CMD_PIPE_CONTROL_WRITE_TIME (3 << 14)
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#define CMD_PIPE_CONTROL_DEPTH_STALL (1 << 13)
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#define CMD_PIPE_CONTROL_WC_FLUSH (1 << 12)
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#define CMD_PIPE_CONTROL_IS_FLUSH (1 << 11)
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#define CMD_PIPE_CONTROL_TC_FLUSH (1 << 10)
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#define CMD_PIPE_CONTROL_NOTIFY_ENABLE (1 << 8)
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#define CMD_PIPE_CONTROL_DC_FLUSH (1 << 5)
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#define CMD_PIPE_CONTROL_GLOBAL_GTT (1 << 2)
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#define CMD_PIPE_CONTROL_LOCAL_PGTT (0 << 2)
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#define CMD_PIPE_CONTROL_DEPTH_CACHE_FLUSH (1 << 0)
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struct intel_batchbuffer;
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#define ALIGN(i, n) (((i) + (n) - 1) & ~((n) - 1))
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#define MIN(a, b) ((a) < (b) ? (a) : (b))
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#define MAX(a, b) ((a) > (b) ? (a) : (b))
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#define ARRAY_ELEMS(a) (sizeof(a) / sizeof((a)[0]))
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#define Bool int
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#define True 1
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#define False 0
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#define SET_BLOCKED_SIGSET() do { \
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sigset_t bl_mask; \
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sigfillset(&bl_mask); \
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sigdelset(&bl_mask, SIGFPE); \
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sigdelset(&bl_mask, SIGILL); \
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sigdelset(&bl_mask, SIGSEGV); \
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sigdelset(&bl_mask, SIGBUS); \
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sigdelset(&bl_mask, SIGKILL); \
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pthread_sigmask(SIG_SETMASK, &bl_mask, &intel->sa_mask); \
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} while (0)
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#define RESTORE_BLOCKED_SIGSET() do { \
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pthread_sigmask(SIG_SETMASK, &intel->sa_mask, NULL); \
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} while (0)
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#define PPTHREAD_MUTEX_LOCK() do { \
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SET_BLOCKED_SIGSET(); \
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pthread_mutex_lock(&intel->ctxmutex); \
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} while (0)
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#define PPTHREAD_MUTEX_UNLOCK() do { \
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pthread_mutex_unlock(&intel->ctxmutex); \
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RESTORE_BLOCKED_SIGSET(); \
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} while (0)
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#define WARN_ONCE(...) do { \
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static int g_once = 1; \
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if (g_once) { \
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g_once = 0; \
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printf("WARNING: " __VA_ARGS__); \
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} \
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} while (0)
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struct intel_driver_data
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{
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int fd;
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int device_id;
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int revision;
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int dri2Enabled;
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sigset_t sa_mask;
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// pthread_mutex_t ctxmutex;
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int locked;
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dri_bufmgr *bufmgr;
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unsigned int has_exec2 : 1; /* Flag: has execbuffer2? */
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unsigned int has_bsd : 1; /* Flag: has bitstream decoder for H.264? */
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unsigned int has_blt : 1; /* Flag: has BLT unit? */
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};
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Bool intel_driver_init(VADriverContextP ctx);
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Bool intel_driver_terminate(VADriverContextP ctx);
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static INLINE struct intel_driver_data *
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intel_driver_data(VADriverContextP ctx)
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{
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return (struct intel_driver_data *)ctx->pDriverData;
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}
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struct intel_region
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{
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int x;
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int y;
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unsigned int width;
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unsigned int height;
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unsigned int cpp;
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unsigned int pitch;
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unsigned int tiling;
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unsigned int swizzle;
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dri_bo *bo;
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};
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#define PCI_CHIP_GM45_GM 0x2A42
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#define PCI_CHIP_IGD_E_G 0x2E02
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#define PCI_CHIP_Q45_G 0x2E12
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#define PCI_CHIP_G45_G 0x2E22
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#define PCI_CHIP_G41_G 0x2E32
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#define PCI_CHIP_B43_G 0x2E42
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#define PCI_CHIP_B43_G1 0x2E92
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#define PCI_CHIP_IRONLAKE_D_G 0x0042
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#define PCI_CHIP_IRONLAKE_M_G 0x0046
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#ifndef PCI_CHIP_SANDYBRIDGE_GT1
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#define PCI_CHIP_SANDYBRIDGE_GT1 0x0102 /* Desktop */
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#define PCI_CHIP_SANDYBRIDGE_GT2 0x0112
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#define PCI_CHIP_SANDYBRIDGE_GT2_PLUS 0x0122
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#define PCI_CHIP_SANDYBRIDGE_M_GT1 0x0106 /* Mobile */
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#define PCI_CHIP_SANDYBRIDGE_M_GT2 0x0116
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#define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126
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#define PCI_CHIP_SANDYBRIDGE_S_GT 0x010A /* Server */
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#endif
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#define PCI_CHIP_IVYBRIDGE_GT1 0x0152 /* Desktop */
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#define PCI_CHIP_IVYBRIDGE_GT2 0x0162
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#define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156 /* Mobile */
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#define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166
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#define PCI_CHIP_IVYBRIDGE_S_GT1 0x015a /* Server */
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#define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a
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#define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */
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#define PCI_CHIP_HASWELL_GT2 0x0412
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#define PCI_CHIP_HASWELL_GT2_PLUS 0x0422
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#define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */
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#define PCI_CHIP_HASWELL_M_GT2 0x0416
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#define PCI_CHIP_HASWELL_M_GT2_PLUS 0x0426
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#define PCI_CHIP_HASWELL_S_GT1 0x040a /* Server */
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#define PCI_CHIP_HASWELL_S_GT2 0x041a
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#define PCI_CHIP_HASWELL_S_GT2_PLUS 0x042a
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#define PCI_CHIP_HASWELL_SDV_GT1 0x0c02 /* Desktop */
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#define PCI_CHIP_HASWELL_SDV_GT2 0x0c12
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#define PCI_CHIP_HASWELL_SDV_GT2_PLUS 0x0c22
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#define PCI_CHIP_HASWELL_SDV_M_GT1 0x0c06 /* Mobile */
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#define PCI_CHIP_HASWELL_SDV_M_GT2 0x0c16
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#define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS 0x0c26
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#define PCI_CHIP_HASWELL_SDV_S_GT1 0x0c0a /* Server */
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#define PCI_CHIP_HASWELL_SDV_S_GT2 0x0c1a
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#define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS 0x0c2a
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#define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */
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#define PCI_CHIP_HASWELL_ULT_GT2 0x0A12
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#define PCI_CHIP_HASWELL_ULT_GT2_PLUS 0x0A22
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#define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */
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#define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16
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#define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS 0x0A26
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#define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */
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#define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
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#define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A
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#define PCI_CHIP_HASWELL_CRW_GT1 0x0D12 /* Desktop */
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#define PCI_CHIP_HASWELL_CRW_GT2 0x0D22
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#define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D32
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#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D16 /* Mobile */
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#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D26
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#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D36
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#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D1A /* Server */
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#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D2A
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#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A
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#define IS_G45(devid) (devid == PCI_CHIP_IGD_E_G || \
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devid == PCI_CHIP_Q45_G || \
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devid == PCI_CHIP_G45_G || \
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devid == PCI_CHIP_G41_G || \
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devid == PCI_CHIP_B43_G || \
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devid == PCI_CHIP_B43_G1)
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#define IS_GM45(devid) (devid == PCI_CHIP_GM45_GM)
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#define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid))
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#define IS_IRONLAKE_D(devid) (devid == PCI_CHIP_IRONLAKE_D_G)
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#define IS_IRONLAKE_M(devid) (devid == PCI_CHIP_IRONLAKE_M_G)
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#define IS_IRONLAKE(devid) (IS_IRONLAKE_D(devid) || IS_IRONLAKE_M(devid))
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#define IS_SNB_GT1(devid) (devid == PCI_CHIP_SANDYBRIDGE_GT1 || \
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devid == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
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devid == PCI_CHIP_SANDYBRIDGE_S_GT)
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#define IS_SNB_GT2(devid) (devid == PCI_CHIP_SANDYBRIDGE_GT2 || \
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devid == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
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devid == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
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devid == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS)
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#define IS_GEN6(devid) (IS_SNB_GT1(devid) || \
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IS_SNB_GT2(devid))
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#define IS_IVB_GT1(devid) (devid == PCI_CHIP_IVYBRIDGE_GT1 || \
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devid == PCI_CHIP_IVYBRIDGE_M_GT1 || \
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devid == PCI_CHIP_IVYBRIDGE_S_GT1)
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#define IS_IVB_GT2(devid) (devid == PCI_CHIP_IVYBRIDGE_GT2 || \
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devid == PCI_CHIP_IVYBRIDGE_M_GT2 || \
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devid == PCI_CHIP_IVYBRIDGE_S_GT2)
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#define IS_IVYBRIDGE(devid) (IS_IVB_GT1(devid) || \
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IS_IVB_GT2(devid))
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#define IS_HSW_GT1(devid) (devid == PCI_CHIP_HASWELL_GT1 || \
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devid == PCI_CHIP_HASWELL_M_GT1 || \
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devid == PCI_CHIP_HASWELL_S_GT1 || \
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devid == PCI_CHIP_HASWELL_SDV_GT1 || \
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devid == PCI_CHIP_HASWELL_SDV_M_GT1 || \
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devid == PCI_CHIP_HASWELL_SDV_S_GT1 || \
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devid == PCI_CHIP_HASWELL_CRW_GT1 || \
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devid == PCI_CHIP_HASWELL_CRW_M_GT1 || \
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devid == PCI_CHIP_HASWELL_CRW_S_GT1 || \
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devid == PCI_CHIP_HASWELL_ULT_GT1 || \
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devid == PCI_CHIP_HASWELL_ULT_M_GT1 || \
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devid == PCI_CHIP_HASWELL_ULT_S_GT1)
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#define IS_HSW_GT2(devid) (devid == PCI_CHIP_HASWELL_GT2|| \
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devid == PCI_CHIP_HASWELL_M_GT2|| \
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devid == PCI_CHIP_HASWELL_S_GT2|| \
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devid == PCI_CHIP_HASWELL_SDV_GT2|| \
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devid == PCI_CHIP_HASWELL_SDV_M_GT2|| \
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devid == PCI_CHIP_HASWELL_SDV_S_GT2|| \
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devid == PCI_CHIP_HASWELL_CRW_GT2|| \
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devid == PCI_CHIP_HASWELL_CRW_M_GT2|| \
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devid == PCI_CHIP_HASWELL_CRW_S_GT2|| \
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devid == PCI_CHIP_HASWELL_ULT_GT2|| \
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devid == PCI_CHIP_HASWELL_ULT_GT2_PLUS|| \
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devid == PCI_CHIP_HASWELL_ULT_M_GT2|| \
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devid == PCI_CHIP_HASWELL_ULT_M_GT2_PLUS|| \
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devid == PCI_CHIP_HASWELL_ULT_S_GT2 || \
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devid == PCI_CHIP_HASWELL_ULT_S_GT2_PLUS || \
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devid == PCI_CHIP_HASWELL_GT2_PLUS|| \
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devid == PCI_CHIP_HASWELL_M_GT2_PLUS || \
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devid == PCI_CHIP_HASWELL_S_GT2_PLUS || \
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devid == PCI_CHIP_HASWELL_SDV_GT2_PLUS|| \
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devid == PCI_CHIP_HASWELL_SDV_M_GT2_PLUS|| \
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devid == PCI_CHIP_HASWELL_SDV_S_GT2_PLUS|| \
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devid == PCI_CHIP_HASWELL_CRW_GT2_PLUS|| \
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devid == PCI_CHIP_HASWELL_CRW_M_GT2_PLUS|| \
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devid == PCI_CHIP_HASWELL_CRW_S_GT2_PLUS)
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#define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \
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IS_HSW_GT2(devid))
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#define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \
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IS_HASWELL(devid))
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#ifndef I915_EXEC_VEBOX
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||
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#define I915_EXEC_VEBOX 4
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||
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#endif
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||
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||
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#endif /* _INTEL_DRIVER_H_ */
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