125 lines
4.2 KiB
C
125 lines
4.2 KiB
C
#ifndef INTEL_DRIVER_H
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#define INTEL_DRIVER_H
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#define INTEL_VERSION 4000
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#define INTEL_NAME "intel"
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#define INTEL_DRIVER_NAME "intel"
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#define INTEL_VERSION_MAJOR PACKAGE_VERSION_MAJOR
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#define INTEL_VERSION_MINOR PACKAGE_VERSION_MINOR
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#define INTEL_VERSION_PATCH PACKAGE_VERSION_PATCHLEVEL
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#define PCI_CHIP_I810 0x7121
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#define PCI_CHIP_I810_DC100 0x7123
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#define PCI_CHIP_I810_E 0x7125
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#define PCI_CHIP_I815 0x1132
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#define PCI_CHIP_I830_M 0x3577
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#define PCI_CHIP_845_G 0x2562
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#define PCI_CHIP_I854 0x358E
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#define PCI_CHIP_I855_GM 0x3582
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#define PCI_CHIP_I865_G 0x2572
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#define PCI_CHIP_I915_G 0x2582
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#define PCI_CHIP_I915_GM 0x2592
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#define PCI_CHIP_E7221_G 0x258A
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#define PCI_CHIP_I945_G 0x2772
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#define PCI_CHIP_I945_GM 0x27A2
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#define PCI_CHIP_I945_GME 0x27AE
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#define PCI_CHIP_PINEVIEW_M 0xA011
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#define PCI_CHIP_PINEVIEW_G 0xA001
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#define PCI_CHIP_Q35_G 0x29B2
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#define PCI_CHIP_G33_G 0x29C2
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#define PCI_CHIP_Q33_G 0x29D2
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#define PCI_CHIP_G35_G 0x2982
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#define PCI_CHIP_I965_Q 0x2992
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#define PCI_CHIP_I965_G 0x29A2
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#define PCI_CHIP_I946_GZ 0x2972
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#define PCI_CHIP_I965_GM 0x2A02
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#define PCI_CHIP_I965_GME 0x2A12
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#define PCI_CHIP_GM45_GM 0x2A42
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#define PCI_CHIP_G45_E_G 0x2E02
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#define PCI_CHIP_G45_G 0x2E22
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#define PCI_CHIP_Q45_G 0x2E12
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#define PCI_CHIP_G41_G 0x2E32
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#define PCI_CHIP_B43_G 0x2E42
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#define PCI_CHIP_B43_G1 0x2E92
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#define PCI_CHIP_IRONLAKE_D_G 0x0042
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#define PCI_CHIP_IRONLAKE_M_G 0x0046
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#define PCI_CHIP_SANDYBRIDGE_GT1 0x0102
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#define PCI_CHIP_SANDYBRIDGE_GT2 0x0112
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#define PCI_CHIP_SANDYBRIDGE_GT2_PLUS 0x0122
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#define PCI_CHIP_SANDYBRIDGE_M_GT1 0x0106
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#define PCI_CHIP_SANDYBRIDGE_M_GT2 0x0116
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#define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126
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#define PCI_CHIP_SANDYBRIDGE_S_GT 0x010A
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#define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156
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#define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166
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#define PCI_CHIP_IVYBRIDGE_D_GT1 0x0152
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#define PCI_CHIP_IVYBRIDGE_D_GT2 0x0162
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#define PCI_CHIP_IVYBRIDGE_S_GT1 0x015a
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#define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a
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#define PCI_CHIP_HASWELL_D_GT1 0x0402
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#define PCI_CHIP_HASWELL_D_GT2 0x0412
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#define PCI_CHIP_HASWELL_D_GT3 0x0422
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#define PCI_CHIP_HASWELL_M_GT1 0x0406
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#define PCI_CHIP_HASWELL_M_GT2 0x0416
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#define PCI_CHIP_HASWELL_M_GT3 0x0426
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#define PCI_CHIP_HASWELL_S_GT1 0x040A
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#define PCI_CHIP_HASWELL_S_GT2 0x041A
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#define PCI_CHIP_HASWELL_S_GT3 0x042A
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#define PCI_CHIP_HASWELL_B_GT1 0x040B
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#define PCI_CHIP_HASWELL_B_GT2 0x041B
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#define PCI_CHIP_HASWELL_B_GT3 0x042B
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#define PCI_CHIP_HASWELL_E_GT1 0x040E
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#define PCI_CHIP_HASWELL_E_GT2 0x041E
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#define PCI_CHIP_HASWELL_E_GT3 0x042E
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#define PCI_CHIP_HASWELL_ULT_D_GT1 0x0A02
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#define PCI_CHIP_HASWELL_ULT_D_GT2 0x0A12
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#define PCI_CHIP_HASWELL_ULT_D_GT3 0x0A22
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#define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06
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#define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16
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#define PCI_CHIP_HASWELL_ULT_M_GT3 0x0A26
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#define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A
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#define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
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#define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A
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#define PCI_CHIP_HASWELL_ULT_B_GT1 0x0A0B
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#define PCI_CHIP_HASWELL_ULT_B_GT2 0x0A1B
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#define PCI_CHIP_HASWELL_ULT_B_GT3 0x0A2B
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#define PCI_CHIP_HASWELL_ULT_E_GT1 0x0A0E
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#define PCI_CHIP_HASWELL_ULT_E_GT2 0x0A1E
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#define PCI_CHIP_HASWELL_ULT_E_GT3 0x0A2E
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#define PCI_CHIP_HASWELL_CRW_D_GT1 0x0D02
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#define PCI_CHIP_HASWELL_CRW_D_GT2 0x0D12
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#define PCI_CHIP_HASWELL_CRW_D_GT3 0x0D22
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#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06
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#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16
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#define PCI_CHIP_HASWELL_CRW_M_GT3 0x0D26
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#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A
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#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A
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#define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A
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#define PCI_CHIP_HASWELL_CRW_B_GT1 0x0D0B
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#define PCI_CHIP_HASWELL_CRW_B_GT2 0x0D1B
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#define PCI_CHIP_HASWELL_CRW_B_GT3 0x0D2B
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#define PCI_CHIP_HASWELL_CRW_E_GT1 0x0D0E
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#define PCI_CHIP_HASWELL_CRW_E_GT2 0x0D1E
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#define PCI_CHIP_HASWELL_CRW_E_GT3 0x0D2E
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struct intel_device_info {
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int gen;
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};
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//void intel_detect_chipset(ScrnInfoPtr scrn,
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// EntityInfoPtr ent,
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// struct pci_device *pci);
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#endif /* INTEL_DRIVER_H */
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