intel-2D: 1)Broadwater/Crestline

2) write full debug log

git-svn-id: svn://kolibrios.org@3291 a494cfbc-eb01-0410-851d-a64ba20cac60

drivers/video/Intel-2D/compiler.h

@@ -38,6 +38,7 @@
 #define constant __attribute__((const))
 #define pure __attribute__((pure))
 #define __packed__ __attribute__((__packed__))
+#define flatten __attribute__((flatten))
 #else
 #define likely(expr) (expr)
 #define unlikely(expr) (expr)
@@ -48,6 +49,7 @@
 #define constant
 #define pure
 #define __packed__
+#define flatten
 #endif
 
 #ifdef HAVE_VALGRIND

drivers/video/Intel-2D/gen5_render.c

@@ -1062,7 +1062,6 @@ gen5_blit_tex(struct sna *sna,
 	gen5_align_vertex(sna, tmp);
 	return true;
 
-	return false;
 }
 
 
@@ -1407,5 +1406,7 @@ bool gen5_render_init(struct sna *sna)
 
 	sna->render.max_3d_size = MAX_3D_SIZE;
 	sna->render.max_3d_pitch = 1 << 18;
+    sna->render.caps = HW_BIT_BLIT | HW_TEX_BLIT;
+	
 	return true;
 }

drivers/video/Intel-2D/gen6_render.c

@@ -42,7 +42,7 @@
 
 #include "brw/brw.h"
 #include "gen6_render.h"
-
+#include "gen4_source.h"
 #include "gen4_vertex.h"
 
 #define NO_COMPOSITE 0
@@ -209,12 +209,12 @@ static uint32_t gen6_get_blend(int op,
 {
 	uint32_t src, dst;
 
-//    src = GEN6_BLENDFACTOR_ONE; //gen6_blend_op[op].src_blend;
-//    dst = GEN6_BLENDFACTOR_ZERO; //gen6_blend_op[op].dst_blend;
 
     src = GEN6_BLENDFACTOR_ONE; //gen6_blend_op[op].src_blend;
     dst = GEN6_BLENDFACTOR_INV_SRC_ALPHA; //gen6_blend_op[op].dst_blend;
 
+//    dst = GEN6_BLENDFACTOR_ZERO; //gen6_blend_op[op].dst_blend;
+
 #if 0
 	/* If there's no dst alpha channel, adjust the blend op so that
 	 * we'll treat it always as 1.
@@ -1836,10 +1836,6 @@ static void gen6_render_composite_done(struct sna *sna,
         gen6_magic_ca_pass(sna, op);
     }
 
-	if (op->mask.bo)
-		kgem_bo_destroy(&sna->kgem, op->mask.bo);
-	if (op->src.bo)
-		kgem_bo_destroy(&sna->kgem, op->src.bo);
 
 //   sna_render_composite_redirect_done(sna, op);
 }
@@ -2708,8 +2704,7 @@ gen6_blit_tex(struct sna *sna,
     tmp->dst.format = PICT_x8r8g8b8;
 
 
-	tmp->src.repeat = RepeatNone;
+	tmp->src.repeat = SAMPLER_EXTEND_NONE;
-	tmp->src.filter = PictFilterNearest;
     tmp->src.is_affine = true;
 
     tmp->src.bo = src_bo;
@@ -2718,6 +2713,12 @@ gen6_blit_tex(struct sna *sna,
     tmp->src.width  = src->drawable.width;
     tmp->src.height = src->drawable.height;
 
+	if ( (tmp->src.width  == width) &&
+         (tmp->src.height == height) )
+		tmp->src.filter = SAMPLER_FILTER_NEAREST;
+	else
+		tmp->src.filter = SAMPLER_FILTER_BILINEAR;
+
 	tmp->is_affine = tmp->src.is_affine;
 	tmp->has_component_alpha = false;
 	tmp->need_magic_ca_pass = false;
@@ -3494,6 +3495,8 @@ bool gen6_render_init(struct sna *sna)
 
     sna->render.max_3d_size = GEN6_MAX_SIZE;
     sna->render.max_3d_pitch = 1 << 18;
+    sna->render.caps = HW_BIT_BLIT | HW_TEX_BLIT;
+    
 	return true;
 }
 

drivers/video/Intel-2D/gen7_render.c

@@ -255,6 +255,7 @@ static uint32_t gen7_get_blend(int op,
     src = GEN7_BLENDFACTOR_ONE; //gen6_blend_op[op].src_blend;
     dst = GEN7_BLENDFACTOR_INV_SRC_ALPHA; //gen6_blend_op[op].dst_blend;
 
+
 #if 0
 	/* If there's no dst alpha channel, adjust the blend op so that
 	 * we'll treat it always as 1.
@@ -1357,6 +1358,14 @@ gen7_align_vertex(struct sna *sna, const struct sna_composite_op *op)
 	}
 }
 
+fastcall static void
+gen7_render_composite_blt(struct sna *sna,
+			  const struct sna_composite_op *op,
+			  const struct sna_composite_rectangles *r)
+{
+	gen7_get_rectangles(sna, op, 1, gen7_emit_composite_state);
+	op->prim_emit(sna, op, r);
+}
 static uint32_t
 gen7_composite_create_blend_state(struct sna_static_stream *stream)
 {
@@ -1390,14 +1399,6 @@ gen7_composite_create_blend_state(struct sna_static_stream *stream)
 }
 
 
-fastcall static void
-gen7_render_composite_blt(struct sna *sna,
-			  const struct sna_composite_op *op,
-			  const struct sna_composite_rectangles *r)
-{
-	gen7_get_rectangles(sna, op, 1, gen7_emit_composite_state);
-	op->prim_emit(sna, op, r);
-}
 
 static void gen7_render_composite_done(struct sna *sna,
 				       const struct sna_composite_op *op)
@@ -1502,6 +1503,93 @@ gen7_blit_tex(struct sna *sna,
 
 
 
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
 static void gen7_render_flush(struct sna *sna)
 {
 	gen4_vertex_close(sna);
@@ -1510,8 +1598,6 @@ static void gen7_render_flush(struct sna *sna)
 	assert(sna->render.vertex_offset == 0);
 }
 
-
-
 static void
 gen7_render_context_switch(struct kgem *kgem,
 			   int new_mode)
@@ -1593,7 +1679,6 @@ static bool is_mobile(struct sna *sna)
 	return (DEVICE_ID(sna->PciInfo) & 0xf) == 0x6;
 }
 
-
 static bool gen7_render_setup(struct sna *sna)
 {
     struct gen7_render_state *state = &sna->render_state.gen7;
@@ -1680,7 +1765,6 @@ static bool gen7_render_setup(struct sna *sna)
     return state->general_bo != NULL;
 }
 
-
 bool gen7_render_init(struct sna *sna)
 {
     if (!gen7_render_setup(sna))
@@ -1698,6 +1782,8 @@ bool gen7_render_init(struct sna *sna)
 
     sna->render.max_3d_size = GEN7_MAX_SIZE;
     sna->render.max_3d_pitch = 1 << 18;
+    sna->render.caps = HW_BIT_BLIT | HW_TEX_BLIT;
+    
     return true;
 }
 

drivers/video/Intel-2D/i915_drm.h

@@ -944,6 +944,8 @@ struct drm_i915_reg_read {
 
 struct drm_i915_mask_update {
     __u32 handle;
+    __u32 width;
+    __u32 height;
     __u32 bo_size;
     __u32 bo_pitch;  
     __u32 bo_map;

drivers/video/Intel-2D/kgem-sna.c

@@ -32,6 +32,18 @@
 #include "sna.h"
 #include "sna_reg.h"
 
+static inline
+int user_free(void *mem)
+{
+    int  val;
+    __asm__ __volatile__(
+    "int $0x40"
+    :"=a"(val)
+    :"a"(68),"b"(12),"c"(mem));
+    return val;
+}
+
+
 
 unsigned int cpu_cache_size();
 
@@ -969,7 +981,7 @@ void kgem_init(struct kgem *kgem, int fd, struct pci_device *dev, unsigned gen)
     DBG(("%s: maximum batch size? %d\n", __FUNCTION__,
          kgem->batch_size));
 
-    kgem->min_alignment = 4;
+    kgem->min_alignment = 16;
     if (gen < 040)
         kgem->min_alignment = 64;
 
@@ -1315,7 +1327,7 @@ static void kgem_bo_release_map(struct kgem *kgem, struct kgem_bo *bo)
 	     bo->handle, kgem->vma[type].count));
 
 	VG(if (type) VALGRIND_MAKE_MEM_NOACCESS(MAP(bo->map), bytes(bo)));
-//	munmap(MAP(bo->map), bytes(bo));
+	user_free(MAP(bo->map));
 	bo->map = NULL;
 
 	if (!list_is_empty(&bo->vma)) {
@@ -1327,6 +1339,8 @@ static void kgem_bo_release_map(struct kgem *kgem, struct kgem_bo *bo)
 static void kgem_bo_free(struct kgem *kgem, struct kgem_bo *bo)
 {
 	DBG(("%s: handle=%d\n", __FUNCTION__, bo->handle));
+	printf("%s: handle=%d\n", __FUNCTION__, bo->handle);
+
 	assert(bo->refcnt == 0);
 	assert(bo->exec == NULL);
 	assert(!bo->snoop || bo->rq == NULL);
@@ -1587,6 +1601,8 @@ static void __kgem_bo_destroy(struct kgem *kgem, struct kgem_bo *bo)
 {
 	DBG(("%s: handle=%d\n", __FUNCTION__, bo->handle));
 
+	printf("%s: handle=%d\n", __FUNCTION__, bo->handle);
+		
 	assert(list_is_empty(&bo->list));
 	assert(bo->refcnt == 0);
 	assert(!bo->purged);
@@ -4198,7 +4214,18 @@ int kgem_init_fb(struct kgem *kgem, struct sna_fb *fb)
     return 1;
 };
 
-
+void kgem_close_batches(struct kgem *kgem)
+{
+    int n;
+
+	for (n = 0; n < ARRAY_SIZE(kgem->pinned_batches); n++) {
+		while (!list_is_empty(&kgem->pinned_batches[n])) {
+			kgem_bo_destroy(kgem,
+					list_first_entry(&kgem->pinned_batches[n],
+							 struct kgem_bo, list));
+		}
+	}
+};
 
 
 

drivers/video/Intel-2D/kgem.h

@@ -28,7 +28,7 @@
 #ifndef KGEM_H
 #define KGEM_H
 
-#define HAS_DEBUG_FULL 0
+#define HAS_DEBUG_FULL 1
 
 #include <stdint.h>
 #include <stdbool.h>

drivers/video/Intel-2D/sna.c

@@ -10,6 +10,16 @@
 static struct sna_fb sna_fb;
 static struct kgem_bo *mask_bo;
 
+static int mask_width, mask_height;
+
+static inline void delay(uint32_t time)
+{
+    __asm__ __volatile__(
+    "int $0x40"
+    ::"a"(5), "b"(time)
+    :"memory");
+};
+
 typedef struct __attribute__((packed))
 {
   unsigned      handle;
@@ -96,7 +106,7 @@ void sna_vertex_init(struct sna *sna)
     sna->render.active = 0;
 }
 
-bool sna_accel_init(struct sna *sna)
+int sna_accel_init(struct sna *sna)
 {
     const char *backend;
 
@@ -122,15 +132,12 @@ bool sna_accel_init(struct sna *sna)
 	} else if (sna->info->gen >= 050) {
 		if (gen5_render_init(sna))
 			backend = "Ironlake";
-/*	} else if (sna->info->gen >= 040) {
+	} else if (sna->info->gen >= 040) {
 		if (gen4_render_init(sna))
 			backend = "Broadwater/Crestline";
-	} else if (sna->info->gen >= 030) {
+/*	} else if (sna->info->gen >= 030) {
 		if (gen3_render_init(sna))
-			backend = "gen3";
+			backend = "gen3"; */
-	} else if (sna->info->gen >= 020) {
-		if (gen2_render_init(sna))
-			backend = "gen2"; */
 	}
 
 	DBG(("%s(backend=%s, prefer_gpu=%x)\n",
@@ -156,9 +163,11 @@ int sna_init(uint32_t service)
 
     DBG(("%s\n", __FUNCTION__));
 
-    sna = malloc(sizeof(struct sna));
+    sna = malloc(sizeof(*sna));
     if (sna == NULL)
-        return false;
+        return 0;
+
+    memset(sna, 0, sizeof(*sna));
     
     io.handle   = service;
     io.io_code  = SRV_GET_PCI_INFO;
@@ -168,13 +177,18 @@ int sna_init(uint32_t service)
     io.out_size = 0;
 
     if (call_service(&io)!=0)
-        return false;
+    {
+        free(sna); 
+        return 0;
+    };
     
     sna->PciInfo = &device;
 
   	sna->info = intel_detect_chipset(sna->PciInfo);
 
     kgem_init(&sna->kgem, service, sna->PciInfo, sna->info->gen);
+    
+    delay(10);
 /*
     if (!xf86ReturnOptValBool(sna->Options,
                   OPTION_RELAXED_FENCING,
@@ -202,7 +216,22 @@ int sna_init(uint32_t service)
 
     sna->flags = 0;
 
-    return sna_accel_init(sna);
+    sna_accel_init(sna);
+
+    delay(10);
+    
+    return sna->render.caps;
+}
+
+void sna_fini()
+{
+    if( sna_device )
+    {
+        sna_device->render.fini(sna_device);
+        kgem_bo_destroy(&sna_device->kgem, mask_bo);
+        kgem_close_batches(&sna_device->kgem);        
+   	    kgem_cleanup_cache(&sna_device->kgem);
+    };
 }
 
 #if 0
@@ -411,6 +440,16 @@ err_1:
            
 };
 
+void sna_destroy_bitmap(bitmap_t *bitmap)
+{
+	struct kgem_bo *bo;
+    
+    bo = (struct kgem_bo *)bitmap->handle;
+        
+    kgem_bo_destroy(&sna_device->kgem, bo);
+
+};
+
 void sna_lock_bitmap(bitmap_t *bitmap)
 {
 	struct kgem_bo *bo;
@@ -424,18 +463,12 @@ void sna_lock_bitmap(bitmap_t *bitmap)
 int sna_create_mask()
 {
 	struct kgem_bo *bo;
-    char proc_info[1024];
     int width, height;
     int i;
 
-    get_proc_info(proc_info);
+    printf("%s width %d height %d\n", __FUNCTION__, sna_fb.width, sna_fb.height);
     
-    width  = *(uint32_t*)(proc_info+42)+1;
+    bo = kgem_create_2d(&sna_device->kgem, sna_fb.width, sna_fb.height,
-    height = *(uint32_t*)(proc_info+46)+1;
-    
-    printf("%s width %d height %d\n", __FUNCTION__, width, height);
-    
-    bo = kgem_create_2d(&sna_device->kgem, width, height,
                         8,I915_TILING_NONE, CREATE_CPU_MAP);
     
     if(bo == NULL)
@@ -448,6 +481,8 @@ int sna_create_mask()
     memset(map, 0, bo->pitch * height);
     
     mask_bo     = bo;
+    mask_width  = width;
+    mask_height = height;
     
     return 0;
     
@@ -504,6 +539,14 @@ int sna_blit_tex(bitmap_t *src_bitmap, int dst_x, int dst_y,
     winw = *(uint32_t*)(proc_info+42)+1;
     winh = *(uint32_t*)(proc_info+46)+1;
     
+    VG_CLEAR(update);
+	update.handle = mask_bo->handle;
+//	update.bo_size   = __kgem_bo_size(mask_bo);
+//	update.bo_pitch  = mask_bo->pitch;
+	update.bo_map    = (__u32)MAP(mask_bo->map);
+	drmIoctl(sna_device->kgem.fd, SRV_MASK_UPDATE, &update);
+    mask_bo->pitch = update.bo_pitch;
+    
     memset(&src, 0, sizeof(src));
     memset(&dst, 0, sizeof(dst));
     memset(&mask, 0, sizeof(dst));
@@ -517,8 +560,8 @@ int sna_blit_tex(bitmap_t *src_bitmap, int dst_x, int dst_y,
     dst.drawable.height = sna_fb.height;
     
     mask.drawable.bitsPerPixel = 8;
-    mask.drawable.width  = winw;
+    mask.drawable.width  = update.width;
-    mask.drawable.height = winh;
+    mask.drawable.height = update.height;
 
     memset(&composite, 0, sizeof(composite));
 
@@ -550,13 +593,6 @@ int sna_blit_tex(bitmap_t *src_bitmap, int dst_x, int dst_y,
         composite.done(sna_device, &composite);
     };
     
-    VG_CLEAR(update);
-	update.handle = mask_bo->handle;
-	update.bo_size   = __kgem_bo_size(mask_bo);
-	update.bo_pitch  = mask_bo->pitch;
-	update.bo_map    = MAP(mask_bo->map);
-	drmIoctl(sna_device->kgem.fd, SRV_MASK_UPDATE, &update);
-
     kgem_submit(&sna_device->kgem);
  
     return 0;            

drivers/video/Intel-2D/sna.h

@@ -134,6 +134,10 @@ typedef enum _PictFormatShort {
 /* 4bpp formats */
 } PictFormatShort;
 
+#define PIXMAN_FORMAT_A(f)	(((f) >> 12) & 0x0f)
+
+#define PICT_FORMAT_A(f)	PIXMAN_FORMAT_A(f)
+
 #define RepeatNone                          0
 #define RepeatNormal                        1
 #define RepeatPad                           2

drivers/video/Intel-2D/sna_reg.h

@@ -51,6 +51,7 @@
 #define XY_TEXT_IMMEDIATE_BLT		((2<<29)|(0x31<<22)|(1<<16))
 #define XY_SRC_COPY_BLT_CMD		((2<<29)|(0x53<<22)|6)
 #define SRC_COPY_BLT_CMD		((2<<29)|(0x43<<22)|0x4)
+#define XY_PAT_BLT			((2<<29)|(0x51<<22)|0x4)
 #define XY_PAT_BLT_IMMEDIATE		((2<<29)|(0x72<<22))
 #define XY_MONO_PAT			((0x2<<29)|(0x52<<22)|0x7)
 #define XY_MONO_SRC_COPY		((0x2<<29)|(0x54<<22)|(0x6))

drivers/video/Intel-2D/sna_render.h

@@ -10,6 +10,10 @@
 
 #define GXinvalid 0xff
 
+#define HW_BIT_BLIT         (1<<0)      /* BGRX blitter             */
+#define HW_TEX_BLIT         (1<<1)      /* stretch blit             */
+#define HW_VID_BLIT         (1<<2)      /* planar and packed video  */
+
 struct sna;
 struct sna_glyph;
 struct sna_video;
@@ -152,6 +156,8 @@ struct sna_copy_op {
 struct sna_render {
 	int active;
 	
+	int caps;
+
 	int max_3d_size;
 	int max_3d_pitch;
 
@@ -160,7 +166,6 @@ struct sna_render {
 #define PREFER_GPU_RENDER 0x2
 #define PREFER_GPU_SPANS 0x4
 
-
 	bool (*composite)(struct sna *sna, uint8_t op,
 			  PicturePtr dst, PicturePtr src, PicturePtr mask,
 			  int16_t src_x, int16_t src_y,

drivers/video/Intel-2D/sna_render_inline.h

@@ -0,0 +1,71 @@
+#ifndef SNA_RENDER_INLINE_H
+#define SNA_RENDER_INLINE_H
+
+static inline bool need_tiling(struct sna *sna, int16_t width, int16_t height)
+{
+	/* Is the damage area too large to fit in 3D pipeline,
+	 * and so do we need to split the operation up into tiles?
+	 */
+	return (width > sna->render.max_3d_size ||
+		height > sna->render.max_3d_size);
+}
+
+static inline bool need_redirect(struct sna *sna, PixmapPtr dst)
+{
+	/* Is the pixmap too large to render to? */
+	return (dst->drawable.width > sna->render.max_3d_size ||
+		dst->drawable.height > sna->render.max_3d_size);
+}
+
+static inline float pack_2s(int16_t x, int16_t y)
+{
+	union {
+		struct sna_coordinate p;
+		float f;
+	} u;
+	u.p.x = x;
+	u.p.y = y;
+	return u.f;
+}
+
+static inline int vertex_space(struct sna *sna)
+{
+	return sna->render.vertex_size - sna->render.vertex_used;
+}
+static inline void vertex_emit(struct sna *sna, float v)
+{
+	assert(sna->render.vertex_used < sna->render.vertex_size);
+	sna->render.vertices[sna->render.vertex_used++] = v;
+}
+static inline void vertex_emit_2s(struct sna *sna, int16_t x, int16_t y)
+{
+	vertex_emit(sna, pack_2s(x, y));
+}
+
+static inline int batch_space(struct sna *sna)
+{
+	assert(sna->kgem.nbatch <= KGEM_BATCH_SIZE(&sna->kgem));
+	assert(sna->kgem.nbatch + KGEM_BATCH_RESERVED <= sna->kgem.surface);
+	return sna->kgem.surface - sna->kgem.nbatch - KGEM_BATCH_RESERVED;
+}
+
+static inline void batch_emit(struct sna *sna, uint32_t dword)
+{
+	assert(sna->kgem.mode != KGEM_NONE);
+	assert(sna->kgem.nbatch + KGEM_BATCH_RESERVED < sna->kgem.surface);
+	sna->kgem.batch[sna->kgem.nbatch++] = dword;
+}
+
+static inline void batch_emit_float(struct sna *sna, float f)
+{
+	union {
+		uint32_t dw;
+		float f;
+	} u;
+	u.f = f;
+	batch_emit(sna, u.dw);
+}
+
+
+
+#endif /* SNA_RENDER_INLINE_H */

drivers/video/Intel-2D/sna_stream.c

@@ -116,7 +116,6 @@ sna_static_stream_compile_sf(struct sna *sna,
 	return sna_static_stream_offsetof(stream, p.store);
 }
 
-
 unsigned
 sna_static_stream_compile_wm(struct sna *sna,
 			     struct sna_static_stream *stream,