forked from KolibriOS/kolibrios
493 lines
16 KiB
PHP
493 lines
16 KiB
PHP
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; ;;
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;; Copyright (C) KolibriOS team 2014-2015. All rights reserved. ;;
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;; Distributed under terms of the GNU General Public License ;;
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;; ;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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$Revision$
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;-----------------------------------------------------------------------------
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; find the IDE controller in the device list
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;-----------------------------------------------------------------------------
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mov ecx, IDE_controller_1
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mov esi, pcidev_list
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;--------------------------------------
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align 4
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.loop:
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mov esi, [esi+PCIDEV.fd]
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cmp esi, pcidev_list
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jz find_IDE_controller_done
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mov eax, [esi+PCIDEV.class]
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; shr eax, 4
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; cmp eax, 0x01018
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shr eax, 7
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cmp eax, 0x010180 shr 7
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jnz .loop
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;--------------------------------------
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.found:
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mov eax, [esi+PCIDEV.class]
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DEBUGF 1, 'K : IDE controller programming interface %x\n', eax
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mov [ecx+IDE_DATA.ProgrammingInterface], eax
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mov [ecx+IDE_DATA.pcidev], esi
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mov ah, [esi+PCIDEV.bus]
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mov al, 2
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mov bh, [esi+PCIDEV.devfn]
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;--------------------------------------
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mov dx, 0x1F0
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test byte [esi+PCIDEV.class], 1
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jz @f
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mov bl, 0x10
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push eax
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call pci_read_reg
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and eax, 0xFFFC
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mov edx, eax
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pop eax
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@@:
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DEBUGF 1, 'K : BAR0 IDE base addr %x\n', dx
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mov [StandardATABases], dx
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mov [ecx+IDE_DATA.BAR0_val], dx
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;--------------------------------------
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mov dx, 0x3F4
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test byte [esi+PCIDEV.class], 1
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jz @f
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mov bl, 0x14
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push eax
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call pci_read_reg
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and eax, 0xFFFC
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mov edx, eax
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pop eax
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@@:
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DEBUGF 1, 'K : BAR1 IDE base addr %x\n', dx
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mov [ecx+IDE_DATA.BAR1_val], dx
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;--------------------------------------
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mov dx, 0x170
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test byte [esi+PCIDEV.class], 4
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jz @f
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mov bl, 0x18
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push eax
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call pci_read_reg
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and eax, 0xFFFC
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mov edx, eax
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pop eax
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@@:
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DEBUGF 1, 'K : BAR2 IDE base addr %x\n', dx
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mov [StandardATABases+2], dx
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mov [ecx+IDE_DATA.BAR2_val], dx
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;--------------------------------------
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mov dx, 0x374
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test byte [esi+PCIDEV.class], 4
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jz @f
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mov bl, 0x1C
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push eax
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call pci_read_reg
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and eax, 0xFFFC
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mov edx, eax
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pop eax
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@@:
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DEBUGF 1, 'K : BAR3 IDE base addr %x\n', dx
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mov [ecx+IDE_DATA.BAR3_val], dx
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;--------------------------------------
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mov bl, 0x20
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push eax
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call pci_read_reg
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and eax, 0xFFFC
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DEBUGF 1, 'K : BAR4 IDE controller register base addr %x\n', ax
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mov [ecx+IDE_DATA.RegsBaseAddres], ax
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pop eax
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;--------------------------------------
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mov bl, 0x3C
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push eax
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call pci_read_reg
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and eax, 0xFF
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DEBUGF 1, 'K : IDE Interrupt %x\n', al
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mov [ecx+IDE_DATA.Interrupt], ax
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pop eax
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add ecx, sizeof.IDE_DATA
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;--------------------------------------
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jmp .loop
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;-----------------------------------------------------------------------------
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uglobal
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align 4
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;--------------------------------------
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IDE_controller_pointer dd ?
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;--------------------------------------
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IDE_controller_1 IDE_DATA
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IDE_controller_2 IDE_DATA
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IDE_controller_3 IDE_DATA
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;--------------------------------------
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cache_ide0 IDE_CACHE
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cache_ide1 IDE_CACHE
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cache_ide2 IDE_CACHE
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cache_ide3 IDE_CACHE
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cache_ide4 IDE_CACHE
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cache_ide5 IDE_CACHE
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cache_ide6 IDE_CACHE
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cache_ide7 IDE_CACHE
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cache_ide8 IDE_CACHE
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cache_ide9 IDE_CACHE
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cache_ide10 IDE_CACHE
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cache_ide11 IDE_CACHE
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;--------------------------------------
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IDE_device_1 rd 2
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IDE_device_2 rd 2
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IDE_device_3 rd 2
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;--------------------------------------
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endg
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;--------------------------------------
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; set Bus Master bit of Command PCI register
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;--------------------------------------
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set_pci_command_bus_master:
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PCI_COMMAND_BUS_MASTER = 0x0004
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push eax ecx
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mov ecx, [ecx+IDE_DATA.pcidev]
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mov ah, [ecx+PCIDEV.bus]
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mov al, 1 ; word
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mov bh, [ecx+PCIDEV.devfn]
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mov bl, 0x4 ; Command register
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push eax
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call pci_read_reg
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mov ecx, eax
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pop eax
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test ecx, PCI_COMMAND_BUS_MASTER ; already set?
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jnz @f
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or ecx, PCI_COMMAND_BUS_MASTER
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call pci_write_reg
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@@:
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pop ecx eax
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ret
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;-----------------------------------------------------------------------------
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; START of initialisation IDE ATA code
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;-----------------------------------------------------------------------------
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Init_IDE_ATA_controller:
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cmp [ecx+IDE_DATA.ProgrammingInterface], 0
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jne @f
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ret
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;--------------------------------------
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@@:
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mov esi, boot_disabling_ide
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call boot_log
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;--------------------------------------
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; Disable IDE interrupts, because the search
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; for IDE partitions is in the PIO mode.
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;--------------------------------------
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.disable_IDE_interrupt:
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; Disable interrupts in IDE controller for PIO
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mov al, 2
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mov dx, [ecx+IDE_DATA.BAR1_val] ;0x3F4
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add dx, 2 ;0x3F6
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out dx, al
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mov dx, [ecx+IDE_DATA.BAR3_val] ;0x374
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add dx, 2 ;0x376
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out dx, al
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;-----------------------------------------------------------------------------
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; set current ata bases
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@@:
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mov ax, [ecx+IDE_DATA.BAR0_val]
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mov [StandardATABases], ax
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mov ax, [ecx+IDE_DATA.BAR2_val]
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mov [StandardATABases+2], ax
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mov esi, boot_detecthdcd
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call boot_log
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;--------------------------------------
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include 'dev_hdcd.inc'
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;--------------------------------------
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ret
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;-----------------------------------------------------------------------------
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Init_IDE_ATA_controller_2:
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cmp [ecx+IDE_DATA.ProgrammingInterface], 0
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jne @f
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ret
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;--------------------------------------
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@@:
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mov dx, [ecx+IDE_DATA.RegsBaseAddres]
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; test whether it is our interrupt?
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add dx, 2
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in al, dx
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test al, 100b
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jz @f
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; clear Bus Master IDE Status register
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; clear Interrupt bit
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out dx, al
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;--------------------------------------
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@@:
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add dx, 8
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; test whether it is our interrupt?
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in al, dx
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test al, 100b
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jz @f
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; clear Bus Master IDE Status register
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; clear Interrupt bit
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out dx, al
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;--------------------------------------
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@@:
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; read status register and remove the interrupt request
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mov dx, [ecx+IDE_DATA.BAR0_val] ;0x1F0
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add dx, 0x7 ;0x1F7
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in al, dx
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mov dx, [ecx+IDE_DATA.BAR2_val] ;0x170
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add dx, 0x7 ;0x177
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in al, dx
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;-----------------------------------------------------------------------------
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; push eax edx
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; mov dx, [ecx+IDE_DATA.RegsBaseAddres]
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; xor eax, eax
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; add dx, 2
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; in al, dx
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; DEBUGF 1, "K : Primary Bus Master IDE Status Register %x\n", eax
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; add dx, 8
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; in al, dx
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; DEBUGF 1, "K : Secondary Bus Master IDE Status Register %x\n", eax
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; pop edx eax
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; cmp [ecx+IDE_DATA.RegsBaseAddres], 0
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; setnz [ecx+IDE_DATA.dma_hdd]
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;-----------------------------------------------------------------------------
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; set interrupts for IDE Controller
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;-----------------------------------------------------------------------------
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pushfd
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cli
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.enable_IDE_interrupt:
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mov esi, boot_enabling_ide
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call boot_log
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; Enable interrupts in IDE controller for DMA
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xor ebx, ebx
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cmp ecx, IDE_controller_2
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jne @f
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add ebx, 5
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jmp .check_DRIVE_DATA
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;--------------------------------------
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@@:
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cmp ecx, IDE_controller_3
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jne .check_DRIVE_DATA
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add ebx, 10
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;--------------------------------------
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.check_DRIVE_DATA:
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mov al, 0
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mov ah, [ebx+DRIVE_DATA+1]
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test ah, 10100000b ; check for ATAPI devices
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jz @f
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;--------------------------------------
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.ch1_pio_set_ATAPI:
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DEBUGF 1, "K : IDE CH1 PIO, because ATAPI drive present\n"
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jmp .ch1_pio_set_for_all
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;--------------------------------------
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.ch1_pio_set_no_devices:
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DEBUGF 1, "K : IDE CH1 PIO because no devices\n"
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jmp .ch1_pio_set_for_all
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;-------------------------------------
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.ch1_pio_set:
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DEBUGF 1, "K : IDE CH1 PIO because device not support UDMA\n"
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;-------------------------------------
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.ch1_pio_set_for_all:
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mov [ecx+IDE_DATA.dma_hdd_channel_1], al
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jmp .ch2_check
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;--------------------------------------
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@@:
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xor ebx, ebx
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call calculate_IDE_device_values_storage
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test ah, 1010000b
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jz .ch1_pio_set_no_devices
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test ah, 1000000b
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jz @f
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cmp [ebx+IDE_DEVICE.UDMA_possible_modes], al
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je .ch1_pio_set
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cmp [ebx+IDE_DEVICE.UDMA_set_mode], al
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je .ch1_pio_set
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;--------------------------------------
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@@:
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test ah, 10000b
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jz @f
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add ebx, 2
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cmp [ebx+IDE_DEVICE.UDMA_possible_modes], al
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je .ch1_pio_set
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cmp [ebx+IDE_DEVICE.UDMA_set_mode], al
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je .ch1_pio_set
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;--------------------------------------
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@@:
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mov dx, [ecx+IDE_DATA.BAR1_val] ;0x3F4
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add dx, 2 ;0x3F6
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out dx, al
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call set_pci_command_bus_master
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DEBUGF 1, "K : IDE CH1 DMA enabled\n"
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mov [ecx+IDE_DATA.dma_hdd_channel_1], byte 1
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;--------------------------------------
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.ch2_check:
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test ah, 1010b ; check for ATAPI devices
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jz @f
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;--------------------------------------
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.ch2_pio_set_ATAPI:
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DEBUGF 1, "K : IDE CH2 PIO, because ATAPI drive present\n"
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jmp .ch2_pio_set_for_all
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;--------------------------------------
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.ch2_pio_set_no_devices:
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DEBUGF 1, "K : IDE CH2 PIO because no devices\n"
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jmp .ch2_pio_set_for_all
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;--------------------------------------
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.ch2_pio_set:
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DEBUGF 1, "K : IDE CH2 PIO because device not support UDMA\n"
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;--------------------------------------
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.ch2_pio_set_for_all:
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mov [ecx+IDE_DATA.dma_hdd_channel_2], al
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jmp .set_interrupts_for_IDE_controllers
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;--------------------------------------
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@@:
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mov ebx, 4
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call calculate_IDE_device_values_storage
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test ah, 101b
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jz .ch2_pio_set_no_devices
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test ah, 100b
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jz @f
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cmp [ebx+IDE_DEVICE.UDMA_possible_modes], al
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je .ch2_pio_set
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cmp [ebx+IDE_DEVICE.UDMA_set_mode], al
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je .ch2_pio_set
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;--------------------------------------
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@@:
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test ah, 1b
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jz @f
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add ebx, 2
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cmp [ebx+IDE_DEVICE.UDMA_possible_modes], al
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je .ch2_pio_set
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cmp [ebx+IDE_DEVICE.UDMA_set_mode], al
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je .ch2_pio_set
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;--------------------------------------
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@@:
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mov dx, [ecx+IDE_DATA.BAR3_val] ;0x374
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add dx, 2 ;0x376
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out dx, al
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call set_pci_command_bus_master
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DEBUGF 1, "K : IDE CH2 DMA enabled\n"
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mov [ecx+IDE_DATA.dma_hdd_channel_2], byte 1
|
||
|
|
;--------------------------------------
|
||
|
|
.set_interrupts_for_IDE_controllers:
|
||
|
|
mov esi, boot_set_int_IDE
|
||
|
|
call boot_log
|
||
|
|
;--------------------------------------
|
||
|
|
mov eax, [ecx+IDE_DATA.ProgrammingInterface]
|
||
|
|
; cmp ax, 0x0180
|
||
|
|
; je .pata_ide
|
||
|
|
|
||
|
|
; cmp ax, 0x018a
|
||
|
|
; jne .sata_ide
|
||
|
|
|
||
|
|
test al, 1 ; 0 - legacy PCI mode, 1 - native PCI mode
|
||
|
|
jnz .sata_ide
|
||
|
|
;--------------------------------------
|
||
|
|
.pata_ide:
|
||
|
|
cmp [ecx+IDE_DATA.RegsBaseAddres], 0
|
||
|
|
je .end_set_interrupts
|
||
|
|
|
||
|
|
push ecx
|
||
|
|
stdcall attach_int_handler, 14, IDE_irq_14_handler, ecx
|
||
|
|
pop ecx
|
||
|
|
DEBUGF 1, "K : Set IDE IRQ14 return code %x\n", eax
|
||
|
|
push ecx
|
||
|
|
stdcall attach_int_handler, 15, IDE_irq_15_handler, ecx
|
||
|
|
DEBUGF 1, "K : Set IDE IRQ15 return code %x\n", eax
|
||
|
|
pop ecx
|
||
|
|
|
||
|
|
jmp .end_set_interrupts
|
||
|
|
;--------------------------------------
|
||
|
|
.sata_ide:
|
||
|
|
; cmp ax, 0x0185
|
||
|
|
; je .sata_ide_1
|
||
|
|
|
||
|
|
; cmp ax, 0x018f
|
||
|
|
; jne .end_set_interrupts
|
||
|
|
;--------------------------------------
|
||
|
|
;.sata_ide_1:
|
||
|
|
; Some weird controllers generate an interrupt even if IDE interrupts
|
||
|
|
; are disabled and no IDE devices. For example, notebook ASUS K72F -
|
||
|
|
; IDE controller 010185 generates false interrupt when we work with
|
||
|
|
; the IDE controller 01018f. For this reason, the interrupt handler
|
||
|
|
; does not need to be installed if both channel IDE controller
|
||
|
|
; running in PIO mode.
|
||
|
|
|
||
|
|
; ...unfortunately, PCI interrupt can be shared with other devices
|
||
|
|
; which could enable it without consulting IDE code.
|
||
|
|
; So install the handler anyways and try to process
|
||
|
|
; even those interrupts which we are not expecting.
|
||
|
|
cmp [ecx+IDE_DATA.RegsBaseAddres], 0
|
||
|
|
je .end_set_interrupts
|
||
|
|
|
||
|
|
mov ax, [ecx+IDE_DATA.Interrupt]
|
||
|
|
movzx eax, al
|
||
|
|
push ecx
|
||
|
|
stdcall attach_int_handler, eax, IDE_common_irq_handler, ecx
|
||
|
|
pop ecx
|
||
|
|
DEBUGF 1, "K : Set IDE IRQ%d return code %x\n", [ecx+IDE_DATA.Interrupt]:1, eax
|
||
|
|
;--------------------------------------
|
||
|
|
.end_set_interrupts:
|
||
|
|
popfd
|
||
|
|
ret
|
||
|
|
;-----------------------------------------------------------------------------
|
||
|
|
; END of initialisation IDE ATA code
|
||
|
|
;-----------------------------------------------------------------------------
|
||
|
|
find_IDE_controller_done:
|
||
|
|
mov ecx, IDE_controller_1
|
||
|
|
mov [IDE_controller_pointer], ecx
|
||
|
|
call Init_IDE_ATA_controller
|
||
|
|
mov ecx, IDE_controller_2
|
||
|
|
mov [IDE_controller_pointer], ecx
|
||
|
|
call Init_IDE_ATA_controller
|
||
|
|
mov ecx, IDE_controller_3
|
||
|
|
mov [IDE_controller_pointer], ecx
|
||
|
|
call Init_IDE_ATA_controller
|
||
|
|
;-----------------------------------------------------------------------------
|
||
|
|
mov esi, boot_getcache
|
||
|
|
call boot_log
|
||
|
|
include 'getcache.inc'
|
||
|
|
;-----------------------------------------------------------------------------
|
||
|
|
mov esi, boot_detectpart
|
||
|
|
call boot_log
|
||
|
|
include 'sear_par.inc'
|
||
|
|
;-----------------------------------------------------------------------------
|
||
|
|
mov esi, boot_init_sys
|
||
|
|
call boot_log
|
||
|
|
call Parser_params
|
||
|
|
|
||
|
|
if ~ defined extended_primary_loader
|
||
|
|
; ramdisk image should be loaded by extended primary loader if it exists
|
||
|
|
; READ RAMDISK IMAGE FROM HD
|
||
|
|
include '../boot/rdload.inc'
|
||
|
|
end if
|
||
|
|
;-----------------------------------------------------------------------------
|
||
|
|
mov ecx, IDE_controller_1
|
||
|
|
mov [IDE_controller_pointer], ecx
|
||
|
|
call Init_IDE_ATA_controller_2
|
||
|
|
mov ecx, IDE_controller_2
|
||
|
|
mov [IDE_controller_pointer], ecx
|
||
|
|
call Init_IDE_ATA_controller_2
|
||
|
|
mov ecx, IDE_controller_3
|
||
|
|
mov [IDE_controller_pointer], ecx
|
||
|
|
call Init_IDE_ATA_controller_2
|
||
|
|
;-----------------------------------------------------------------------------
|