forked from KolibriOS/kolibrios
191 lines
7.9 KiB
PHP
191 lines
7.9 KiB
PHP
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; ;;
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;; Copyright (C) KolibriOS team 2004-2021. All rights reserved. ;;
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;; Distributed under terms of the GNU General Public License ;;
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;; ;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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$Revision$
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PCI_REG_STATUS_COMMAND = 0x0004
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PCI_REG_BAR5 = 0x0024
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AHCI_BOHCf_BOS = 0 ; BIOS-Owned Semaphore (BIOS owns controller)
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AHCI_BOHCf_OOS = 1 ; OS-Owned Semaphore (OS owns controller)
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AHCI_BOHCf_BB = 4 ; BIOS Busy (polling bit while BIOS cleans up
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AHCI_CAP2_BOH = 0 ; number of bit in BOH which shows Supports BIOS/OS Handoff
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HBA_MEMORY_SIZE = 0x1100
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struct AHCI_DATA
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;;
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abar dd ? ; pointer to HBA Memory (BAR5) mapped to virtual kernelspace memory
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pcidev dd ? ; pointer to corresponding PCIDEV structure
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ends
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; Generic Host Control registers
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struct HBA_MEM
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capability dd ? ; 0x00
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global_host_control dd ? ; 0x04
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interrupt_status dd ? ; 0x08
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port_implemented dd ? ; 0x0C
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version dd ? ; 0x10
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ccc_ctl dd ? ; 0x14, Command completion coalescing control
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ccc_pts dd ? ; 0x18, Command completion coalescing ports
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em_loc dd ? ; 0x1C, Enclosure management location
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em_ctl dd ? ; 0x20, Enclosure management control
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capability2 dd ? ; 0x24, Host capabilities extended
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bohc dd ? ; 0x28, BIOS/OS handoff control and status
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reserved rb (0xA0-0x2C) ; 0x2C - 0x9F, Reserved
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vendor rb (0x100-0xA0) ; 0xA0 - 0xFF, Vendor specific
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ports rb (sizeof.HBA_PORT*32) ; 0x100 - 0x10FF, Port control registers, max 32
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ends
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; Port Control registers
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struct HBA_PORT
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command_list_base_l dd ? ; 0x00, command list base address, 1K-byte aligned
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command_list_base_h dd ? ; 0x04, command list base address upper 32 bits, used on 64 bit systems
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fis_base_l dd ? ; 0x08, FIS base address, 256-byte aligned
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fis_base_h dd ? ; 0x0C, FIS base address upper 32 bits, used on 64 bit systems
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interrupt_status dd ? ; 0x10
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interrupt_enable dd ? ; 0x14
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command dd ? ; 0x18, command and status
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reserved0 dd ? ; 0x1C
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task_file_data dd ? ; 0x20
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signature dd ? ; 0x24
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sata_status dd ? ; 0x28, SATA status (SCR0:SStatus)
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sata_control dd ? ; 0x2C, SATA control (SCR2:SControl)
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sata_error dd ? ; 0x30, SATA error (SCR1:SError)
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sata_active dd ? ; 0x34, SATA active (SCR3:SActive)
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command_issue dd ? ; 0x38
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sata_notification dd ? ; 0x3C, SATA notification (SCR4:SNotification)
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fis_based_switch_control dd ? ; 0x40
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reserved1 rd 11 ; 0x44 - 0x6F
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vendor rd 4 ; 0x70 - 0x7F, vendor specific
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ends
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uglobal
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align 4
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ahci_controller AHCI_DATA
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endg
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; detect ahci controller and initialize
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align 4
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init_ahci:
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mov ecx, ahci_controller
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mov esi, pcidev_list
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.find_ahci_ctr:
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mov esi, [esi + PCIDEV.fd]
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cmp esi, pcidev_list
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jz .ahci_ctr_not_found
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mov eax, [esi + PCIDEV.class]
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;DEBUGF 1, "K: device class = %x\n", eax
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shr eax, 8 ; shift right because lowest 8 bits if ProgIf field
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cmp eax, 0x0106 ; 0x01 - Mass Storage Controller class, 0x06 - Serial ATA Controller subclass
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jz .ahci_ctr_found
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jmp .find_ahci_ctr
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.ahci_ctr_not_found:
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DEBUGF 1, "K: AHCI controller not found\n"
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ret
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.ahci_ctr_found:
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mov [ahci_controller + AHCI_DATA.pcidev], esi
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mov eax, [esi+PCIDEV.class]
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movzx ebx, byte [esi+PCIDEV.bus]
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movzx ecx, byte [esi+PCIDEV.devfn]
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shr ecx, 3 ; get rid of 3 lowest bits (function code), the rest bits is device code
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movzx edx, byte [esi+PCIDEV.devfn]
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and edx, 00000111b ; get only 3 lowest bits (function code)
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DEBUGF 1, "K: found AHCI controller, (class, subcl, progif) = %x, bus = %x, device = %x, function = %x\n", eax, ebx, ecx, edx
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mov ah, [esi + PCIDEV.bus]
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mov al, 2 ; read dword
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mov bh, [esi + PCIDEV.devfn]
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mov bl, PCI_REG_BAR5
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call pci_read_reg
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DEBUGF 1, "K: AHCI controller BAR5 = %x\n", eax
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stdcall map_io_mem, eax, HBA_MEMORY_SIZE, PG_SWR + PG_NOCACHE
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mov [ahci_controller + AHCI_DATA.abar], eax
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DEBUGF 1, "K: AHCI controller BAR5 mapped to virtual addr %x\n", eax
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mov ah, [esi + PCIDEV.bus]
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mov al, 2 ; read dword
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mov bh, [esi + PCIDEV.devfn]
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mov bl, PCI_REG_STATUS_COMMAND
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call pci_read_reg
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DEBUGF 1, "K: AHCI: pci_status_command = %x\nEnabling interrupts, DMA bus mastering and memory space access\n", eax
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or eax, 0x06 ; pci.command |= 0x06 (dma bus mastering + memory space access)
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btr eax, 10 ; clear the "disable interrupts" bit
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DEBUGF 1, "K: AHCI: pci_status_command = %x\n", eax
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mov ecx, eax
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mov ah, [esi + PCIDEV.bus]
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mov al, 2 ; write dword
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mov bh, [esi + PCIDEV.devfn]
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mov bl, PCI_REG_STATUS_COMMAND
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call pci_write_reg
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mov eax, [ahci_controller + AHCI_DATA.abar]
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mov ebx, [eax + HBA_MEM.capability]
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mov ecx, [eax + HBA_MEM.global_host_control]
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mov edx, [eax + HBA_MEM.version]
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DEBUGF 1, "K: AHCI: HBA.cap = %x, HBA.ghc = %x, HBA_MEM.version = %x\n", ebx, ecx, edx
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; //Transferring ownership from BIOS if supported.
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; if (Bt(&hba->caps_ext, AHCI_CAPSEXTf_BOH))
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; {
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; Bts(&hba->bohc, AHCI_BOHCf_OOS);
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; "AHCI: Transferring ownership from BIOS\n";
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; while (Bt(&hba->bohc, AHCI_BOHCf_BOS));
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; Sleep(25);
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; if (Bt(&hba->bohc, AHCI_BOHCf_BB)) //if Bios Busy is still set after 25 mS, wait 2 seconds.
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; Sleep(2000);
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; }
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; Transferring ownership from BIOS if supported. (TODO check)
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mov eax, [ahci_controller + AHCI_DATA.abar]
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mov ebx, [eax + HBA_MEM.capability2]
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DEBUGF 1, "K: AHCI: HBA_MEM.cap2 = %x\n", ebx
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bt dword [eax + HBA_MEM.capability2], AHCI_CAP2_BOH
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jnc .end_handoff
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DEBUGF 1, "K: AHCI: Transferring ownership from BIOS...\n"
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bts dword [eax + HBA_MEM.bohc], AHCI_BOHCf_OOS
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.wait_not_bos:
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bt dword [eax + HBA_MEM.bohc], AHCI_BOHCf_BOS
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jc .wait_not_bos
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mov ebx, 3
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call delay_hs
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; if Bios Busy is still set after 25 mS, wait 2 seconds.
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bt dword [eax + HBA_MEM.bohc], AHCI_BOHCf_BB
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jnc @f
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mov ebx, 200
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call delay_hs
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@@:
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DEBUGF 1, "K: AHCI: Done.\n"
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.end_handoff:
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;; TODO: Reset controller ?
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;; TODO enble AHCI ? (see https://github.com/ZenithOS/ZenithOS/blob/4ea8b133613ab95a8b53ed543d8e63525a21954e/src/Kernel/BlkDev/DiskAHCI.CC#L719)
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;; TODO: find drives (see https://github.com/ZenithOS/ZenithOS/blob/4ea8b133613ab95a8b53ed543d8e63525a21954e/src/Kernel/BlkDev/DiskAHCI.CC#L742)
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ret
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