forked from KolibriOS/kolibrios
added pci.inc for drivers, removed redundant code from netdrv.inc
git-svn-id: svn://kolibrios.org@2886 a494cfbc-eb01-0410-851d-a64ba20cac60
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hidnplayr
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124
kernel/branches/net/drivers/bus/pci.inc
Normal file
124
kernel/branches/net/drivers/bus/pci.inc
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@ -0,0 +1,124 @@
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; ;;
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;; Copyright (C) KolibriOS team 2004-2012. All rights reserved. ;;
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;; Distributed under terms of the GNU General Public License ;;
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;; ;;
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;; GNU GENERAL PUBLIC LICENSE ;;
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;; Version 2, June 1991 ;;
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;; ;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; PCI Bus defines
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PCI_HEADER_TYPE = 0x0e ; 8 bit
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PCI_BASE_ADDRESS_0 = 0x10 ; 32 bit
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PCI_BASE_ADDRESS_5 = 0x24 ; 32 bits
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PCI_BASE_ADDRESS_SPACE_IO = 0x01
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PCI_VENDOR_ID = 0x00 ; 16 bit
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PCI_BASE_ADDRESS_IO_MASK = 0xFFFFFFFC
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; PCI programming
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PCI_REG_COMMAND = 0x4 ; command register
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PCI_REG_STATUS = 0x6 ; status register
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PCI_REG_LATENCY = 0xd ; latency timer register
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PCI_REG_CAP_PTR = 0x34 ; capabilities pointer
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PCI_REG_CAPABILITY_ID = 0x0 ; capapility ID in pm register block
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PCI_REG_PM_STATUS = 0x4 ; power management status register
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PCI_REG_PM_CTRL = 0x4 ; power management control register
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PCI_BIT_PIO = 1 ; bit0: io space control
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PCI_BIT_MMIO = 2 ; bit1: memory space control
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PCI_BIT_MASTER = 4 ; bit2: device acts as a PCI master
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macro find_io bus, dev, io {
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local .check, .inc, .got
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xor eax, eax
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mov esi, PCI_BASE_ADDRESS_0
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movzx ecx, bus
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movzx edx, dev
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.check:
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stdcall PciRead32, ecx ,edx ,esi
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test eax, PCI_BASE_ADDRESS_IO_MASK
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jz .inc
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test eax, PCI_BASE_ADDRESS_SPACE_IO
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jz .inc
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and eax, PCI_BASE_ADDRESS_IO_MASK
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mov io , eax
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jmp .got
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.inc:
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add esi, 4
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cmp esi, PCI_BASE_ADDRESS_5
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jle .check
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.got:
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}
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macro find_mmio32 bus, dev, mmio32 {
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local .check, .got
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xor eax, eax
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mov esi, PCI_BASE_ADDRESS_0
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movzx ecx, bus
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movzx edx, dev
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.check:
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stdcall PciRead32, ecx ,edx ,esi
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test eax, not PCI_BASE_ADDRESS_IO_MASK
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jz .got
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add esi, 4
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cmp esi, PCI_BASE_ADDRESS_5
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jle .check
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xor eax, eax
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.got:
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mov mmio32, eax
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}
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macro find_irq bus, dev, irq {
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push eax edx ecx
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movzx ecx, bus
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movzx edx, dev
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stdcall PciRead8, ecx ,edx ,0x3c ; 0x3c is the offset where irq can be found
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mov irq, al
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pop ecx edx eax
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}
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macro find_rev bus, dev, rev {
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push eax edx ecx
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movzx ecx, bus
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movzx edx, dev
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stdcall PciRead8, ecx ,edx ,0x8
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mov rev, al
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pop ecx edx eax
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}
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macro make_bus_master bus, dev {
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movzx ecx, bus
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movzx edx, dev
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stdcall PciRead32, ecx ,edx, PCI_REG_COMMAND
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or al, PCI_BIT_MASTER ;or PCI_BIT_PIO
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; and al, not PCI_BIT_MMIO
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stdcall PciWrite32, ecx, edx, PCI_REG_COMMAND, eax
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;; TODO: try to switch to PIO, and check if PIO works or not..
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}
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@ -1,24 +1,14 @@
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; PCI Bus defines
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PCI_HEADER_TYPE equ 0x0e ;8 bit
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PCI_BASE_ADDRESS_0 equ 0x10 ;32 bit
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PCI_BASE_ADDRESS_5 equ 0x24 ;32 bits
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PCI_BASE_ADDRESS_SPACE_IO equ 0x01
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PCI_VENDOR_ID equ 0x00 ;16 bit
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PCI_BASE_ADDRESS_IO_MASK equ 0xFFFFFFFC
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; PCI programming
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PCI_REG_COMMAND equ 0x4 ; command register
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PCI_REG_STATUS equ 0x6 ; status register
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PCI_REG_LATENCY equ 0xd ; latency timer register
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PCI_REG_CAP_PTR equ 0x34 ; capabilities pointer
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PCI_REG_CAPABILITY_ID equ 0x0 ; capapility ID in pm register block
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PCI_REG_PM_STATUS equ 0x4 ; power management status register
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PCI_REG_PM_CTRL equ 0x4 ; power management control register
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PCI_BIT_PIO equ 1 ; bit0: io space control
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PCI_BIT_MMIO equ 2 ; bit1: memory space control
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PCI_BIT_MASTER equ 4 ; bit2: device acts as a PCI master
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; ;;
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;; Copyright (C) KolibriOS team 2004-2012. All rights reserved. ;;
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;; Distributed under terms of the GNU General Public License ;;
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;; ;;
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;; GNU GENERAL PUBLIC LICENSE ;;
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;; Version 2, June 1991 ;;
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;; ;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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include 'bus/pci.inc'
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; Kernel variables
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@ -32,7 +22,6 @@
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NET_TYPE_SLIP equ 2
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LAST_IO = 0
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macro set_io addr {
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@ -79,72 +68,6 @@ macro allocate_and_clear dest, size, err {
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}
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macro find_io bus, dev, io {
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local .check, .inc, .got
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xor eax, eax
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mov esi, PCI_BASE_ADDRESS_0
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movzx ecx, bus
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movzx edx, dev
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.check:
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stdcall PciRead32, ecx ,edx ,esi
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test eax, PCI_BASE_ADDRESS_IO_MASK
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jz .inc
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test eax, PCI_BASE_ADDRESS_SPACE_IO
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jz .inc
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and eax, PCI_BASE_ADDRESS_IO_MASK
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mov io , eax
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jmp .got
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.inc:
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add esi, 4
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cmp esi, PCI_BASE_ADDRESS_5
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jle .check
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.got:
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}
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macro find_irq bus, dev, irq {
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push eax edx ecx
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movzx ecx, bus
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movzx edx, dev
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stdcall PciRead8, ecx ,edx ,0x3c ; 0x3c is the offset where irq can be found
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mov irq, al
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pop ecx edx eax
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}
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macro find_rev bus, dev, rev {
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push eax edx ecx
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movzx ecx, bus
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movzx edx, dev
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stdcall PciRead8, ecx ,edx ,0x8
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mov rev, al
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pop ecx edx eax
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}
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macro make_bus_master bus, dev {
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movzx ecx, bus
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movzx edx, dev
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stdcall PciRead32, ecx ,edx, PCI_REG_COMMAND
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or al, PCI_BIT_MASTER ;or PCI_BIT_PIO
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; and al, not PCI_BIT_MMIO
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stdcall PciWrite32, ecx, edx, PCI_REG_COMMAND, eax
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;; TODO: try to switch to PIO, and check if PIO works or not..
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}
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struc IOCTL {
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.handle dd ?
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.io_code dd ?
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