forked from KolibriOS/kolibrios
469 lines
15 KiB
PHP
469 lines
15 KiB
PHP
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;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
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;***** Created: 2005-01-11 10:31 ******* Source: ATtiny13.xml ************
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;*************************************************************************
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;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
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;*
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;* Number : AVR000
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;* File Name : "tn13def.inc"
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;* Title : Register/Bit Definitions for the ATtiny13
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;* Date : 2005-01-11
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;* Version : 2.14
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;* Support E-mail : avr@atmel.com
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;* Target MCU : ATtiny13
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;*
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;* DESCRIPTION
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;* When including this file in the assembly program file, all I/O register
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;* names and I/O register bit names appearing in the data book can be used.
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;* In addition, the six registers forming the three data pointers X, Y and
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;* Z have been assigned names XL - ZH. Highest RAM address for Internal
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;* SRAM is also defined
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;*
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;* The Register names are represented by their hexadecimal address.
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;*
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;* The Register Bit names are represented by their bit number (0-7).
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;*
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;* Please observe the difference in using the bit names with instructions
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;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
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;* (skip if bit in register set/cleared). The following example illustrates
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;* this:
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;*
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;* in r16,PORTB ;read PORTB latch
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;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
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;* out PORTB,r16 ;output to PORTB
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;*
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;* in r16,TIFR ;read the Timer Interrupt Flag Register
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;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
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;* rjmp TOV0_is_set ;jump if set
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;* ... ;otherwise do something else
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;*************************************************************************
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#ifndef _TN13DEF_INC_
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#define _TN13DEF_INC_
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#pragma partinc 0
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; ***** SPECIFY DEVICE ***************************************************
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.device ATtiny13
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#pragma AVRPART ADMIN PART_NAME ATtiny13
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.equ SIGNATURE_000 = 0x1e
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.equ SIGNATURE_001 = 0x90
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.equ SIGNATURE_002 = 0x07
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#pragma AVRPART CORE CORE_VERSION V2
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#pragma AVRPART CORE NEW_INSTRUCTIONS lpm rd,z+
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; ***** I/O REGISTER DEFINITIONS *****************************************
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; NOTE:
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; Definitions marked "MEMORY MAPPED"are extended I/O ports
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; and cannot be used with IN/OUT instructions
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.equ SREG = 0x3f
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.equ SPL = 0x3d
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.equ GIMSK = 0x3b
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.equ GIFR = 0x3a
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.equ TIMSK0 = 0x39
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.equ TIFR0 = 0x38
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.equ SPMCSR = 0x37
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.equ OCR0A = 0x36
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.equ MCUCR = 0x35
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.equ MCUSR = 0x34
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.equ TCCR0B = 0x33
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.equ TCNT0 = 0x32
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.equ OSCCAL = 0x31
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.equ TCCR0A = 0x2f
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.equ DWDR = 0x2e
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.equ OCR0B = 0x29
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.equ GTCCR = 0x28
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.equ CLKPR = 0x26
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.equ WDTCR = 0x21
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.equ EEAR = 0x1e
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.equ EEDR = 0x1d
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.equ EECR = 0x1c
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.equ PORTB = 0x18
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.equ DDRB = 0x17
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.equ PINB = 0x16
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.equ PCMSK = 0x15
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.equ DIDR0 = 0x14
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.equ ACSR = 0x08
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.equ ADMUX = 0x07
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.equ ADCSRA = 0x06
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.equ ADCH = 0x05
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.equ ADCL = 0x04
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.equ ADCSRB = 0x03
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; ***** BIT DEFINITIONS **************************************************
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; ***** AD_CONVERTER *****************
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; ADMUX - The ADC multiplexer Selection Register
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.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits
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.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits
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.equ ADLAR = 5 ; Left Adjust Result
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.equ REFS0 = 6 ; Reference Selection Bit 0
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; ADCSRA - The ADC Control and Status register
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.equ ADPS0 = 0 ; ADC Prescaler Select Bits
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.equ ADPS1 = 1 ; ADC Prescaler Select Bits
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.equ ADPS2 = 2 ; ADC Prescaler Select Bits
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.equ ADIE = 3 ; ADC Interrupt Enable
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.equ ADIF = 4 ; ADC Interrupt Flag
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.equ ADATE = 5 ; ADC Auto Trigger Enable
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.equ ADSC = 6 ; ADC Start Conversion
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.equ ADEN = 7 ; ADC Enable
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; ADCH - ADC Data Register High Byte
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.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0
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.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1
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.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2
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.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3
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.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4
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.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5
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.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6
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.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7
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; ADCL - ADC Data Register Low Byte
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.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0
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.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1
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.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2
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.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3
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.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4
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.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5
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.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6
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.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7
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; ADCSRB - ADC Control and Status Register B
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.equ ADTS0 = 0 ; ADC Auto Trigger Source 0
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.equ ADTS1 = 1 ; ADC Auto Trigger Source 1
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.equ ADTS2 = 2 ; ADC Auto Trigger Source 2
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; DIDR0 - Digital Input Disable Register 0
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.equ ADC1D = 2 ; ADC2 Digital input Disable
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.equ ADC3D = 3 ; ADC3 Digital input Disable
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.equ ADC2D = 4 ; ADC2 Digital input Disable
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.equ ADC0D = 5 ; ADC0 Digital input Disable
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; ***** ANALOG_COMPARATOR ************
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; ADCSRB - ADC Control and Status Register B
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.equ ACME = 6 ; Analog Comparator Multiplexer Enable
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; ACSR - Analog Comparator Control And Status Register
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.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0
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.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1
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.equ ACIE = 3 ; Analog Comparator Interrupt Enable
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.equ ACI = 4 ; Analog Comparator Interrupt Flag
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.equ ACO = 5 ; Analog Compare Output
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.equ ACBG = 6 ; Analog Comparator Bandgap Select
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.equ AINBG = ACBG ; For compatibility
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.equ ACD = 7 ; Analog Comparator Disable
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; DIDR0 -
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.equ AIN0D = 0 ; AIN0 Digital Input Disable
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.equ AIN1D = 1 ; AIN1 Digital Input Disable
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; ***** EEPROM ***********************
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; EEAR - EEPROM Read/Write Access
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.equ EEARL = EEAR ; For compatibility
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.equ EEAR0 = 0 ; EEPROM Read/Write Access bit 0
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.equ EEAR1 = 1 ; EEPROM Read/Write Access bit 1
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.equ EEAR2 = 2 ; EEPROM Read/Write Access bit 2
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.equ EEAR3 = 3 ; EEPROM Read/Write Access bit 3
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.equ EEAR4 = 4 ; EEPROM Read/Write Access bit 4
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.equ EEAR5 = 5 ; EEPROM Read/Write Access bit 5
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; EEDR - EEPROM Data Register
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.equ EEDR0 = 0 ; EEPROM Data Register bit 0
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.equ EEDR1 = 1 ; EEPROM Data Register bit 1
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.equ EEDR2 = 2 ; EEPROM Data Register bit 2
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.equ EEDR3 = 3 ; EEPROM Data Register bit 3
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.equ EEDR4 = 4 ; EEPROM Data Register bit 4
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.equ EEDR5 = 5 ; EEPROM Data Register bit 5
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.equ EEDR6 = 6 ; EEPROM Data Register bit 6
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.equ EEDR7 = 7 ; EEPROM Data Register bit 7
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; EECR - EEPROM Control Register
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.equ EERE = 0 ; EEPROM Read Enable
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.equ EEWE = 1 ; EEPROM Write Enable
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.equ EEPE = EEWE ; For compatibility
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.equ EEMWE = 2 ; EEPROM Master Write Enable
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.equ EEMPE = EEMWE ; For compatibility
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.equ EERIE = 3 ; EEProm Ready Interrupt Enable
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.equ EEPM0 = 4 ;
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.equ EEPM1 = 5 ;
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; ***** CPU **************************
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; SREG - Status Register
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.equ SREG_C = 0 ; Carry Flag
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.equ SREG_Z = 1 ; Zero Flag
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.equ SREG_N = 2 ; Negative Flag
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.equ SREG_V = 3 ; Two's Complement Overflow Flag
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.equ SREG_S = 4 ; Sign Bit
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.equ SREG_H = 5 ; Half Carry Flag
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.equ SREG_T = 6 ; Bit Copy Storage
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.equ SREG_I = 7 ; Global Interrupt Enable
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; SPL - Stack Pointer Low Byte
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.equ SP0 = 0 ; Stack Pointer Bit 0
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.equ SP1 = 1 ; Stack Pointer Bit 1
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.equ SP2 = 2 ; Stack Pointer Bit 2
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.equ SP3 = 3 ; Stack Pointer Bit 3
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.equ SP4 = 4
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.equ SP5 = 5 ; Stack Pointer Bit 5
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.equ SP6 = 6 ; Stack Pointer Bit 6
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.equ SP7 = 7 ; Stack Pointer Bit 7
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; MCUCR - MCU Control Register
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.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0
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.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1
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.equ SM0 = 3 ; Sleep Mode Select Bit 0
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.equ SM1 = 4 ; Sleep Mode Select Bit 1
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.equ SE = 5 ; Sleep Enable
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.equ PUD = 6 ; Pull-up Disable
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; MCUSR - MCU Status register
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.equ PORF = 0 ; Power-On Reset Flag
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.equ EXTRF = 1 ; External Reset Flag
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.equ BORF = 2 ; Brown-out Reset Flag
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.equ WDRF = 3 ; Watchdog Reset Flag
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; OSCCAL - Oscillator Calibration Register
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.equ CAL0 = 0 ; Oscillatro Calibration Value Bit 0
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.equ CAL1 = 1 ; Oscillatro Calibration Value Bit 1
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.equ CAL2 = 2 ; Oscillatro Calibration Value Bit 2
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.equ CAL3 = 3 ; Oscillatro Calibration Value Bit 3
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.equ CAL4 = 4 ; Oscillatro Calibration Value Bit 4
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.equ CAL5 = 5 ; Oscillatro Calibration Value Bit 5
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.equ CAL6 = 6 ; Oscillatro Calibration Value Bit 6
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; CLKPR - Clock Prescale Register
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.equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0
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.equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1
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.equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2
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.equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3
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.equ CLKPCE = 7 ; Clock Prescaler Change Enable
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; DWDR - Debug Wire Data Register
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.equ DWDR0 = 0 ; Debug Wire Data Register Bit 0
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.equ DWDR1 = 1 ; Debug Wire Data Register Bit 1
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.equ DWDR2 = 2 ; Debug Wire Data Register Bit 2
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.equ DWDR3 = 3 ; Debug Wire Data Register Bit 3
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.equ DWDR4 = 4 ; Debug Wire Data Register Bit 4
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.equ DWDR5 = 5 ; Debug Wire Data Register Bit 5
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.equ DWDR6 = 6 ; Debug Wire Data Register Bit 6
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.equ DWDR7 = 7 ; Debug Wire Data Register Bit 7
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; SPMCSR - Store Program Memory Control and Status Register
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.equ SPMEN = 0 ; Store program Memory Enable
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.equ PGERS = 1 ; Page Erase
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.equ PGWRT = 2 ; Page Write
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.equ RFLB = 3 ; Read Fuse and Lock Bits
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.equ CTPB = 4 ; Clear Temporary Page Buffer
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; ***** PORTB ************************
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; PORTB - Data Register, Port B
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.equ PORTB0 = 0 ;
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.equ PB0 = 0 ; For compatibility
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.equ PORTB1 = 1 ;
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.equ PB1 = 1 ; For compatibility
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.equ PORTB2 = 2 ;
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.equ PB2 = 2 ; For compatibility
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.equ PORTB3 = 3 ;
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.equ PB3 = 3 ; For compatibility
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.equ PORTB4 = 4 ;
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.equ PB4 = 4 ; For compatibility
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.equ PORTB5 = 5 ;
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.equ PB5 = 5 ; For compatibility
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; DDRB - Data Direction Register, Port B
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.equ DDB0 = 0 ;
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.equ DDB1 = 1 ;
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.equ DDB2 = 2 ;
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.equ DDB3 = 3 ;
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.equ DDB4 = 4 ;
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.equ DDB5 = 5 ;
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; PINB - Input Pins, Port B
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.equ PINB0 = 0 ;
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.equ PINB1 = 1 ;
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.equ PINB2 = 2 ;
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.equ PINB3 = 3 ;
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.equ PINB4 = 4 ;
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.equ PINB5 = 5 ;
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; ***** EXTERNAL_INTERRUPT ***********
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; MCUCR - MCU Control Register
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;.equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0
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;.equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1
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; GIMSK - General Interrupt Mask Register
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.equ GICR = GIMSK ; For compatibility
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.equ PCIE = 5 ; Pin Change Interrupt Enable
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.equ INT0 = 6 ; External Interrupt Request 0 Enable
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; GIFR - General Interrupt Flag register
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.equ PCIF = 5 ; Pin Change Interrupt Flag
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.equ INTF0 = 6 ; External Interrupt Flag 0
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; PCMSK - Pin Change Enable Mask
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.equ PCINT0 = 0 ; Pin Change Enable Mask Bit 0
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.equ PCINT1 = 1 ; Pin Change Enable Mask Bit 1
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.equ PCINT2 = 2 ; Pin Change Enable Mask Bit 2
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.equ PCINT3 = 3 ; Pin Change Enable Mask Bit 3
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.equ PCINT4 = 4 ; Pin Change Enable Mask Bit 4
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.equ PCINT5 = 5 ; Pin Change Enable Mask Bit 5
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; ***** TIMER_COUNTER_0 **************
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; TIMSK0 - Timer/Counter0 Interrupt Mask Register
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.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable
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.equ OCIE0A = 2 ; Timer/Counter0 Output Compare Match A Interrupt Enable
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.equ OCIE0B = 3 ; Timer/Counter0 Output Compare Match B Interrupt Enable
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; TIFR0 - Timer/Counter0 Interrupt Flag register
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.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag
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.equ OCF0A = 2 ; Timer/Counter0 Output Compare Flag 0A
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.equ OCF0B = 3 ; Timer/Counter0 Output Compare Flag 0B
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; OCR0A - Timer/Counter0 Output Compare Register
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.equ OCR0_0 = 0 ;
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.equ OCR0_1 = 1 ;
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.equ OCR0_2 = 2 ;
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.equ OCR0_3 = 3 ;
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.equ OCR0_4 = 4 ;
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.equ OCR0_5 = 5 ;
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.equ OCR0_6 = 6 ;
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.equ OCR0_7 = 7 ;
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; TCCR0A - Timer/Counter Control Register A
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||
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.equ WGM00 = 0 ; Waveform Generation Mode
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|
.equ WGM01 = 1 ; Waveform Generation Mode
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||
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|
.equ COM0B0 = 4 ; Compare Match Output B Mode
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||
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|
.equ COM0B1 = 5 ; Compare Match Output B Mode
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||
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|
.equ COM0A0 = 6 ; Compare Match Output A Mode
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||
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.equ COM0A1 = 7 ; Compare Match Output A Mode
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||
|
|
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||
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|
; TCNT0 - Timer/Counter0
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||
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|
.equ TCNT0_0 = 0 ;
|
||
|
|
.equ TCNT0_1 = 1 ;
|
||
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|
.equ TCNT0_2 = 2 ;
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||
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|
.equ TCNT0_3 = 3 ;
|
||
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.equ TCNT0_4 = 4 ;
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||
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.equ TCNT0_5 = 5 ;
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||
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.equ TCNT0_6 = 6 ;
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||
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.equ TCNT0_7 = 7 ;
|
||
|
|
|
||
|
|
; TCCR0B - Timer/Counter Control Register B
|
||
|
|
.equ CS00 = 0 ; Clock Select
|
||
|
|
.equ CS01 = 1 ; Clock Select
|
||
|
|
.equ CS02 = 2 ; Clock Select
|
||
|
|
.equ WGM02 = 3 ; Waveform Generation Mode
|
||
|
|
.equ FOC0B = 6 ; Force Output Compare B
|
||
|
|
.equ FOC0A = 7 ; Force Output Compare A
|
||
|
|
|
||
|
|
; OCR0B - Timer/Counter0 Output Compare Register
|
||
|
|
;.equ OCR0_0 = 0 ;
|
||
|
|
;.equ OCR0_1 = 1 ;
|
||
|
|
;.equ OCR0_2 = 2 ;
|
||
|
|
;.equ OCR0_3 = 3 ;
|
||
|
|
;.equ OCR0_4 = 4 ;
|
||
|
|
;.equ OCR0_5 = 5 ;
|
||
|
|
;.equ OCR0_6 = 6 ;
|
||
|
|
;.equ OCR0_7 = 7 ;
|
||
|
|
|
||
|
|
; GTCCR - General Timer Conuter Register
|
||
|
|
.equ PSR10 = 0 ; Prescaler Reset Timer/Counter0
|
||
|
|
.equ TSM = 7 ; Timer/Counter Synchronization Mode
|
||
|
|
|
||
|
|
|
||
|
|
; ***** WATCHDOG *********************
|
||
|
|
; WDTCR - Watchdog Timer Control Register
|
||
|
|
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
|
||
|
|
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
|
||
|
|
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
|
||
|
|
.equ WDE = 3 ; Watch Dog Enable
|
||
|
|
.equ WDCE = 4 ; Watchdog Change Enable
|
||
|
|
.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3
|
||
|
|
.equ WDTIE = 6 ; Watchdog Timeout Interrupt Enable
|
||
|
|
.equ WDTIF = 7 ; Watchdog Timeout Interrupt Flag
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
; ***** LOCKSBITS ********************************************************
|
||
|
|
.equ LB1 = 0 ; Lockbit
|
||
|
|
.equ LB2 = 1 ; Lockbit
|
||
|
|
|
||
|
|
|
||
|
|
; ***** FUSES ************************************************************
|
||
|
|
; LOW fuse bits
|
||
|
|
.equ CKSEL0 = 0 ; Select Clock Source
|
||
|
|
.equ CKSEL1 = 1 ; Select Clock Source
|
||
|
|
.equ SUT0 = 2 ; Select start-up time
|
||
|
|
.equ SUT1 = 3 ; Select start-up time
|
||
|
|
.equ CKDIV8 = 4 ; Start up with system clock divided by 8
|
||
|
|
.equ WDTON = 5 ; Watch dog timer always on
|
||
|
|
.equ EESAVE = 6 ; Keep EEprom contents during chip erase
|
||
|
|
.equ SPIEN = 7 ; SPI programming enable
|
||
|
|
|
||
|
|
; HIGH fuse bits
|
||
|
|
.equ RSTDISBL = 0 ; Disable external reset
|
||
|
|
.equ BODLEVEL0 = 1 ; Enable BOD and select level
|
||
|
|
.equ BODLEVEL1 = 2 ; Enable BOD and select level
|
||
|
|
.equ DWEN = 3 ; DebugWire Enable
|
||
|
|
.equ SELFPRGEN = 4 ; Self Programming Enable
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
; ***** CPU REGISTER DEFINITIONS *****************************************
|
||
|
|
.def XH = r27
|
||
|
|
.def XL = r26
|
||
|
|
.def YH = r29
|
||
|
|
.def YL = r28
|
||
|
|
.def ZH = r31
|
||
|
|
.def ZL = r30
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
; ***** DATA MEMORY DECLARATIONS *****************************************
|
||
|
|
.equ FLASHEND = 0x01ff ; Note: Word address
|
||
|
|
.equ IOEND = 0x003f
|
||
|
|
.equ SRAM_START = 0x0060
|
||
|
|
.equ SRAM_SIZE = 64
|
||
|
|
.equ RAMEND = 0x009f
|
||
|
|
.equ XRAMEND = 0x0000
|
||
|
|
.equ E2END = 0x003f
|
||
|
|
.equ EEPROMEND = 0x003f
|
||
|
|
.equ EEADRBITS = 6
|
||
|
|
#pragma AVRPART MEMORY PROG_FLASH 1024
|
||
|
|
#pragma AVRPART MEMORY EEPROM 64
|
||
|
|
#pragma AVRPART MEMORY INT_SRAM SIZE 64
|
||
|
|
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
; ***** BOOTLOADER DECLARATIONS ******************************************
|
||
|
|
.equ PAGESIZE = 16
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
; ***** INTERRUPT VECTORS ************************************************
|
||
|
|
.equ INT0addr = 0x0001 ; External Interrupt 0
|
||
|
|
.equ PCI0addr = 0x0002 ; External Interrupt Request 0
|
||
|
|
.equ OVF0addr = 0x0003 ; Timer/Counter0 Overflow
|
||
|
|
.equ ERDYaddr = 0x0004 ; EEPROM Ready
|
||
|
|
.equ ACIaddr = 0x0005 ; Analog Comparator
|
||
|
|
.equ OC0Aaddr = 0x0006 ; Timer/Counter Compare Match A
|
||
|
|
.equ OC0Baddr = 0x0007 ; Timer/Counter Compare Match B
|
||
|
|
.equ WDTaddr = 0x0008 ; Watchdog Time-out
|
||
|
|
.equ ADCCaddr = 0x0009 ; ADC Conversion Complete
|
||
|
|
|
||
|
|
.equ INT_VECTORS_SIZE = 10 ; size in words
|
||
|
|
|
||
|
|
#endif /* _TN13DEF_INC_ */
|
||
|
|
|
||
|
|
; ***** END OF FILE ******************************************************
|