2011-12-18 14:35:29 +01:00
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/*
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* Intel AGPGART routines.
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*/
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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2015-01-05 20:15:42 +01:00
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#include <linux/gfp.h>
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2011-12-18 14:35:29 +01:00
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#include <linux/pci.h>
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2015-01-05 20:15:42 +01:00
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#include <linux/slab.h>
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2016-11-03 11:03:00 +01:00
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#include <linux/init.h>
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2015-01-05 20:15:42 +01:00
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#include <linux/kernel.h>
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#include <linux/agp_backend.h>
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#include "agp.h"
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#include "intel-agp.h"
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#include <drm/intel-gtt.h>
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2011-12-18 14:35:29 +01:00
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#include <linux/spinlock.h>
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2015-01-05 20:15:42 +01:00
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2011-12-18 14:35:29 +01:00
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#include <syscall.h>
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#define __devinit
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#define PCI_VENDOR_ID_INTEL 0x8086
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2012-01-30 08:06:25 +01:00
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#define PCI_DEVICE_ID_INTEL_82915G_HB 0x2580
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#define PCI_DEVICE_ID_INTEL_82915GM_HB 0x2590
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#define PCI_DEVICE_ID_INTEL_82945G_HB 0x2770
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#define PCI_DEVICE_ID_INTEL_82945GM_HB 0x27A0
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2011-12-18 14:35:29 +01:00
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2013-10-26 15:34:57 +02:00
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int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev,
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2011-12-18 14:35:29 +01:00
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struct agp_bridge_data *bridge);
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int intel_agp_enabled;
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struct agp_bridge_data *agp_alloc_bridge(void)
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{
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struct agp_bridge_data *bridge;
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bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
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if (!bridge)
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return NULL;
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atomic_set(&bridge->agp_in_use, 0);
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atomic_set(&bridge->current_memory_agp, 0);
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// if (list_empty(&agp_bridges))
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// agp_bridge = bridge;
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return bridge;
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}
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static int __devinit agp_intel_probe(struct pci_dev *pdev,
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const struct pci_device_id *ent)
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{
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struct agp_bridge_data *bridge;
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u8 cap_ptr = 0;
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int err = -ENODEV;
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cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
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bridge = agp_alloc_bridge();
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if (!bridge)
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return -ENOMEM;
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bridge->capndx = cap_ptr;
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2013-10-26 15:34:57 +02:00
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if (intel_gmch_probe(pdev, NULL, bridge))
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2011-12-18 14:35:29 +01:00
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{
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// pci_set_drvdata(pdev, bridge);
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// err = agp_add_bridge(bridge);
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// if (!err)
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intel_agp_enabled = 1;
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err = 0;
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}
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return err;
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}
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static struct pci_device_id agp_intel_pci_table[] = {
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#define ID(x) \
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{ \
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.class = (PCI_CLASS_BRIDGE_HOST << 8), \
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.class_mask = ~0, \
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.vendor = PCI_VENDOR_ID_INTEL, \
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.device = x, \
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.subvendor = PCI_ANY_ID, \
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.subdevice = PCI_ANY_ID, \
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}
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2012-01-30 08:06:25 +01:00
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ID(PCI_DEVICE_ID_INTEL_E7221_HB),
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ID(PCI_DEVICE_ID_INTEL_82915G_HB),
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ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
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ID(PCI_DEVICE_ID_INTEL_82945G_HB),
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ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
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ID(PCI_DEVICE_ID_INTEL_82945GME_HB),
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ID(PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB),
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ID(PCI_DEVICE_ID_INTEL_PINEVIEW_HB),
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ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
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ID(PCI_DEVICE_ID_INTEL_82G35_HB),
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ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
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ID(PCI_DEVICE_ID_INTEL_82965G_HB),
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ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
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ID(PCI_DEVICE_ID_INTEL_82965GME_HB),
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ID(PCI_DEVICE_ID_INTEL_G33_HB),
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ID(PCI_DEVICE_ID_INTEL_Q35_HB),
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ID(PCI_DEVICE_ID_INTEL_Q33_HB),
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ID(PCI_DEVICE_ID_INTEL_GM45_HB),
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ID(PCI_DEVICE_ID_INTEL_EAGLELAKE_HB),
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ID(PCI_DEVICE_ID_INTEL_Q45_HB),
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ID(PCI_DEVICE_ID_INTEL_G45_HB),
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ID(PCI_DEVICE_ID_INTEL_G41_HB),
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ID(PCI_DEVICE_ID_INTEL_B43_HB),
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ID(PCI_DEVICE_ID_INTEL_B43_1_HB),
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ID(PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB),
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2012-11-12 22:22:52 +01:00
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ID(PCI_DEVICE_ID_INTEL_IRONLAKE_D2_HB),
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2012-01-30 08:06:25 +01:00
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ID(PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB),
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ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB),
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ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB),
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2011-12-18 14:35:29 +01:00
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{ }
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};
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static pci_dev_t agp_device;
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int init_agp(void)
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{
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const struct pci_device_id *ent;
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ent = find_pci_device(&agp_device, agp_intel_pci_table);
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if( unlikely(ent == NULL) )
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{
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dbgprintf("host controller not found\n");
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return -ENODEV;
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};
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return agp_intel_probe(&agp_device.pci_dev, ent);
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}
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