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Intel-2D: sna static stream initialization

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git-svn-id: svn://kolibrios.org@3258 a494cfbc-eb01-0410-851d-a64ba20cac60
This commit is contained in:
Sergey Semyonov (Serge) 2013-02-19 17:03:18 +00:00
parent 89bfe5f5d6
commit 1633df9e80
6 changed files with 2809 additions and 189 deletions
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22
drivers/video/Intel-2D/gen6_render.c
View File

@ -397,7 +397,7 @@ gen6_choose_composite_kernel(int op, bool has_mask, bool is_ca, bool is_affine)
/* /*
if (is_ca) { if (is_ca) {
if (gen6_blend_op[op].src_alpha) if (gen6_blend_op[op].src_alpha)
base = GEN6_WM_KERNEL_MASKCA_SRCALPHA; base = GEN6_WM_KERNEL_MASKSA;
else else
base = GEN6_WM_KERNEL_MASKCA; base = GEN6_WM_KERNEL_MASKCA;
} else } else
@ -1647,7 +1647,7 @@ gen6_render_video(struct sna *sna,
_kgem_set_mode(&sna->kgem, KGEM_RENDER); _kgem_set_mode(&sna->kgem, KGEM_RENDER);
} }
gen6_emit_video_state(sna, &tmp, frame); gen6_emit_video_state(sna, &tmp);
gen6_align_vertex(sna, &tmp); gen6_align_vertex(sna, &tmp);
/* Set up the offset for translating from the given region (in screen /* Set up the offset for translating from the given region (in screen
@ -1815,10 +1815,10 @@ static void gen6_render_composite_done(struct sna *sna,
gen6_magic_ca_pass(sna, op); gen6_magic_ca_pass(sna, op);
} }
// if (op->mask.bo) if (op->mask.bo)
// kgem_bo_destroy(&sna->kgem, op->mask.bo); kgem_bo_destroy(&sna->kgem, op->mask.bo);
// if (op->src.bo) if (op->src.bo)
// kgem_bo_destroy(&sna->kgem, op->src.bo); kgem_bo_destroy(&sna->kgem, op->src.bo);
// sna_render_composite_redirect_done(sna, op); // sna_render_composite_redirect_done(sna, op);
} }
@ -3223,7 +3223,7 @@ static void gen6_render_reset(struct sna *sna)
static void gen6_render_fini(struct sna *sna) static void gen6_render_fini(struct sna *sna)
{ {
// kgem_bo_destroy(&sna->kgem, sna->render_state.gen6.general_bo); kgem_bo_destroy(&sna->kgem, sna->render_state.gen6.general_bo);
} }
static bool is_gt2(struct sna *sna) static bool is_gt2(struct sna *sna)
@ -3333,7 +3333,7 @@ bool gen6_render_init(struct sna *sna)
// sna->render.fill_one = gen6_render_fill_one; // sna->render.fill_one = gen6_render_fill_one;
// sna->render.clear = gen6_render_clear; // sna->render.clear = gen6_render_clear;
// sna->render.flush = gen6_render_flush; sna->render.flush = gen6_render_flush;
sna->render.reset = gen6_render_reset; sna->render.reset = gen6_render_reset;
sna->render.fini = gen6_render_fini; sna->render.fini = gen6_render_fini;
@ -3445,9 +3445,3 @@ int gen4_vertex_finish(struct sna *sna)
return sna->render.vertex_size - sna->render.vertex_used; return sna->render.vertex_size - sna->render.vertex_used;
} }
void *kgem_bo_map(struct kgem *kgem, struct kgem_bo *bo)
{
return NULL;
};

96
drivers/video/Intel-2D/i915_drm.h
View File

@ -199,54 +199,54 @@ typedef struct _drm_i915_sarea {
#define DRM_I915_GEM_GET_CACHEING 0x30 #define DRM_I915_GEM_GET_CACHEING 0x30
#define DRM_I915_REG_READ 0x31 #define DRM_I915_REG_READ 0x31
#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) #define DRM_IOCTL_I915_INIT
#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) #define DRM_IOCTL_I915_FLUSH
#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) #define DRM_IOCTL_I915_FLIP
#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) #define DRM_IOCTL_I915_BATCHBUFFER
#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) #define DRM_IOCTL_I915_IRQ_EMIT
#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) #define DRM_IOCTL_I915_IRQ_WAIT
#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) #define DRM_IOCTL_I915_GETPARAM SRV_GET_PARAM
#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) #define DRM_IOCTL_I915_SETPARAM
#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) #define DRM_IOCTL_I915_ALLOC
#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) #define DRM_IOCTL_I915_FREE
#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) #define DRM_IOCTL_I915_INIT_HEAP
#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) #define DRM_IOCTL_I915_CMDBUFFER
#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) #define DRM_IOCTL_I915_DESTROY_HEAP
#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) #define DRM_IOCTL_I915_SET_VBLANK_PIPE
#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) #define DRM_IOCTL_I915_GET_VBLANK_PIPE
#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) #define DRM_IOCTL_I915_VBLANK_SWAP
#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) #define DRM_IOCTL_I915_HWS_ADDR
#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) #define DRM_IOCTL_I915_GEM_INIT
#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) #define DRM_IOCTL_I915_GEM_EXECBUFFER
#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) #define DRM_IOCTL_I915_GEM_EXECBUFFER2
#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) #define DRM_IOCTL_I915_GEM_PIN SRV_I915_GEM_PIN
#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) #define DRM_IOCTL_I915_GEM_UNPIN
#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) #define DRM_IOCTL_I915_GEM_BUSY SRV_I915_GEM_BUSY
#define DRM_IOCTL_I915_GEM_SET_CACHEING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHEING, struct drm_i915_gem_cacheing) #define DRM_IOCTL_I915_GEM_SET_CACHEING SRV_I915_GEM_SET_CACHEING
#define DRM_IOCTL_I915_GEM_GET_CACHEING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHEING, struct drm_i915_gem_cacheing) #define DRM_IOCTL_I915_GEM_GET_CACHEING
#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) #define DRM_IOCTL_I915_GEM_THROTTLE
#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) #define DRM_IOCTL_I915_GEM_ENTERVT
#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) #define DRM_IOCTL_I915_GEM_LEAVEVT
#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) #define DRM_IOCTL_I915_GEM_CREATE SRV_I915_GEM_CREATE
#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) #define DRM_IOCTL_I915_GEM_PREAD
#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) #define DRM_IOCTL_I915_GEM_PWRITE SRV_I915_GEM_PWRITE
#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) #define DRM_IOCTL_I915_GEM_MMAP SRV_I915_GEM_MMAP
#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) #define DRM_IOCTL_I915_GEM_MMAP_GTT SRV_I915_GEM_MMAP_GTT
#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) #define DRM_IOCTL_I915_GEM_SET_DOMAIN SRV_I915_GEM_SET_DOMAIN
#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) #define DRM_IOCTL_I915_GEM_SW_FINISH
#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) #define DRM_IOCTL_I915_GEM_SET_TILING
#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) #define DRM_IOCTL_I915_GEM_GET_TILING
#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) #define DRM_IOCTL_I915_GEM_GET_APERTURE SRV_I915_GEM_GET_APERTURE
#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID
#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) #define DRM_IOCTL_I915_GEM_MADVISE
#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE
#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) #define DRM_IOCTL_I915_OVERLAY_ATTRS
#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY
#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY
#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) #define DRM_IOCTL_I915_GEM_WAIT
#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE
#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY
#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) #define DRM_IOCTL_I915_REG_READ
/* Allow drivers to submit batchbuffers directly to hardware, relying /* Allow drivers to submit batchbuffers directly to hardware, relying
* on the security mechanisms provided by hardware. * on the security mechanisms provided by hardware.

2752
drivers/video/Intel-2D/kgem-sna.c
View File

File diff suppressed because it is too large Load Diff

49
drivers/video/Intel-2D/kgem.h
View File

@ -273,6 +273,11 @@ struct kgem_bo *kgem_create_2d(struct kgem *kgem,
int bpp, int bpp,
int tiling, int tiling,
uint32_t flags); uint32_t flags);
struct kgem_bo *kgem_create_cpu_2d(struct kgem *kgem,
int width,
int height,
int bpp,
uint32_t flags);
uint32_t kgem_bo_get_binding(struct kgem_bo *bo, uint32_t format); uint32_t kgem_bo_get_binding(struct kgem_bo *bo, uint32_t format);
void kgem_bo_set_binding(struct kgem_bo *bo, uint32_t format, uint16_t offset); void kgem_bo_set_binding(struct kgem_bo *bo, uint32_t format, uint16_t offset);
@ -314,8 +319,6 @@ static inline bool kgem_flush(struct kgem *kgem, bool flush)
return (kgem->flush ^ flush) && kgem_ring_is_idle(kgem, kgem->ring); return (kgem->flush ^ flush) && kgem_ring_is_idle(kgem, kgem->ring);
} }
#if 0
static inline void kgem_bo_submit(struct kgem *kgem, struct kgem_bo *bo) static inline void kgem_bo_submit(struct kgem *kgem, struct kgem_bo *bo)
{ {
if (bo->exec) if (bo->exec)
@ -337,8 +340,6 @@ static inline void kgem_bo_flush(struct kgem *kgem, struct kgem_bo *bo)
__kgem_flush(kgem, bo); __kgem_flush(kgem, bo);
} }
#endif
static inline struct kgem_bo *kgem_bo_reference(struct kgem_bo *bo) static inline struct kgem_bo *kgem_bo_reference(struct kgem_bo *bo)
{ {
assert(bo->refcnt); assert(bo->refcnt);
@ -517,6 +518,15 @@ static inline bool __kgem_bo_is_mappable(struct kgem *kgem,
return bo->presumed_offset + kgem_bo_size(bo) <= kgem->aperture_mappable; return bo->presumed_offset + kgem_bo_size(bo) <= kgem->aperture_mappable;
} }
static inline bool kgem_bo_is_mappable(struct kgem *kgem,
struct kgem_bo *bo)
{
DBG(("%s: domain=%d, offset: %d size: %d\n",
__FUNCTION__, bo->domain, bo->presumed_offset, kgem_bo_size(bo)));
assert(bo->refcnt);
return __kgem_bo_is_mappable(kgem, bo);
}
static inline bool kgem_bo_mapped(struct kgem *kgem, struct kgem_bo *bo) static inline bool kgem_bo_mapped(struct kgem *kgem, struct kgem_bo *bo)
{ {
DBG(("%s: map=%p, tiling=%d, domain=%d\n", DBG(("%s: map=%p, tiling=%d, domain=%d\n",
@ -529,15 +539,42 @@ static inline bool kgem_bo_mapped(struct kgem *kgem, struct kgem_bo *bo)
return IS_CPU_MAP(bo->map) == !bo->tiling; return IS_CPU_MAP(bo->map) == !bo->tiling;
} }
static inline bool kgem_bo_can_map(struct kgem *kgem, struct kgem_bo *bo)
{
if (kgem_bo_mapped(kgem, bo))
return true;
if (!bo->tiling && kgem->has_llc)
return true;
if (kgem->gen == 021 && bo->tiling == I915_TILING_Y)
return false;
return kgem_bo_size(bo) <= kgem->aperture_mappable / 4;
}
static inline bool kgem_bo_is_snoop(struct kgem_bo *bo)
{
assert(bo->refcnt);
while (bo->proxy)
bo = bo->proxy;
return bo->snoop;
}
bool __kgem_busy(struct kgem *kgem, int handle);
static inline void kgem_bo_mark_busy(struct kgem_bo *bo, int ring)
{
bo->rq = (struct kgem_request *)((uintptr_t)bo->rq | ring);
}
inline static void __kgem_bo_clear_busy(struct kgem_bo *bo)
{
bo->needs_flush = false;
list_del(&bo->request);
bo->rq = NULL;
bo->domain = DOMAIN_NONE;
}
static inline bool kgem_bo_is_busy(struct kgem_bo *bo) static inline bool kgem_bo_is_busy(struct kgem_bo *bo)
{ {

47
drivers/video/Intel-2D/sna.c
View File

@ -5,6 +5,28 @@
#include "sna.h" #include "sna.h"
typedef struct __attribute__((packed))
{
unsigned handle;
unsigned io_code;
void *input;
int inp_size;
void *output;
int out_size;
}ioctl_t;
static int call_service(ioctl_t *io)
{
int retval;
asm volatile("int $0x40"
:"=a"(retval)
:"a"(68),"b"(17),"c"(io)
:"memory","cc");
return retval;
};
const struct intel_device_info * const struct intel_device_info *
intel_detect_chipset(struct pci_device *pci); intel_detect_chipset(struct pci_device *pci);
@ -15,6 +37,11 @@ static bool sna_solid_cache_init(struct sna *sna);
struct sna *sna_device; struct sna *sna_device;
static void no_render_reset(struct sna *sna)
{
(void)sna;
}
void no_render_init(struct sna *sna) void no_render_init(struct sna *sna)
{ {
struct sna_render *render = &sna->render; struct sna_render *render = &sna->render;
@ -36,14 +63,14 @@ void no_render_init(struct sna *sna)
// render->fill_one = no_render_fill_one; // render->fill_one = no_render_fill_one;
// render->clear = no_render_clear; // render->clear = no_render_clear;
// render->reset = no_render_reset; render->reset = no_render_reset;
// render->flush = no_render_flush; render->flush = no_render_flush;
// render->fini = no_render_fini; // render->fini = no_render_fini;
// sna->kgem.context_switch = no_render_context_switch; // sna->kgem.context_switch = no_render_context_switch;
// sna->kgem.retire = no_render_retire; // sna->kgem.retire = no_render_retire;
// if (sna->kgem.gen >= 60) if (sna->kgem.gen >= 60)
sna->kgem.ring = KGEM_RENDER; sna->kgem.ring = KGEM_RENDER;
sna_vertex_init(sna); sna_vertex_init(sna);
@ -594,5 +621,19 @@ intel_detect_chipset(struct pci_device *pci)
} }
int drmIoctl(int fd, unsigned long request, void *arg)
{
ioctl_t io;
io.handle = fd;
io.io_code = request;
io.input = arg;
io.inp_size = 64;
io.output = NULL;
io.out_size = 0;
return call_service(&io);
}

26
drivers/video/Intel-2D/sna.h
View File

@ -57,15 +57,8 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define assert(x) #define assert(x)
typedef struct int drmIoctl(int fd, unsigned long request, void *arg);
{
unsigned handle;
unsigned io_code;
void *input;
int inp_size;
void *output;
int out_size;
}ioctl_t;
#define SRV_GET_PCI_INFO 20 #define SRV_GET_PCI_INFO 20
#define SRV_GET_PARAM 21 #define SRV_GET_PARAM 21
@ -74,19 +67,16 @@ typedef struct
#define SRV_I915_GEM_PIN 24 #define SRV_I915_GEM_PIN 24
#define SRV_I915_GEM_SET_CACHEING 25 #define SRV_I915_GEM_SET_CACHEING 25
#define SRV_I915_GEM_GET_APERTURE 26 #define SRV_I915_GEM_GET_APERTURE 26
#define SRV_I915_GEM_PWRITE 27
#define SRV_I915_GEM_BUSY 28
static int call_service(ioctl_t *io) #define SRV_I915_GEM_SET_DOMAIN 29
{ #define SRV_I915_GEM_MMAP 30
int retval; #define SRV_I915_GEM_MMAP_GTT 31
asm volatile("int $0x40"
:"=a"(retval)
:"a"(68),"b"(17),"c"(io)
:"memory","cc");
return retval;
};
#define DRM_IOCTL_GEM_CLOSE SRV_DRM_GEM_CLOSE
#define PIXMAN_FORMAT(bpp,type,a,r,g,b) (((bpp) << 24) | \ #define PIXMAN_FORMAT(bpp,type,a,r,g,b) (((bpp) << 24) | \
((type) << 16) | \ ((type) << 16) | \