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PCIe config bugs fixed

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git-svn-id: svn://kolibrios.org@1560 a494cfbc-eb01-0410-851d-a64ba20cac60
This commit is contained in:
Artem Jerdev (art_zh) 2010-08-07 12:38:03 +00:00
parent 08ea0b5f68
commit 849a203279
5 changed files with 69 additions and 199 deletions
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47
kernel/branches/Kolibri-A/trunk/bus/HT.INC
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@ -11,15 +11,16 @@
;; ;; ;; ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
$Revision: 1554 $
align 4
;============================================================================= ;=============================================================================
; ;
; This code is a part of Kolibri-A and will only work with AMD RS760+ chipsets ; This code is a part of Kolibri-A and will only work with AMD RS760+ chipsets
; ;
;============================================================================= ;=============================================================================
align 4
;------------------------------------------ ;------------------------------------------
; params: al = nbconfig register# ; params: al = nbconfig register#
@ -33,6 +34,7 @@ rs7xx_nbconfig_read_pci:
add dl, 4 add dl, 4
in eax, dx in eax, dx
ret ret
align 4
rs7xx_nbconfig_flush_pci: rs7xx_nbconfig_flush_pci:
mov eax, 0x0B0 ; a scratch reg mov eax, 0x0B0 ; a scratch reg
@ -40,6 +42,7 @@ rs7xx_nbconfig_flush_pci:
out dx, eax out dx, eax
ret ret
align 4
rs7xx_nbconfig_write_pci: rs7xx_nbconfig_write_pci:
and eax, 0x0FC ; leave register# only and eax, 0x0FC ; leave register# only
@ -60,10 +63,9 @@ rs7xx_nbconfig_write_pci:
; ;
;*************************************************************************** ;***************************************************************************
align 4
rs7xx_pcie_init: rs7xx_pcie_init:
; mov al, 0x7C ; NB_IOC_CFG_CNTL
; mov ebx, 0x20000000
; call rs7xx_nbconfig_write_pci
mov al, 0x7C ; NB_IOC_CFG_CNTL mov al, 0x7C ; NB_IOC_CFG_CNTL
call rs7xx_nbconfig_read_pci call rs7xx_nbconfig_read_pci
mov ebx, eax mov ebx, eax
@ -98,47 +100,50 @@ rs7xx_pcie_init:
call rs7xx_nbconfig_flush_pci call rs7xx_nbconfig_flush_pci
mov eax, ebx mov eax, ebx
and eax, 0xFFE00000 ; valid bits [31..21] and eax, 0xFFE00000 ; valid bits [31..21]
jnz @f ; NB BAR3 may be invisible! jz .rs7xx_pcie_blocked ; NB BAR3 may be invisible!
call pci_ext_config ; try to get pcie ecfg address indirectly ; try to get pcie ecfg address indirectly
@@: .addr_found:
or eax, eax
jz .rs7xx_pcie_fail
mov [mmio_pcie_cfg_addr], eax ; physical address (lower 32 bits) mov [mmio_pcie_cfg_addr], eax ; physical address (lower 32 bits)
add [mmio_pcie_cfg_lim], eax add [mmio_pcie_cfg_lim], eax
; -- map the whole PCIe config space;
or eax, (PG_SHARED + PG_LARGE + PG_UW) ; by the way, UW is unsafe! or eax, (PG_SHARED + PG_LARGE + PG_UW) ; by the way, UW is unsafe!
mov ecx, PCIe_CONFIG_SPACE ; linear address mov ecx, PCIe_CONFIG_SPACE ; linear address
mov ebx, ecx mov ebx, ecx
shr ebx, 20 shr ebx, 20
add ebx, sys_pgdir ; PgDir entry @ add ebx, sys_pgdir ; PgDir entry @
xor dx, dx ; PDEs counter mov dl, byte[mmio_pcie_cfg_pdes] ; 1 page = 4M in address space
cmp dl, (USER_DMA_BUFFER - PCIe_CONFIG_SPACE) / 4194304
jb @f
mov dl, ((USER_DMA_BUFFER - PCIe_CONFIG_SPACE) / 4194304) - 1
mov byte[mmio_pcie_cfg_pdes], dl
@@: @@:
mov dword[ebx], eax ; map 4 buses xor dx, dx ; PDEs counter
@@:
mov dword[ebx], eax ; map 4 buses
invlpg [ecx] ; next PgDir entry invlpg [ecx] ; next PgDir entry
add bx, 4 ; new PDE add bx, 4 ; new PDE
add eax, 0x400000 ; +4M phys. add eax, 0x400000 ; +4M phys.
add ecx, 0x400000 ; +4M lin. add ecx, 0x400000 ; +4M lin.
inc dx cmp dl, byte[mmio_pcie_cfg_pdes]
cmp dx, [mmio_pcie_cfg_pdes] ; all mapped yet? jnc .pcie_cfg_mapped
jnz @b inc dl
jmp @b
.pcie_cfg_mapped: .pcie_cfg_mapped:
mov esi, boot_pcie_ok mov esi, boot_pcie_ok
call boot_log call boot_log
ret ; <<<<<<<<<<< OK >>>>>>>>>>> ret ; <<< OK >>>
.rs7xx_pcie_fail: .rs7xx_pcie_fail:
mov esi, boot_rs7xx_fail mov esi, boot_rs7xx_fail
call boot_log call boot_log
ret ret
.rs7xx_pcie_blocked: .rs7xx_pcie_blocked:
mov esi, boot_rs7xx_blkd mov esi, boot_rs7xx_blkd
call boot_log call boot_log
call pci_ext_config
jmp .addr_found
ret ret

57
kernel/branches/Kolibri-A/trunk/bus/pci/PCIe.inc
View File

@ -8,11 +8,11 @@
;; ;; ;; ;;
;; Extended PCI express services ;; ;; Extended PCI express services ;;
;; ;; ;; ;;
;; art_zh <artem@jerdev.co.uk> ;; ;; art_zh <artem@jerdev.co.uk> ;;
;; ;; ;; ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
$Revision: 1463 $ $Revision: 1554 $
;*************************************************************************** ;***************************************************************************
; Function ; Function
@ -21,31 +21,32 @@ $Revision: 1463 $
; Description ; Description
; PCIe extended (memory-mapped) config space detection ; PCIe extended (memory-mapped) config space detection
; ;
; WARNINGs: ; WARNINGs:
; 1) Very Experimental! ; 1) Very Experimental!
; 2) direct HT-detection (no ACPI or BIOS service used) ; 2) direct HT-detection (no ACPI or BIOS service used)
; 3) Only AMD/HT processors currently supported ; 3) Only AMD/HT processors currently supported
; ;
;*************************************************************************** ;***************************************************************************
align 4 align 4
mmio_pcie_cfg_addr dd 0x00000000 ; pcie space may be defined here mmio_pcie_cfg_addr dd 0x00000000 ; pcie space may be defined here
mmio_pcie_cfg_lim dd 0x000FFFFF ; upper pcie space address mmio_pcie_cfg_lim dd 0x000FFFFF ; upper pcie space address
mmio_pcie_cfg_pdes dw 0 ; number of PDEs to map the space mmio_pcie_cfg_pdes dw 1 ; number of PDEs to map the space
PCIe_bus_range dw 0 ; the Bus range: power-of-2 Megabytes PCIe_bus_range dw 2 ; the Bus range: power-of-2 Megabytes
align 4 align 4
pci_ext_config: pci_ext_config:
mov ebx, [mmio_pcie_cfg_addr] mov eax, [mmio_pcie_cfg_addr]
or ebx,ebx mov ebx, eax
or ebx, ebx
jz @f jz @f
or ebx, 0x7FFFFFFF ; required by PCI-SIG standards or ebx, 0x7FFFFFFF ; required by PCI-SIG standards
jnz .pcie_failed jnz .pcie_failed
add ebx, 0x0FFFFC add ebx, 0x0FFFFC
cmp ebx, [mmio_pcie_cfg_lim]; is the space limit correct? cmp ebx, [mmio_pcie_cfg_lim]; is the space limit correct?
ja .pcie_failed ja .pcie_failed
jmp .pcie_cfg_mapped ret ; return the address forced
@@: @@:
mov ebx, [cpu_vendor] mov ebx, [cpu_vendor]
cmp ebx, dword [AMD_str] cmp ebx, dword [AMD_str]
@ -55,17 +56,17 @@ pci_ext_config:
.check_HT_mmio: .check_HT_mmio:
mov cx, bx mov cx, bx
mov ax, 0x0002 ; bus = 0, 1dword to read mov ax, 0x0002 ; bus = 0, 1dword to read
call pci_read_reg call pci_read_reg
mov bx, cx mov bx, cx
sub bl, 4 sub bl, 4
and al, 0x80 ; check the NP bit and al, 0x80 ; check the NP bit
jz .no_pcie_cfg jz .no_pcie_cfg
shl eax, 8 ; bus:[27..20], dev:[19:15] shl eax, 8 ; bus:[27..20], dev:[19:15]
or eax, 0x00007FFC ; fun:[14..12], reg:[11:2] or eax, 0x00007FFC ; fun:[14..12], reg:[11:2]
; mov [mmio_pcie_cfg_lim], eax ; mov [mmio_pcie_cfg_lim], eax
mov cl, bl mov cl, bl
mov ax, 0x0002 ; bus = 0, 1dword to read mov ax, 0x0002 ; bus = 0, 1dword to read
call pci_read_reg call pci_read_reg
mov bx, cx mov bx, cx
test al, 0x03 ; MMIO Base RW enabled? test al, 0x03 ; MMIO Base RW enabled?
jz .no_pcie_cfg jz .no_pcie_cfg
@ -73,29 +74,21 @@ pci_ext_config:
jnz .no_pcie_cfg jnz .no_pcie_cfg
xor al, al xor al, al
shl eax, 8 shl eax, 8
test eax, 0x000F0000 ; MMIO Base must be bus0-aligned test eax, 0x000F0000 ; MMIO Base must be bus0-aligned
jnz .no_pcie_cfg jnz .no_pcie_cfg
mov [mmio_pcie_cfg_addr], eax
; add eax, 0x000FFFFC
; sub eax,[mmio_pcie_cfg_lim] ; MMIO must cover at least one bus
; ja .no_pcie_cfg
; -- it looks like a true PCIe config space; ; -- it looks like a true PCIe config space;
.pcie_cfg_mapped:
mov esi, boot_pcie_ok
call boot_log
ret ; <<<<<<<<<<< OK >>>>>>>>>>> ret ; <<<<<<<<<<< OK >>>>>>>>>>>
.no_pcie_cfg:
.no_pcie_cfg:
xor eax, eax xor eax, eax
mov [mmio_pcie_cfg_addr], eax mov [mmio_pcie_cfg_addr], eax
mov [mmio_pcie_cfg_lim], eax mov [mmio_pcie_cfg_lim], eax
add bl, 12 add bl, 12
cmp bl, 0xC0 ; MMIO regs lay below this offset cmp bl, 0xC0 ; MMIO regs lay below this offset
jb .check_HT_mmio jb .check_HT_mmio
.pcie_failed: .pcie_failed:
mov esi, boot_pcie_fail mov esi, boot_pcie_fail
call boot_log call boot_log

155
kernel/branches/Kolibri-A/trunk/bus/pci/pci32.inc
View File

@ -32,7 +32,7 @@ $Revision$
; Description ; Description
; entry point for system PCI calls ; entry point for system PCI calls
;*************************************************************************** ;***************************************************************************
mmio_pci_addr dw 0x400 ; default PCI device bdf-address mmio_pci_addr dw 0x400 ; default PCI device bdf-address
align 4 align 4
@ -78,7 +78,7 @@ pci_fn_3:
cmp al,10 cmp al,10
jz pci_write_reg ;dword jz pci_write_reg ;dword
cmp al,11 ; user-level MMIO functions cmp al,11 ; user-level MMIO functions
jz pci_mmio_init jz pci_mmio_init
cmp al,12 cmp al,12
jz pci_mmio_map jz pci_mmio_map
@ -128,10 +128,6 @@ pci_make_config_cmd:
align 4 align 4
pci_read_reg: pci_read_reg:
cmp byte [BOOT_VAR+0x9020],2 ;what mechanism will we use?
je pci_read_reg_2
; mechanism 1
push esi ; save register size into ESI push esi ; save register size into ESI
mov esi,eax mov esi,eax
and esi,3 and esi,3
@ -174,66 +170,6 @@ pci_fin_read1:
mov dx,0xcf8 mov dx,0xcf8
out dx,eax out dx,eax
pop eax
pop esi
ret
pci_read_reg_2:
test bh,128 ;mech#2 only supports 16 devices per bus
jnz pci_read_reg_err
push esi ; save register size into ESI
mov esi,eax
and esi,3
push eax
;store current state of config space
mov dx,0xcf8
in al,dx
mov ah,al
mov dl,0xfa
in al,dx
xchg eax,[esp]
; out 0xcfa,bus
mov al,ah
out dx,al
; out 0xcf8,0x80
mov dl,0xf8
mov al,0x80
out dx,al
; compute addr
shr bh,3 ; func is ignored in mechanism 2
or bh,0xc0
mov dx,bx
or esi,esi
jz pci_read_byte2
cmp esi,1
jz pci_read_word2
cmp esi,2
jz pci_read_dword2
jmp pci_fin_read2
pci_read_byte2:
in al,dx
jmp pci_fin_read2
pci_read_word2:
in ax,dx
jmp pci_fin_read2
pci_read_dword2:
in eax,dx
; jmp pci_fin_read2
pci_fin_read2:
; restore configuration space
xchg eax,[esp]
mov dx,0xcfa
out dx,al
mov dl,0xf8
mov al,ah
out dx,al
pop eax pop eax
pop esi pop esi
ret ret
@ -259,10 +195,6 @@ pci_read_reg_err:
align 4 align 4
pci_write_reg: pci_write_reg:
cmp byte [BOOT_VAR+0x9020],2 ;what mechanism will we use?
je pci_write_reg_2
; mechanism 1
push esi ; save register size into ESI push esi ; save register size into ESI
mov esi,eax mov esi,eax
and esi,3 and esi,3
@ -301,74 +233,11 @@ pci_write_dword1:
out dx,eax out dx,eax
jmp pci_fin_write1 jmp pci_fin_write1
pci_fin_write1: pci_fin_write1:
; restore configuration control ; restore configuration control
pop eax pop eax
mov dl,0xf8 mov dl,0xf8
out dx,eax out dx,eax
xor eax,eax
pop esi
ret
pci_write_reg_2:
test bh,128 ;mech#2 only supports 16 devices per bus
jnz pci_write_reg_err
push esi ; save register size into ESI
mov esi,eax
and esi,3
push eax
;store current state of config space
mov dx,0xcf8
in al,dx
mov ah,al
mov dl,0xfa
in al,dx
xchg eax,[esp]
; out 0xcfa,bus
mov al,ah
out dx,al
; out 0xcf8,0x80
mov dl,0xf8
mov al,0x80
out dx,al
; compute addr
shr bh,3 ; func is ignored in mechanism 2
or bh,0xc0
mov dx,bx
; write register
mov eax,ecx
or esi,esi
jz pci_write_byte2
cmp esi,1
jz pci_write_word2
cmp esi,2
jz pci_write_dword2
jmp pci_fin_write2
pci_write_byte2:
out dx,al
jmp pci_fin_write2
pci_write_word2:
out dx,ax
jmp pci_fin_write2
pci_write_dword2:
out dx,eax
jmp pci_fin_write2
pci_fin_write2:
; restore configuration space
pop eax
mov dx,0xcfa
out dx,al
mov dl,0xf8
mov al,ah
out dx,al
xor eax,eax xor eax,eax
pop esi pop esi
ret ret
@ -380,11 +249,11 @@ pci_write_reg_err:
;*************************************************************************** ;***************************************************************************
; Function ; Function
; pci_mmio_init ; pci_mmio_init
; ;
; Description ; Description
; IN: bx = device's PCI bus address (bbbbbbbbdddddfff) ; IN: bx = device's PCI bus address (bbbbbbbbdddddfff)
; Returns eax = phys. address of user-accessible DMA block ; Returns eax = phys. address of user-accessible DMA block
; Error codes ; Error codes
; eax = -1 : PCI user access blocked, ; eax = -1 : PCI user access blocked,
; eax = -3 : user heap initialization failure ; eax = -3 : user heap initialization failure
@ -404,14 +273,14 @@ pci_mmio_init:
;*************************************************************************** ;***************************************************************************
; Function ; Function
; pci_mmio_map ; pci_mmio_map
; ;
; Description ; Description
; maps a block of PCI memory to user-accessible linear address ; maps a block of PCI memory to user-accessible linear address
; ;
; ;
; IN: ah = BAR#; or ; IN: ah = BAR#; or
; IN: ah = 0xDA for DMA-mapping requests; ; IN: ah = 0xDA for DMA-mapping requests;
; IN: ebx = block size (bytes); ; IN: ebx = block size (bytes);
; IN: ecx = offset in MMIO block (in 4K-pages, to avoid misaligned pages); ; IN: ecx = offset in MMIO block (in 4K-pages, to avoid misaligned pages);
; ;
@ -429,10 +298,10 @@ pci_mmio_init:
pci_mmio_map: pci_mmio_map:
and edx,0x0ffff and edx,0x0ffff
cmp ah, 0xDA cmp ah, 0xDA
jz .dma_map jz .dma_map
cmp ah,6 cmp ah,6
jc .bar_0_5 jc .bar_0_5
jz .bar_rom jz .bar_rom
mov eax,-2 mov eax,-2
ret ret
@ -441,7 +310,7 @@ pci_mmio_map:
mov ecx,ebx mov ecx,ebx
mov eax,[UserDMAaddr] mov eax,[UserDMAaddr]
jmp .allocate_block jmp .allocate_block
.bar_rom: .bar_rom:
mov ah, 8 ; bar6 = Expansion ROM base address mov ah, 8 ; bar6 = Expansion ROM base address
.bar_0_5: .bar_0_5:
@ -472,7 +341,7 @@ pci_mmio_map:
and eax, 0xFFFFFFF0 and eax, 0xFFFFFFF0
.allocate_block: .allocate_block:
push eax ; store MMIO physical address + keep the stack 2x4b deep push eax ; store MMIO physical address + keep the stack 2x4b deep
stdcall user_alloc, ecx stdcall user_alloc, ecx
or eax, eax or eax, eax
jnz mmio_map_over jnz mmio_map_over
@ -499,7 +368,7 @@ mmio_map_over:
;*************************************************************************** ;***************************************************************************
; Function ; Function
; pci_mmio_unmap_page ; pci_mmio_unmap_page
; ;
; Description ; Description
; unmaps the linear space previously tied to a PCI memory block ; unmaps the linear space previously tied to a PCI memory block

1
kernel/branches/Kolibri-A/trunk/data32.inc
View File

@ -67,6 +67,7 @@ keymap_alt:
; boot_pal_vga db 'Setting VGA 640x480 palette',0 ; boot_pal_vga db 'Setting VGA 640x480 palette',0
boot_failed db 'Failed to start first app',0 boot_failed db 'Failed to start first app',0
boot_mtrr db 'Setting MTRR',0 boot_mtrr db 'Setting MTRR',0
boot_uDMA_ok db 'Set user DMA OK',0
boot_pcie_ok db 'PCIe config set OK',0 boot_pcie_ok db 'PCIe config set OK',0
boot_pcie_fail db 'PCIe config XXX failed XXX',0 boot_pcie_fail db 'PCIe config XXX failed XXX',0
boot_rs7xx_fail db 'RS7xx config XXX failed XXX',0 boot_rs7xx_fail db 'RS7xx config XXX failed XXX',0

8
kernel/branches/Kolibri-A/trunk/kernel.asm
View File

@ -677,9 +677,9 @@ end if
; RESERVE SYSTEM IRQ'S JA PORT'S ; RESERVE SYSTEM IRQ'S JA PORT'S
mov esi,boot_resirqports ; mov esi,boot_resirqports
call boot_log ; call boot_log
call reserve_irqs_ports ; call reserve_irqs_ports
; SET UP OS TASK ; SET UP OS TASK
@ -828,6 +828,8 @@ end if
no_st_network: no_st_network:
call init_userDMA ; <<<<<<<<< ============== core/memory.inc ================= call init_userDMA ; <<<<<<<<< ============== core/memory.inc =================
mov esi, boot_uDMA_ok
call boot_log
; call pci_ext_config ; <<<<<<<<< bus/pci/pcie.inc ; call pci_ext_config ; <<<<<<<<< bus/pci/pcie.inc
;------------------------------------------------------------------------------- ;-------------------------------------------------------------------------------
call rs7xx_pcie_init ; <<<<<<<<< bus/ht.inc call rs7xx_pcie_init ; <<<<<<<<< bus/ht.inc