forked from KolibriOS/kolibrios
intel-2D: gen6 debug output
git-svn-id: svn://kolibrios.org@4245 a494cfbc-eb01-0410-851d-a64ba20cac60
This commit is contained in:
Sergey Semyonov (Serge)
parent
05dd88b5f5
commit
bdfa17a781
@ -1,825 +0,0 @@
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/**
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* \file drm.h
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* Header for the Direct Rendering Manager
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*
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* \author Rickard E. (Rik) Faith <faith@valinux.com>
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*
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* \par Acknowledgments:
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* Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg.
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*/
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/*
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* Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
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* Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
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* All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _DRM_H_
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#define _DRM_H_
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#include <stddef.h>
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//#include <asm/ioctl.h>
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typedef int8_t __s8;
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typedef uint8_t __u8;
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typedef int16_t __s16;
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typedef uint16_t __u16;
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typedef int32_t __s32;
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typedef uint32_t __u32;
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typedef int64_t __s64;
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typedef uint64_t __u64;
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typedef unsigned int drm_handle_t;
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#define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */
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#define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */
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#define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */
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#define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */
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#define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */
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#define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */
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#define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)
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#define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)
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#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
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typedef unsigned int drm_context_t;
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typedef unsigned int drm_drawable_t;
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typedef unsigned int drm_magic_t;
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/**
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* Cliprect.
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*
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* \warning: If you change this structure, make sure you change
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* XF86DRIClipRectRec in the server as well
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*
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* \note KW: Actually it's illegal to change either for
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* backwards-compatibility reasons.
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*/
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struct drm_clip_rect {
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unsigned short x1;
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unsigned short y1;
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unsigned short x2;
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unsigned short y2;
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};
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/**
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* Drawable information.
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*/
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struct drm_drawable_info {
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unsigned int num_rects;
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struct drm_clip_rect *rects;
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};
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/**
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* Texture region,
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*/
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struct drm_tex_region {
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unsigned char next;
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unsigned char prev;
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unsigned char in_use;
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unsigned char padding;
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unsigned int age;
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};
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/**
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* Hardware lock.
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*
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* The lock structure is a simple cache-line aligned integer. To avoid
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* processor bus contention on a multiprocessor system, there should not be any
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* other data stored in the same cache line.
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*/
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struct drm_hw_lock {
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__volatile__ unsigned int lock; /**< lock variable */
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char padding[60]; /**< Pad to cache line */
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};
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/**
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* DRM_IOCTL_VERSION ioctl argument type.
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*
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* \sa drmGetVersion().
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*/
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struct drm_version {
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int version_major; /**< Major version */
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int version_minor; /**< Minor version */
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int version_patchlevel; /**< Patch level */
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size_t name_len; /**< Length of name buffer */
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char *name; /**< Name of driver */
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size_t date_len; /**< Length of date buffer */
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char *date; /**< User-space buffer to hold date */
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size_t desc_len; /**< Length of desc buffer */
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char *desc; /**< User-space buffer to hold desc */
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};
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/**
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* DRM_IOCTL_GET_UNIQUE ioctl argument type.
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*
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* \sa drmGetBusid() and drmSetBusId().
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*/
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struct drm_unique {
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size_t unique_len; /**< Length of unique */
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char *unique; /**< Unique name for driver instantiation */
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};
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struct drm_list {
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int count; /**< Length of user-space structures */
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struct drm_version *version;
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};
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struct drm_block {
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int unused;
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};
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/**
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* DRM_IOCTL_CONTROL ioctl argument type.
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*
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* \sa drmCtlInstHandler() and drmCtlUninstHandler().
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*/
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struct drm_control {
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enum {
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DRM_ADD_COMMAND,
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DRM_RM_COMMAND,
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DRM_INST_HANDLER,
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DRM_UNINST_HANDLER
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} func;
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int irq;
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};
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/**
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* Type of memory to map.
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*/
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enum drm_map_type {
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_DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */
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_DRM_REGISTERS = 1, /**< no caching, no core dump */
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_DRM_SHM = 2, /**< shared, cached */
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_DRM_AGP = 3, /**< AGP/GART */
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_DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */
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_DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */
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_DRM_GEM = 6, /**< GEM object */
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};
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/**
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* Memory mapping flags.
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*/
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enum drm_map_flags {
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_DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */
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_DRM_READ_ONLY = 0x02,
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_DRM_LOCKED = 0x04, /**< shared, cached, locked */
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_DRM_KERNEL = 0x08, /**< kernel requires access */
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_DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */
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_DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */
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_DRM_REMOVABLE = 0x40, /**< Removable mapping */
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_DRM_DRIVER = 0x80 /**< Managed by driver */
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};
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struct drm_ctx_priv_map {
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unsigned int ctx_id; /**< Context requesting private mapping */
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void *handle; /**< Handle of map */
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};
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/**
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* DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
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* argument type.
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*
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* \sa drmAddMap().
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*/
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struct drm_map {
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unsigned long offset; /**< Requested physical address (0 for SAREA)*/
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unsigned long size; /**< Requested physical size (bytes) */
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enum drm_map_type type; /**< Type of memory to map */
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enum drm_map_flags flags; /**< Flags */
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void *handle; /**< User-space: "Handle" to pass to mmap() */
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/**< Kernel-space: kernel-virtual address */
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int mtrr; /**< MTRR slot used */
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/* Private data */
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};
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/**
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* DRM_IOCTL_GET_CLIENT ioctl argument type.
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*/
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struct drm_client {
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int idx; /**< Which client desired? */
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int auth; /**< Is client authenticated? */
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unsigned long pid; /**< Process ID */
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unsigned long uid; /**< User ID */
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unsigned long magic; /**< Magic */
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unsigned long iocs; /**< Ioctl count */
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};
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enum drm_stat_type {
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_DRM_STAT_LOCK,
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_DRM_STAT_OPENS,
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_DRM_STAT_CLOSES,
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_DRM_STAT_IOCTLS,
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_DRM_STAT_LOCKS,
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_DRM_STAT_UNLOCKS,
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_DRM_STAT_VALUE, /**< Generic value */
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_DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */
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_DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */
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_DRM_STAT_IRQ, /**< IRQ */
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_DRM_STAT_PRIMARY, /**< Primary DMA bytes */
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_DRM_STAT_SECONDARY, /**< Secondary DMA bytes */
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_DRM_STAT_DMA, /**< DMA */
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_DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */
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_DRM_STAT_MISSED /**< Missed DMA opportunity */
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/* Add to the *END* of the list */
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};
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/**
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* DRM_IOCTL_GET_STATS ioctl argument type.
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*/
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struct drm_stats {
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unsigned long count;
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struct {
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unsigned long value;
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enum drm_stat_type type;
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} data[15];
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};
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/**
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* Hardware locking flags.
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*/
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enum drm_lock_flags {
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_DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */
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_DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */
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_DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */
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_DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */
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/* These *HALT* flags aren't supported yet
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-- they will be used to support the
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full-screen DGA-like mode. */
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_DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */
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_DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */
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};
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/**
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* DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
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*
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* \sa drmGetLock() and drmUnlock().
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*/
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struct drm_lock {
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int context;
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enum drm_lock_flags flags;
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};
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/**
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* DMA flags
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*
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* \warning
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* These values \e must match xf86drm.h.
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*
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* \sa drm_dma.
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*/
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enum drm_dma_flags {
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/* Flags for DMA buffer dispatch */
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_DRM_DMA_BLOCK = 0x01, /**<
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* Block until buffer dispatched.
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*
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* \note The buffer may not yet have
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* been processed by the hardware --
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* getting a hardware lock with the
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* hardware quiescent will ensure
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* that the buffer has been
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* processed.
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*/
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_DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */
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_DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */
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/* Flags for DMA buffer request */
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_DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */
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_DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */
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_DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */
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};
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/**
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* DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
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*
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* \sa drmAddBufs().
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*/
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struct drm_buf_desc {
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int count; /**< Number of buffers of this size */
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int size; /**< Size in bytes */
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int low_mark; /**< Low water mark */
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int high_mark; /**< High water mark */
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enum {
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_DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */
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_DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */
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_DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */
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_DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */
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_DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */
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} flags;
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unsigned long agp_start; /**<
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* Start address of where the AGP buffers are
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* in the AGP aperture
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*/
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};
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/**
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* DRM_IOCTL_INFO_BUFS ioctl argument type.
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*/
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struct drm_buf_info {
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int count; /**< Entries in list */
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struct drm_buf_desc *list;
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};
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/**
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* DRM_IOCTL_FREE_BUFS ioctl argument type.
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*/
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struct drm_buf_free {
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int count;
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int *list;
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};
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/**
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* Buffer information
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*
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* \sa drm_buf_map.
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*/
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struct drm_buf_pub {
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int idx; /**< Index into the master buffer list */
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int total; /**< Buffer size */
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int used; /**< Amount of buffer in use (for DMA) */
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void *address; /**< Address of buffer */
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};
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/**
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* DRM_IOCTL_MAP_BUFS ioctl argument type.
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*/
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struct drm_buf_map {
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int count; /**< Length of the buffer list */
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#ifdef __cplusplus
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void *virt;
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#else
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void *virtual; /**< Mmap'd area in user-virtual */
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#endif
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struct drm_buf_pub *list; /**< Buffer information */
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};
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/**
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* DRM_IOCTL_DMA ioctl argument type.
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*
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* Indices here refer to the offset into the buffer list in drm_buf_get.
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*
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* \sa drmDMA().
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*/
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struct drm_dma {
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int context; /**< Context handle */
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int send_count; /**< Number of buffers to send */
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int *send_indices; /**< List of handles to buffers */
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int *send_sizes; /**< Lengths of data to send */
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enum drm_dma_flags flags; /**< Flags */
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int request_count; /**< Number of buffers requested */
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int request_size; /**< Desired size for buffers */
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int *request_indices; /**< Buffer information */
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int *request_sizes;
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int granted_count; /**< Number of buffers granted */
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};
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enum drm_ctx_flags {
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_DRM_CONTEXT_PRESERVED = 0x01,
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_DRM_CONTEXT_2DONLY = 0x02
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};
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/**
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* DRM_IOCTL_ADD_CTX ioctl argument type.
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*
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* \sa drmCreateContext() and drmDestroyContext().
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*/
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struct drm_ctx {
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drm_context_t handle;
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enum drm_ctx_flags flags;
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};
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/**
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* DRM_IOCTL_RES_CTX ioctl argument type.
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*/
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struct drm_ctx_res {
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int count;
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struct drm_ctx *contexts;
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};
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/**
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* DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
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*/
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struct drm_draw {
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drm_drawable_t handle;
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};
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/**
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* DRM_IOCTL_UPDATE_DRAW ioctl argument type.
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*/
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typedef enum {
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DRM_DRAWABLE_CLIPRECTS,
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} drm_drawable_info_type_t;
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struct drm_update_draw {
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drm_drawable_t handle;
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unsigned int type;
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unsigned int num;
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unsigned long long data;
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};
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/**
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* DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
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*/
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struct drm_auth {
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drm_magic_t magic;
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};
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/**
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* DRM_IOCTL_IRQ_BUSID ioctl argument type.
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*
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* \sa drmGetInterruptFromBusID().
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*/
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struct drm_irq_busid {
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int irq; /**< IRQ number */
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int busnum; /**< bus number */
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int devnum; /**< device number */
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int funcnum; /**< function number */
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};
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enum drm_vblank_seq_type {
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_DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */
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_DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */
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_DRM_VBLANK_EVENT = 0x4000000, /**< Send event instead of blocking */
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_DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */
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_DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */
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_DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */
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_DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking, unsupported */
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};
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#define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE)
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#define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | \
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_DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS)
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struct drm_wait_vblank_request {
|
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enum drm_vblank_seq_type type;
|
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unsigned int sequence;
|
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unsigned long signal;
|
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};
|
||||
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struct drm_wait_vblank_reply {
|
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enum drm_vblank_seq_type type;
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unsigned int sequence;
|
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long tval_sec;
|
||||
long tval_usec;
|
||||
};
|
||||
|
||||
/**
|
||||
* DRM_IOCTL_WAIT_VBLANK ioctl argument type.
|
||||
*
|
||||
* \sa drmWaitVBlank().
|
||||
*/
|
||||
union drm_wait_vblank {
|
||||
struct drm_wait_vblank_request request;
|
||||
struct drm_wait_vblank_reply reply;
|
||||
};
|
||||
|
||||
#define _DRM_PRE_MODESET 1
|
||||
#define _DRM_POST_MODESET 2
|
||||
|
||||
/**
|
||||
* DRM_IOCTL_MODESET_CTL ioctl argument type
|
||||
*
|
||||
* \sa drmModesetCtl().
|
||||
*/
|
||||
struct drm_modeset_ctl {
|
||||
__u32 crtc;
|
||||
__u32 cmd;
|
||||
};
|
||||
|
||||
/**
|
||||
* DRM_IOCTL_AGP_ENABLE ioctl argument type.
|
||||
*
|
||||
* \sa drmAgpEnable().
|
||||
*/
|
||||
struct drm_agp_mode {
|
||||
unsigned long mode; /**< AGP mode */
|
||||
};
|
||||
|
||||
/**
|
||||
* DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
|
||||
*
|
||||
* \sa drmAgpAlloc() and drmAgpFree().
|
||||
*/
|
||||
struct drm_agp_buffer {
|
||||
unsigned long size; /**< In bytes -- will round to page boundary */
|
||||
unsigned long handle; /**< Used for binding / unbinding */
|
||||
unsigned long type; /**< Type of memory to allocate */
|
||||
unsigned long physical; /**< Physical used by i810 */
|
||||
};
|
||||
|
||||
/**
|
||||
* DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
|
||||
*
|
||||
* \sa drmAgpBind() and drmAgpUnbind().
|
||||
*/
|
||||
struct drm_agp_binding {
|
||||
unsigned long handle; /**< From drm_agp_buffer */
|
||||
unsigned long offset; /**< In bytes -- will round to page boundary */
|
||||
};
|
||||
|
||||
/**
|
||||
* DRM_IOCTL_AGP_INFO ioctl argument type.
|
||||
*
|
||||
* \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),
|
||||
* drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),
|
||||
* drmAgpVendorId() and drmAgpDeviceId().
|
||||
*/
|
||||
struct drm_agp_info {
|
||||
int agp_version_major;
|
||||
int agp_version_minor;
|
||||
unsigned long mode;
|
||||
unsigned long aperture_base; /* physical address */
|
||||
unsigned long aperture_size; /* bytes */
|
||||
unsigned long memory_allowed; /* bytes */
|
||||
unsigned long memory_used;
|
||||
|
||||
/* PCI information */
|
||||
unsigned short id_vendor;
|
||||
unsigned short id_device;
|
||||
};
|
||||
|
||||
/**
|
||||
* DRM_IOCTL_SG_ALLOC ioctl argument type.
|
||||
*/
|
||||
struct drm_scatter_gather {
|
||||
unsigned long size; /**< In bytes -- will round to page boundary */
|
||||
unsigned long handle; /**< Used for mapping / unmapping */
|
||||
};
|
||||
|
||||
/**
|
||||
* DRM_IOCTL_SET_VERSION ioctl argument type.
|
||||
*/
|
||||
struct drm_set_version {
|
||||
int drm_di_major;
|
||||
int drm_di_minor;
|
||||
int drm_dd_major;
|
||||
int drm_dd_minor;
|
||||
};
|
||||
|
||||
/** DRM_IOCTL_GEM_CLOSE ioctl argument type */
|
||||
struct drm_gem_close {
|
||||
/** Handle of the object to be closed. */
|
||||
__u32 handle;
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
/** DRM_IOCTL_GEM_FLINK ioctl argument type */
|
||||
struct drm_gem_flink {
|
||||
/** Handle for the object being named */
|
||||
__u32 handle;
|
||||
|
||||
/** Returned global name */
|
||||
__u32 name;
|
||||
};
|
||||
|
||||
/** DRM_IOCTL_GEM_OPEN ioctl argument type */
|
||||
struct drm_gem_open {
|
||||
/** Name of object being opened */
|
||||
__u32 name;
|
||||
|
||||
/** Returned handle for the object */
|
||||
__u32 handle;
|
||||
|
||||
/** Returned size of the object */
|
||||
__u64 size;
|
||||
};
|
||||
|
||||
/** DRM_IOCTL_GET_CAP ioctl argument type */
|
||||
struct drm_get_cap {
|
||||
__u64 capability;
|
||||
__u64 value;
|
||||
};
|
||||
|
||||
#define DRM_CLOEXEC O_CLOEXEC
|
||||
struct drm_prime_handle {
|
||||
__u32 handle;
|
||||
|
||||
/** Flags.. only applicable for handle->fd */
|
||||
__u32 flags;
|
||||
|
||||
/** Returned dmabuf file descriptor */
|
||||
__s32 fd;
|
||||
};
|
||||
|
||||
//#include "drm_mode.h"
|
||||
|
||||
#if 0
|
||||
|
||||
#define DRM_IOCTL_BASE 'd'
|
||||
#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
|
||||
#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)
|
||||
#define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)
|
||||
#define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)
|
||||
|
||||
#define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version)
|
||||
#define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique)
|
||||
#define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth)
|
||||
#define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid)
|
||||
#define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map)
|
||||
#define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client)
|
||||
#define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats)
|
||||
#define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version)
|
||||
#define DRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl)
|
||||
#define DRM_IOCTL_GEM_CLOSE DRM_IOW (0x09, struct drm_gem_close)
|
||||
#define DRM_IOCTL_GEM_FLINK DRM_IOWR(0x0a, struct drm_gem_flink)
|
||||
#define DRM_IOCTL_GEM_OPEN DRM_IOWR(0x0b, struct drm_gem_open)
|
||||
#define DRM_IOCTL_GET_CAP DRM_IOWR(0x0c, struct drm_get_cap)
|
||||
|
||||
#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique)
|
||||
#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth)
|
||||
#define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block)
|
||||
#define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block)
|
||||
#define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control)
|
||||
#define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map)
|
||||
#define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc)
|
||||
#define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc)
|
||||
#define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info)
|
||||
#define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map)
|
||||
#define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free)
|
||||
|
||||
#define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map)
|
||||
|
||||
#define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map)
|
||||
#define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map)
|
||||
|
||||
#define DRM_IOCTL_SET_MASTER DRM_IO(0x1e)
|
||||
#define DRM_IOCTL_DROP_MASTER DRM_IO(0x1f)
|
||||
|
||||
#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx)
|
||||
#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx)
|
||||
#define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx)
|
||||
#define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx)
|
||||
#define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx)
|
||||
#define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx)
|
||||
#define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res)
|
||||
#define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw)
|
||||
#define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw)
|
||||
#define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma)
|
||||
#define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock)
|
||||
#define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock)
|
||||
#define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock)
|
||||
|
||||
#define DRM_IOCTL_PRIME_HANDLE_TO_FD DRM_IOWR(0x2d, struct drm_prime_handle)
|
||||
#define DRM_IOCTL_PRIME_FD_TO_HANDLE DRM_IOWR(0x2e, struct drm_prime_handle)
|
||||
|
||||
#define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
|
||||
#define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)
|
||||
#define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode)
|
||||
#define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info)
|
||||
#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer)
|
||||
#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer)
|
||||
#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding)
|
||||
#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding)
|
||||
|
||||
#define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather)
|
||||
#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather)
|
||||
|
||||
#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank)
|
||||
|
||||
#define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw)
|
||||
|
||||
#define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res)
|
||||
#define DRM_IOCTL_MODE_GETCRTC DRM_IOWR(0xA1, struct drm_mode_crtc)
|
||||
#define DRM_IOCTL_MODE_SETCRTC DRM_IOWR(0xA2, struct drm_mode_crtc)
|
||||
#define DRM_IOCTL_MODE_CURSOR DRM_IOWR(0xA3, struct drm_mode_cursor)
|
||||
#define DRM_IOCTL_MODE_GETGAMMA DRM_IOWR(0xA4, struct drm_mode_crtc_lut)
|
||||
#define DRM_IOCTL_MODE_SETGAMMA DRM_IOWR(0xA5, struct drm_mode_crtc_lut)
|
||||
#define DRM_IOCTL_MODE_GETENCODER DRM_IOWR(0xA6, struct drm_mode_get_encoder)
|
||||
#define DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA7, struct drm_mode_get_connector)
|
||||
#define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA8, struct drm_mode_mode_cmd)
|
||||
#define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd)
|
||||
|
||||
#define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAA, struct drm_mode_get_property)
|
||||
#define DRM_IOCTL_MODE_SETPROPERTY DRM_IOWR(0xAB, struct drm_mode_connector_set_property)
|
||||
#define DRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xAC, struct drm_mode_get_blob)
|
||||
#define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xAD, struct drm_mode_fb_cmd)
|
||||
#define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xAE, struct drm_mode_fb_cmd)
|
||||
#define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, unsigned int)
|
||||
#define DRM_IOCTL_MODE_PAGE_FLIP DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip)
|
||||
#define DRM_IOCTL_MODE_DIRTYFB DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd)
|
||||
|
||||
#define DRM_IOCTL_MODE_CREATE_DUMB DRM_IOWR(0xB2, struct drm_mode_create_dumb)
|
||||
#define DRM_IOCTL_MODE_MAP_DUMB DRM_IOWR(0xB3, struct drm_mode_map_dumb)
|
||||
#define DRM_IOCTL_MODE_DESTROY_DUMB DRM_IOWR(0xB4, struct drm_mode_destroy_dumb)
|
||||
#define DRM_IOCTL_MODE_GETPLANERESOURCES DRM_IOWR(0xB5, struct drm_mode_get_plane_res)
|
||||
#define DRM_IOCTL_MODE_GETPLANE DRM_IOWR(0xB6, struct drm_mode_get_plane)
|
||||
#define DRM_IOCTL_MODE_SETPLANE DRM_IOWR(0xB7, struct drm_mode_set_plane)
|
||||
#define DRM_IOCTL_MODE_ADDFB2 DRM_IOWR(0xB8, struct drm_mode_fb_cmd2)
|
||||
#define DRM_IOCTL_MODE_OBJ_GETPROPERTIES DRM_IOWR(0xB9, struct drm_mode_obj_get_properties)
|
||||
#define DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct drm_mode_obj_set_property)
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Device specific ioctls should only be in their respective headers
|
||||
* The device specific ioctl range is from 0x40 to 0x99.
|
||||
* Generic IOCTLS restart at 0xA0.
|
||||
*
|
||||
* \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
|
||||
* drmCommandReadWrite().
|
||||
*/
|
||||
#define DRM_COMMAND_BASE 0x40
|
||||
#define DRM_COMMAND_END 0xA0
|
||||
|
||||
/**
|
||||
* Header for events written back to userspace on the drm fd. The
|
||||
* type defines the type of event, the length specifies the total
|
||||
* length of the event (including the header), and user_data is
|
||||
* typically a 64 bit value passed with the ioctl that triggered the
|
||||
* event. A read on the drm fd will always only return complete
|
||||
* events, that is, if for example the read buffer is 100 bytes, and
|
||||
* there are two 64 byte events pending, only one will be returned.
|
||||
*
|
||||
* Event types 0 - 0x7fffffff are generic drm events, 0x80000000 and
|
||||
* up are chipset specific.
|
||||
*/
|
||||
struct drm_event {
|
||||
__u32 type;
|
||||
__u32 length;
|
||||
};
|
||||
|
||||
#define DRM_EVENT_VBLANK 0x01
|
||||
#define DRM_EVENT_FLIP_COMPLETE 0x02
|
||||
|
||||
struct drm_event_vblank {
|
||||
struct drm_event base;
|
||||
__u64 user_data;
|
||||
__u32 tv_sec;
|
||||
__u32 tv_usec;
|
||||
__u32 sequence;
|
||||
__u32 reserved;
|
||||
};
|
||||
|
||||
#define DRM_CAP_DUMB_BUFFER 0x1
|
||||
#define DRM_CAP_VBLANK_HIGH_CRTC 0x2
|
||||
#define DRM_CAP_DUMB_PREFERRED_DEPTH 0x3
|
||||
#define DRM_CAP_DUMB_PREFER_SHADOW 0x4
|
||||
#define DRM_CAP_PRIME 0x5
|
||||
|
||||
#define DRM_PRIME_CAP_IMPORT 0x1
|
||||
#define DRM_PRIME_CAP_EXPORT 0x2
|
||||
|
||||
/* typedef area */
|
||||
typedef struct drm_clip_rect drm_clip_rect_t;
|
||||
typedef struct drm_drawable_info drm_drawable_info_t;
|
||||
typedef struct drm_tex_region drm_tex_region_t;
|
||||
typedef struct drm_hw_lock drm_hw_lock_t;
|
||||
typedef struct drm_version drm_version_t;
|
||||
typedef struct drm_unique drm_unique_t;
|
||||
typedef struct drm_list drm_list_t;
|
||||
typedef struct drm_block drm_block_t;
|
||||
typedef struct drm_control drm_control_t;
|
||||
typedef enum drm_map_type drm_map_type_t;
|
||||
typedef enum drm_map_flags drm_map_flags_t;
|
||||
typedef struct drm_ctx_priv_map drm_ctx_priv_map_t;
|
||||
typedef struct drm_map drm_map_t;
|
||||
typedef struct drm_client drm_client_t;
|
||||
typedef enum drm_stat_type drm_stat_type_t;
|
||||
typedef struct drm_stats drm_stats_t;
|
||||
typedef enum drm_lock_flags drm_lock_flags_t;
|
||||
typedef struct drm_lock drm_lock_t;
|
||||
typedef enum drm_dma_flags drm_dma_flags_t;
|
||||
typedef struct drm_buf_desc drm_buf_desc_t;
|
||||
typedef struct drm_buf_info drm_buf_info_t;
|
||||
typedef struct drm_buf_free drm_buf_free_t;
|
||||
typedef struct drm_buf_pub drm_buf_pub_t;
|
||||
typedef struct drm_buf_map drm_buf_map_t;
|
||||
typedef struct drm_dma drm_dma_t;
|
||||
typedef union drm_wait_vblank drm_wait_vblank_t;
|
||||
typedef struct drm_agp_mode drm_agp_mode_t;
|
||||
typedef enum drm_ctx_flags drm_ctx_flags_t;
|
||||
typedef struct drm_ctx drm_ctx_t;
|
||||
typedef struct drm_ctx_res drm_ctx_res_t;
|
||||
typedef struct drm_draw drm_draw_t;
|
||||
typedef struct drm_update_draw drm_update_draw_t;
|
||||
typedef struct drm_auth drm_auth_t;
|
||||
typedef struct drm_irq_busid drm_irq_busid_t;
|
||||
typedef enum drm_vblank_seq_type drm_vblank_seq_type_t;
|
||||
|
||||
typedef struct drm_agp_buffer drm_agp_buffer_t;
|
||||
typedef struct drm_agp_binding drm_agp_binding_t;
|
||||
typedef struct drm_agp_info drm_agp_info_t;
|
||||
typedef struct drm_scatter_gather drm_scatter_gather_t;
|
||||
typedef struct drm_set_version drm_set_version_t;
|
||||
|
||||
#endif
|
||||
@ -1912,11 +1912,11 @@ gen3_blit_tex(struct sna *sna,
|
||||
tmp->floats_per_vertex += tmp->src.is_affine ? 2 : 4;
|
||||
if (!is_constant_ps(tmp->mask.u.gen3.type))
|
||||
tmp->floats_per_vertex += tmp->mask.is_affine ? 2 : 4;
|
||||
DBG(("%s: floats_per_vertex = 2 + %d + %d = %d [specialised emitter? %d]\n", __FUNCTION__,
|
||||
!is_constant_ps(tmp->src.u.gen3.type) ? tmp->src.is_affine ? 2 : 4 : 0,
|
||||
!is_constant_ps(tmp->mask.u.gen3.type) ? tmp->mask.is_affine ? 2 : 4 : 0,
|
||||
tmp->floats_per_vertex,
|
||||
tmp->prim_emit != gen3_emit_composite_primitive));
|
||||
// DBG(("%s: floats_per_vertex = 2 + %d + %d = %d [specialised emitter? %d]\n", __FUNCTION__,
|
||||
// !is_constant_ps(tmp->src.u.gen3.type) ? tmp->src.is_affine ? 2 : 4 : 0,
|
||||
// !is_constant_ps(tmp->mask.u.gen3.type) ? tmp->mask.is_affine ? 2 : 4 : 0,
|
||||
// tmp->floats_per_vertex,
|
||||
// tmp->prim_emit != gen3_emit_composite_primitive));
|
||||
tmp->floats_per_rect = 3 * tmp->floats_per_vertex;
|
||||
|
||||
tmp->blt = gen3_render_composite_blt;
|
||||
|
||||
@ -1,954 +0,0 @@
|
||||
/*
|
||||
* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the
|
||||
* "Software"), to deal in the Software without restriction, including
|
||||
* without limitation the rights to use, copy, modify, merge, publish,
|
||||
* distribute, sub license, and/or sell copies of the Software, and to
|
||||
* permit persons to whom the Software is furnished to do so, subject to
|
||||
* the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the
|
||||
* next paragraph) shall be included in all copies or substantial portions
|
||||
* of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
||||
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
|
||||
* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
|
||||
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _I915_DRM_H_
|
||||
#define _I915_DRM_H_
|
||||
|
||||
#include "drm.h"
|
||||
|
||||
/* Please note that modifications to all structs defined here are
|
||||
* subject to backwards-compatibility constraints.
|
||||
*/
|
||||
|
||||
|
||||
/* Each region is a minimum of 16k, and there are at most 255 of them.
|
||||
*/
|
||||
#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
|
||||
* of chars for next/prev indices */
|
||||
#define I915_LOG_MIN_TEX_REGION_SIZE 14
|
||||
|
||||
typedef struct _drm_i915_init {
|
||||
enum {
|
||||
I915_INIT_DMA = 0x01,
|
||||
I915_CLEANUP_DMA = 0x02,
|
||||
I915_RESUME_DMA = 0x03
|
||||
} func;
|
||||
unsigned int mmio_offset;
|
||||
int sarea_priv_offset;
|
||||
unsigned int ring_start;
|
||||
unsigned int ring_end;
|
||||
unsigned int ring_size;
|
||||
unsigned int front_offset;
|
||||
unsigned int back_offset;
|
||||
unsigned int depth_offset;
|
||||
unsigned int w;
|
||||
unsigned int h;
|
||||
unsigned int pitch;
|
||||
unsigned int pitch_bits;
|
||||
unsigned int back_pitch;
|
||||
unsigned int depth_pitch;
|
||||
unsigned int cpp;
|
||||
unsigned int chipset;
|
||||
} drm_i915_init_t;
|
||||
|
||||
typedef struct _drm_i915_sarea {
|
||||
struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
|
||||
int last_upload; /* last time texture was uploaded */
|
||||
int last_enqueue; /* last time a buffer was enqueued */
|
||||
int last_dispatch; /* age of the most recently dispatched buffer */
|
||||
int ctxOwner; /* last context to upload state */
|
||||
int texAge;
|
||||
int pf_enabled; /* is pageflipping allowed? */
|
||||
int pf_active;
|
||||
int pf_current_page; /* which buffer is being displayed? */
|
||||
int perf_boxes; /* performance boxes to be displayed */
|
||||
int width, height; /* screen size in pixels */
|
||||
|
||||
drm_handle_t front_handle;
|
||||
int front_offset;
|
||||
int front_size;
|
||||
|
||||
drm_handle_t back_handle;
|
||||
int back_offset;
|
||||
int back_size;
|
||||
|
||||
drm_handle_t depth_handle;
|
||||
int depth_offset;
|
||||
int depth_size;
|
||||
|
||||
drm_handle_t tex_handle;
|
||||
int tex_offset;
|
||||
int tex_size;
|
||||
int log_tex_granularity;
|
||||
int pitch;
|
||||
int rotation; /* 0, 90, 180 or 270 */
|
||||
int rotated_offset;
|
||||
int rotated_size;
|
||||
int rotated_pitch;
|
||||
int virtualX, virtualY;
|
||||
|
||||
unsigned int front_tiled;
|
||||
unsigned int back_tiled;
|
||||
unsigned int depth_tiled;
|
||||
unsigned int rotated_tiled;
|
||||
unsigned int rotated2_tiled;
|
||||
|
||||
int pipeA_x;
|
||||
int pipeA_y;
|
||||
int pipeA_w;
|
||||
int pipeA_h;
|
||||
int pipeB_x;
|
||||
int pipeB_y;
|
||||
int pipeB_w;
|
||||
int pipeB_h;
|
||||
|
||||
/* fill out some space for old userspace triple buffer */
|
||||
drm_handle_t unused_handle;
|
||||
__u32 unused1, unused2, unused3;
|
||||
|
||||
/* buffer object handles for static buffers. May change
|
||||
* over the lifetime of the client.
|
||||
*/
|
||||
__u32 front_bo_handle;
|
||||
__u32 back_bo_handle;
|
||||
__u32 unused_bo_handle;
|
||||
__u32 depth_bo_handle;
|
||||
|
||||
} drm_i915_sarea_t;
|
||||
|
||||
/* due to userspace building against these headers we need some compat here */
|
||||
#define planeA_x pipeA_x
|
||||
#define planeA_y pipeA_y
|
||||
#define planeA_w pipeA_w
|
||||
#define planeA_h pipeA_h
|
||||
#define planeB_x pipeB_x
|
||||
#define planeB_y pipeB_y
|
||||
#define planeB_w pipeB_w
|
||||
#define planeB_h pipeB_h
|
||||
|
||||
/* Flags for perf_boxes
|
||||
*/
|
||||
#define I915_BOX_RING_EMPTY 0x1
|
||||
#define I915_BOX_FLIP 0x2
|
||||
#define I915_BOX_WAIT 0x4
|
||||
#define I915_BOX_TEXTURE_LOAD 0x8
|
||||
#define I915_BOX_LOST_CONTEXT 0x10
|
||||
|
||||
/* I915 specific ioctls
|
||||
* The device specific ioctl range is 0x40 to 0x79.
|
||||
*/
|
||||
#define DRM_I915_INIT 0x00
|
||||
#define DRM_I915_FLUSH 0x01
|
||||
#define DRM_I915_FLIP 0x02
|
||||
#define DRM_I915_BATCHBUFFER 0x03
|
||||
#define DRM_I915_IRQ_EMIT 0x04
|
||||
#define DRM_I915_IRQ_WAIT 0x05
|
||||
#define DRM_I915_GETPARAM 0x06
|
||||
#define DRM_I915_SETPARAM 0x07
|
||||
#define DRM_I915_ALLOC 0x08
|
||||
#define DRM_I915_FREE 0x09
|
||||
#define DRM_I915_INIT_HEAP 0x0a
|
||||
#define DRM_I915_CMDBUFFER 0x0b
|
||||
#define DRM_I915_DESTROY_HEAP 0x0c
|
||||
#define DRM_I915_SET_VBLANK_PIPE 0x0d
|
||||
#define DRM_I915_GET_VBLANK_PIPE 0x0e
|
||||
#define DRM_I915_VBLANK_SWAP 0x0f
|
||||
#define DRM_I915_HWS_ADDR 0x11
|
||||
#define DRM_I915_GEM_INIT 0x13
|
||||
#define DRM_I915_GEM_EXECBUFFER 0x14
|
||||
#define DRM_I915_GEM_PIN 0x15
|
||||
#define DRM_I915_GEM_UNPIN 0x16
|
||||
#define DRM_I915_GEM_BUSY 0x17
|
||||
#define DRM_I915_GEM_THROTTLE 0x18
|
||||
#define DRM_I915_GEM_ENTERVT 0x19
|
||||
#define DRM_I915_GEM_LEAVEVT 0x1a
|
||||
#define DRM_I915_GEM_CREATE 0x1b
|
||||
#define DRM_I915_GEM_PREAD 0x1c
|
||||
#define DRM_I915_GEM_PWRITE 0x1d
|
||||
#define DRM_I915_GEM_MMAP 0x1e
|
||||
#define DRM_I915_GEM_SET_DOMAIN 0x1f
|
||||
#define DRM_I915_GEM_SW_FINISH 0x20
|
||||
#define DRM_I915_GEM_SET_TILING 0x21
|
||||
#define DRM_I915_GEM_GET_TILING 0x22
|
||||
#define DRM_I915_GEM_GET_APERTURE 0x23
|
||||
#define DRM_I915_GEM_MMAP_GTT 0x24
|
||||
#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
|
||||
#define DRM_I915_GEM_MADVISE 0x26
|
||||
#define DRM_I915_OVERLAY_PUT_IMAGE 0x27
|
||||
#define DRM_I915_OVERLAY_ATTRS 0x28
|
||||
#define DRM_I915_GEM_EXECBUFFER2 0x29
|
||||
#define DRM_I915_GET_SPRITE_COLORKEY 0x2a
|
||||
#define DRM_I915_SET_SPRITE_COLORKEY 0x2b
|
||||
#define DRM_I915_GEM_WAIT 0x2c
|
||||
#define DRM_I915_GEM_CONTEXT_CREATE 0x2d
|
||||
#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e
|
||||
#define DRM_I915_GEM_SET_CACHEING 0x2f
|
||||
#define DRM_I915_GEM_GET_CACHEING 0x30
|
||||
#define DRM_I915_REG_READ 0x31
|
||||
|
||||
#define DRM_IOCTL_I915_INIT
|
||||
#define DRM_IOCTL_I915_FLUSH
|
||||
#define DRM_IOCTL_I915_FLIP
|
||||
#define DRM_IOCTL_I915_BATCHBUFFER
|
||||
#define DRM_IOCTL_I915_IRQ_EMIT
|
||||
#define DRM_IOCTL_I915_IRQ_WAIT
|
||||
#define DRM_IOCTL_I915_GETPARAM SRV_GET_PARAM
|
||||
#define DRM_IOCTL_I915_SETPARAM
|
||||
#define DRM_IOCTL_I915_ALLOC
|
||||
#define DRM_IOCTL_I915_FREE
|
||||
#define DRM_IOCTL_I915_INIT_HEAP
|
||||
#define DRM_IOCTL_I915_CMDBUFFER
|
||||
#define DRM_IOCTL_I915_DESTROY_HEAP
|
||||
#define DRM_IOCTL_I915_SET_VBLANK_PIPE
|
||||
#define DRM_IOCTL_I915_GET_VBLANK_PIPE
|
||||
#define DRM_IOCTL_I915_VBLANK_SWAP
|
||||
#define DRM_IOCTL_I915_HWS_ADDR
|
||||
#define DRM_IOCTL_I915_GEM_INIT
|
||||
#define DRM_IOCTL_I915_GEM_EXECBUFFER
|
||||
#define DRM_IOCTL_I915_GEM_EXECBUFFER2 SRV_I915_GEM_EXECBUFFER2
|
||||
#define DRM_IOCTL_I915_GEM_PIN SRV_I915_GEM_PIN
|
||||
#define DRM_IOCTL_I915_GEM_UNPIN
|
||||
#define DRM_IOCTL_I915_GEM_BUSY SRV_I915_GEM_BUSY
|
||||
#define DRM_IOCTL_I915_GEM_SET_CACHEING SRV_I915_GEM_SET_CACHEING
|
||||
#define DRM_IOCTL_I915_GEM_GET_CACHEING
|
||||
#define DRM_IOCTL_I915_GEM_THROTTLE SRV_I915_GEM_THROTTLE
|
||||
#define DRM_IOCTL_I915_GEM_ENTERVT
|
||||
#define DRM_IOCTL_I915_GEM_LEAVEVT
|
||||
#define DRM_IOCTL_I915_GEM_CREATE SRV_I915_GEM_CREATE
|
||||
#define DRM_IOCTL_I915_GEM_PREAD
|
||||
#define DRM_IOCTL_I915_GEM_PWRITE SRV_I915_GEM_PWRITE
|
||||
#define DRM_IOCTL_I915_GEM_MMAP SRV_I915_GEM_MMAP
|
||||
#define DRM_IOCTL_I915_GEM_MMAP_GTT SRV_I915_GEM_MMAP_GTT
|
||||
#define DRM_IOCTL_I915_GEM_SET_DOMAIN SRV_I915_GEM_SET_DOMAIN
|
||||
#define DRM_IOCTL_I915_GEM_SW_FINISH
|
||||
#define DRM_IOCTL_I915_GEM_SET_TILING
|
||||
#define DRM_IOCTL_I915_GEM_GET_TILING
|
||||
#define DRM_IOCTL_I915_GEM_GET_APERTURE SRV_I915_GEM_GET_APERTURE
|
||||
#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID
|
||||
#define DRM_IOCTL_I915_GEM_MADVISE
|
||||
#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE
|
||||
#define DRM_IOCTL_I915_OVERLAY_ATTRS
|
||||
#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY
|
||||
#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY
|
||||
#define DRM_IOCTL_I915_GEM_WAIT
|
||||
#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE
|
||||
#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY
|
||||
#define DRM_IOCTL_I915_REG_READ
|
||||
|
||||
/* Allow drivers to submit batchbuffers directly to hardware, relying
|
||||
* on the security mechanisms provided by hardware.
|
||||
*/
|
||||
typedef struct drm_i915_batchbuffer {
|
||||
int start; /* agp offset */
|
||||
int used; /* nr bytes in use */
|
||||
int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
|
||||
int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
|
||||
int num_cliprects; /* mulitpass with multiple cliprects? */
|
||||
struct drm_clip_rect *cliprects; /* pointer to userspace cliprects */
|
||||
} drm_i915_batchbuffer_t;
|
||||
|
||||
/* As above, but pass a pointer to userspace buffer which can be
|
||||
* validated by the kernel prior to sending to hardware.
|
||||
*/
|
||||
typedef struct _drm_i915_cmdbuffer {
|
||||
char *buf; /* pointer to userspace command buffer */
|
||||
int sz; /* nr bytes in buf */
|
||||
int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
|
||||
int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
|
||||
int num_cliprects; /* mulitpass with multiple cliprects? */
|
||||
struct drm_clip_rect *cliprects; /* pointer to userspace cliprects */
|
||||
} drm_i915_cmdbuffer_t;
|
||||
|
||||
/* Userspace can request & wait on irq's:
|
||||
*/
|
||||
typedef struct drm_i915_irq_emit {
|
||||
int *irq_seq;
|
||||
} drm_i915_irq_emit_t;
|
||||
|
||||
typedef struct drm_i915_irq_wait {
|
||||
int irq_seq;
|
||||
} drm_i915_irq_wait_t;
|
||||
|
||||
/* Ioctl to query kernel params:
|
||||
*/
|
||||
#define I915_PARAM_IRQ_ACTIVE 1
|
||||
#define I915_PARAM_ALLOW_BATCHBUFFER 2
|
||||
#define I915_PARAM_LAST_DISPATCH 3
|
||||
#define I915_PARAM_CHIPSET_ID 4
|
||||
#define I915_PARAM_HAS_GEM 5
|
||||
#define I915_PARAM_NUM_FENCES_AVAIL 6
|
||||
#define I915_PARAM_HAS_OVERLAY 7
|
||||
#define I915_PARAM_HAS_PAGEFLIPPING 8
|
||||
#define I915_PARAM_HAS_EXECBUF2 9
|
||||
#define I915_PARAM_HAS_BSD 10
|
||||
#define I915_PARAM_HAS_BLT 11
|
||||
#define I915_PARAM_HAS_RELAXED_FENCING 12
|
||||
#define I915_PARAM_HAS_COHERENT_RINGS 13
|
||||
#define I915_PARAM_HAS_EXEC_CONSTANTS 14
|
||||
#define I915_PARAM_HAS_RELAXED_DELTA 15
|
||||
#define I915_PARAM_HAS_GEN7_SOL_RESET 16
|
||||
#define I915_PARAM_HAS_LLC 17
|
||||
#define I915_PARAM_HAS_ALIASING_PPGTT 18
|
||||
#define I915_PARAM_HAS_WAIT_TIMEOUT 19
|
||||
|
||||
typedef struct drm_i915_getparam {
|
||||
int param;
|
||||
int *value;
|
||||
} drm_i915_getparam_t;
|
||||
|
||||
/* Ioctl to set kernel params:
|
||||
*/
|
||||
#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
|
||||
#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
|
||||
#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
|
||||
#define I915_SETPARAM_NUM_USED_FENCES 4
|
||||
|
||||
typedef struct drm_i915_setparam {
|
||||
int param;
|
||||
int value;
|
||||
} drm_i915_setparam_t;
|
||||
|
||||
/* A memory manager for regions of shared memory:
|
||||
*/
|
||||
#define I915_MEM_REGION_AGP 1
|
||||
|
||||
typedef struct drm_i915_mem_alloc {
|
||||
int region;
|
||||
int alignment;
|
||||
int size;
|
||||
int *region_offset; /* offset from start of fb or agp */
|
||||
} drm_i915_mem_alloc_t;
|
||||
|
||||
typedef struct drm_i915_mem_free {
|
||||
int region;
|
||||
int region_offset;
|
||||
} drm_i915_mem_free_t;
|
||||
|
||||
typedef struct drm_i915_mem_init_heap {
|
||||
int region;
|
||||
int size;
|
||||
int start;
|
||||
} drm_i915_mem_init_heap_t;
|
||||
|
||||
/* Allow memory manager to be torn down and re-initialized (eg on
|
||||
* rotate):
|
||||
*/
|
||||
typedef struct drm_i915_mem_destroy_heap {
|
||||
int region;
|
||||
} drm_i915_mem_destroy_heap_t;
|
||||
|
||||
/* Allow X server to configure which pipes to monitor for vblank signals
|
||||
*/
|
||||
#define DRM_I915_VBLANK_PIPE_A 1
|
||||
#define DRM_I915_VBLANK_PIPE_B 2
|
||||
|
||||
typedef struct drm_i915_vblank_pipe {
|
||||
int pipe;
|
||||
} drm_i915_vblank_pipe_t;
|
||||
|
||||
/* Schedule buffer swap at given vertical blank:
|
||||
*/
|
||||
typedef struct drm_i915_vblank_swap {
|
||||
drm_drawable_t drawable;
|
||||
enum drm_vblank_seq_type seqtype;
|
||||
unsigned int sequence;
|
||||
} drm_i915_vblank_swap_t;
|
||||
|
||||
typedef struct drm_i915_hws_addr {
|
||||
__u64 addr;
|
||||
} drm_i915_hws_addr_t;
|
||||
|
||||
struct drm_i915_gem_init {
|
||||
/**
|
||||
* Beginning offset in the GTT to be managed by the DRM memory
|
||||
* manager.
|
||||
*/
|
||||
__u64 gtt_start;
|
||||
/**
|
||||
* Ending offset in the GTT to be managed by the DRM memory
|
||||
* manager.
|
||||
*/
|
||||
__u64 gtt_end;
|
||||
};
|
||||
|
||||
struct drm_i915_gem_create {
|
||||
/**
|
||||
* Requested size for the object.
|
||||
*
|
||||
* The (page-aligned) allocated size for the object will be returned.
|
||||
*/
|
||||
__u64 size;
|
||||
/**
|
||||
* Returned handle for the object.
|
||||
*
|
||||
* Object handles are nonzero.
|
||||
*/
|
||||
__u32 handle;
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
struct drm_i915_gem_pread {
|
||||
/** Handle for the object being read. */
|
||||
__u32 handle;
|
||||
__u32 pad;
|
||||
/** Offset into the object to read from */
|
||||
__u64 offset;
|
||||
/** Length of data to read */
|
||||
__u64 size;
|
||||
/**
|
||||
* Pointer to write the data into.
|
||||
*
|
||||
* This is a fixed-size type for 32/64 compatibility.
|
||||
*/
|
||||
__u64 data_ptr;
|
||||
};
|
||||
|
||||
struct drm_i915_gem_pwrite {
|
||||
/** Handle for the object being written to. */
|
||||
__u32 handle;
|
||||
__u32 pad;
|
||||
/** Offset into the object to write to */
|
||||
__u64 offset;
|
||||
/** Length of data to write */
|
||||
__u64 size;
|
||||
/**
|
||||
* Pointer to read the data from.
|
||||
*
|
||||
* This is a fixed-size type for 32/64 compatibility.
|
||||
*/
|
||||
__u64 data_ptr;
|
||||
};
|
||||
|
||||
struct drm_i915_gem_mmap {
|
||||
/** Handle for the object being mapped. */
|
||||
__u32 handle;
|
||||
__u32 pad;
|
||||
/** Offset in the object to map. */
|
||||
__u64 offset;
|
||||
/**
|
||||
* Length of data to map.
|
||||
*
|
||||
* The value will be page-aligned.
|
||||
*/
|
||||
__u64 size;
|
||||
/**
|
||||
* Returned pointer the data was mapped at.
|
||||
*
|
||||
* This is a fixed-size type for 32/64 compatibility.
|
||||
*/
|
||||
__u64 addr_ptr;
|
||||
};
|
||||
|
||||
struct drm_i915_gem_mmap_gtt {
|
||||
/** Handle for the object being mapped. */
|
||||
__u32 handle;
|
||||
__u32 pad;
|
||||
/**
|
||||
* Fake offset to use for subsequent mmap call
|
||||
*
|
||||
* This is a fixed-size type for 32/64 compatibility.
|
||||
*/
|
||||
__u64 offset;
|
||||
};
|
||||
|
||||
struct drm_i915_gem_set_domain {
|
||||
/** Handle for the object */
|
||||
__u32 handle;
|
||||
|
||||
/** New read domains */
|
||||
__u32 read_domains;
|
||||
|
||||
/** New write domain */
|
||||
__u32 write_domain;
|
||||
};
|
||||
|
||||
struct drm_i915_gem_sw_finish {
|
||||
/** Handle for the object */
|
||||
__u32 handle;
|
||||
};
|
||||
|
||||
struct drm_i915_gem_relocation_entry {
|
||||
/**
|
||||
* Handle of the buffer being pointed to by this relocation entry.
|
||||
*
|
||||
* It's appealing to make this be an index into the mm_validate_entry
|
||||
* list to refer to the buffer, but this allows the driver to create
|
||||
* a relocation list for state buffers and not re-write it per
|
||||
* exec using the buffer.
|
||||
*/
|
||||
__u32 target_handle;
|
||||
|
||||
/**
|
||||
* Value to be added to the offset of the target buffer to make up
|
||||
* the relocation entry.
|
||||
*/
|
||||
__u32 delta;
|
||||
|
||||
/** Offset in the buffer the relocation entry will be written into */
|
||||
__u64 offset;
|
||||
|
||||
/**
|
||||
* Offset value of the target buffer that the relocation entry was last
|
||||
* written as.
|
||||
*
|
||||
* If the buffer has the same offset as last time, we can skip syncing
|
||||
* and writing the relocation. This value is written back out by
|
||||
* the execbuffer ioctl when the relocation is written.
|
||||
*/
|
||||
__u64 presumed_offset;
|
||||
|
||||
/**
|
||||
* Target memory domains read by this operation.
|
||||
*/
|
||||
__u32 read_domains;
|
||||
|
||||
/**
|
||||
* Target memory domains written by this operation.
|
||||
*
|
||||
* Note that only one domain may be written by the whole
|
||||
* execbuffer operation, so that where there are conflicts,
|
||||
* the application will get -EINVAL back.
|
||||
*/
|
||||
__u32 write_domain;
|
||||
};
|
||||
|
||||
/** @{
|
||||
* Intel memory domains
|
||||
*
|
||||
* Most of these just align with the various caches in
|
||||
* the system and are used to flush and invalidate as
|
||||
* objects end up cached in different domains.
|
||||
*/
|
||||
/** CPU cache */
|
||||
#define I915_GEM_DOMAIN_CPU 0x00000001
|
||||
/** Render cache, used by 2D and 3D drawing */
|
||||
#define I915_GEM_DOMAIN_RENDER 0x00000002
|
||||
/** Sampler cache, used by texture engine */
|
||||
#define I915_GEM_DOMAIN_SAMPLER 0x00000004
|
||||
/** Command queue, used to load batch buffers */
|
||||
#define I915_GEM_DOMAIN_COMMAND 0x00000008
|
||||
/** Instruction cache, used by shader programs */
|
||||
#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
|
||||
/** Vertex address cache */
|
||||
#define I915_GEM_DOMAIN_VERTEX 0x00000020
|
||||
/** GTT domain - aperture and scanout */
|
||||
#define I915_GEM_DOMAIN_GTT 0x00000040
|
||||
/** @} */
|
||||
|
||||
struct drm_i915_gem_exec_object {
|
||||
/**
|
||||
* User's handle for a buffer to be bound into the GTT for this
|
||||
* operation.
|
||||
*/
|
||||
__u32 handle;
|
||||
|
||||
/** Number of relocations to be performed on this buffer */
|
||||
__u32 relocation_count;
|
||||
/**
|
||||
* Pointer to array of struct drm_i915_gem_relocation_entry containing
|
||||
* the relocations to be performed in this buffer.
|
||||
*/
|
||||
__u64 relocs_ptr;
|
||||
|
||||
/** Required alignment in graphics aperture */
|
||||
__u64 alignment;
|
||||
|
||||
/**
|
||||
* Returned value of the updated offset of the object, for future
|
||||
* presumed_offset writes.
|
||||
*/
|
||||
__u64 offset;
|
||||
};
|
||||
|
||||
struct drm_i915_gem_execbuffer {
|
||||
/**
|
||||
* List of buffers to be validated with their relocations to be
|
||||
* performend on them.
|
||||
*
|
||||
* This is a pointer to an array of struct drm_i915_gem_validate_entry.
|
||||
*
|
||||
* These buffers must be listed in an order such that all relocations
|
||||
* a buffer is performing refer to buffers that have already appeared
|
||||
* in the validate list.
|
||||
*/
|
||||
__u64 buffers_ptr;
|
||||
__u32 buffer_count;
|
||||
|
||||
/** Offset in the batchbuffer to start execution from. */
|
||||
__u32 batch_start_offset;
|
||||
/** Bytes used in batchbuffer from batch_start_offset */
|
||||
__u32 batch_len;
|
||||
__u32 DR1;
|
||||
__u32 DR4;
|
||||
__u32 num_cliprects;
|
||||
/** This is a struct drm_clip_rect *cliprects */
|
||||
__u64 cliprects_ptr;
|
||||
};
|
||||
|
||||
struct drm_i915_gem_exec_object2 {
|
||||
/**
|
||||
* User's handle for a buffer to be bound into the GTT for this
|
||||
* operation.
|
||||
*/
|
||||
__u32 handle;
|
||||
|
||||
/** Number of relocations to be performed on this buffer */
|
||||
__u32 relocation_count;
|
||||
/**
|
||||
* Pointer to array of struct drm_i915_gem_relocation_entry containing
|
||||
* the relocations to be performed in this buffer.
|
||||
*/
|
||||
__u64 relocs_ptr;
|
||||
|
||||
/** Required alignment in graphics aperture */
|
||||
__u64 alignment;
|
||||
|
||||
/**
|
||||
* Returned value of the updated offset of the object, for future
|
||||
* presumed_offset writes.
|
||||
*/
|
||||
__u64 offset;
|
||||
|
||||
#define EXEC_OBJECT_NEEDS_FENCE (1<<0)
|
||||
__u64 flags;
|
||||
__u64 rsvd1;
|
||||
__u64 rsvd2;
|
||||
};
|
||||
|
||||
struct drm_i915_gem_execbuffer2 {
|
||||
/**
|
||||
* List of gem_exec_object2 structs
|
||||
*/
|
||||
__u64 buffers_ptr;
|
||||
__u32 buffer_count;
|
||||
|
||||
/** Offset in the batchbuffer to start execution from. */
|
||||
__u32 batch_start_offset;
|
||||
/** Bytes used in batchbuffer from batch_start_offset */
|
||||
__u32 batch_len;
|
||||
__u32 DR1;
|
||||
__u32 DR4;
|
||||
__u32 num_cliprects;
|
||||
/** This is a struct drm_clip_rect *cliprects */
|
||||
__u64 cliprects_ptr;
|
||||
#define I915_EXEC_RING_MASK (7<<0)
|
||||
#define I915_EXEC_DEFAULT (0<<0)
|
||||
#define I915_EXEC_RENDER (1<<0)
|
||||
#define I915_EXEC_BSD (2<<0)
|
||||
#define I915_EXEC_BLT (3<<0)
|
||||
|
||||
/* Used for switching the constants addressing mode on gen4+ RENDER ring.
|
||||
* Gen6+ only supports relative addressing to dynamic state (default) and
|
||||
* absolute addressing.
|
||||
*
|
||||
* These flags are ignored for the BSD and BLT rings.
|
||||
*/
|
||||
#define I915_EXEC_CONSTANTS_MASK (3<<6)
|
||||
#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */
|
||||
#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6)
|
||||
#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
|
||||
__u64 flags;
|
||||
__u64 rsvd1; /* now used for context info */
|
||||
__u64 rsvd2;
|
||||
};
|
||||
|
||||
/** Resets the SO write offset registers for transform feedback on gen7. */
|
||||
#define I915_EXEC_GEN7_SOL_RESET (1<<8)
|
||||
|
||||
#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
|
||||
#define i915_execbuffer2_set_context_id(eb2, context) \
|
||||
(eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
|
||||
#define i915_execbuffer2_get_context_id(eb2) \
|
||||
((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK)
|
||||
|
||||
struct drm_i915_gem_pin {
|
||||
/** Handle of the buffer to be pinned. */
|
||||
__u32 handle;
|
||||
__u32 pad;
|
||||
|
||||
/** alignment required within the aperture */
|
||||
__u64 alignment;
|
||||
|
||||
/** Returned GTT offset of the buffer. */
|
||||
__u64 offset;
|
||||
};
|
||||
|
||||
struct drm_i915_gem_unpin {
|
||||
/** Handle of the buffer to be unpinned. */
|
||||
__u32 handle;
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
struct drm_i915_gem_busy {
|
||||
/** Handle of the buffer to check for busy */
|
||||
__u32 handle;
|
||||
|
||||
/** Return busy status (1 if busy, 0 if idle).
|
||||
* The high word is used to indicate on which rings the object
|
||||
* currently resides:
|
||||
* 16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc)
|
||||
*/
|
||||
__u32 busy;
|
||||
};
|
||||
|
||||
#define I915_CACHEING_NONE 0
|
||||
#define I915_CACHEING_CACHED 1
|
||||
|
||||
struct drm_i915_gem_cacheing {
|
||||
/**
|
||||
* Handle of the buffer to set/get the cacheing level of. */
|
||||
__u32 handle;
|
||||
|
||||
/**
|
||||
* Cacheing level to apply or return value
|
||||
*
|
||||
* bits0-15 are for generic cacheing control (i.e. the above defined
|
||||
* values). bits16-31 are reserved for platform-specific variations
|
||||
* (e.g. l3$ caching on gen7). */
|
||||
__u32 cacheing;
|
||||
};
|
||||
|
||||
#define I915_TILING_NONE 0
|
||||
#define I915_TILING_X 1
|
||||
#define I915_TILING_Y 2
|
||||
|
||||
#define I915_BIT_6_SWIZZLE_NONE 0
|
||||
#define I915_BIT_6_SWIZZLE_9 1
|
||||
#define I915_BIT_6_SWIZZLE_9_10 2
|
||||
#define I915_BIT_6_SWIZZLE_9_11 3
|
||||
#define I915_BIT_6_SWIZZLE_9_10_11 4
|
||||
/* Not seen by userland */
|
||||
#define I915_BIT_6_SWIZZLE_UNKNOWN 5
|
||||
/* Seen by userland. */
|
||||
#define I915_BIT_6_SWIZZLE_9_17 6
|
||||
#define I915_BIT_6_SWIZZLE_9_10_17 7
|
||||
|
||||
struct drm_i915_gem_set_tiling {
|
||||
/** Handle of the buffer to have its tiling state updated */
|
||||
__u32 handle;
|
||||
|
||||
/**
|
||||
* Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
|
||||
* I915_TILING_Y).
|
||||
*
|
||||
* This value is to be set on request, and will be updated by the
|
||||
* kernel on successful return with the actual chosen tiling layout.
|
||||
*
|
||||
* The tiling mode may be demoted to I915_TILING_NONE when the system
|
||||
* has bit 6 swizzling that can't be managed correctly by GEM.
|
||||
*
|
||||
* Buffer contents become undefined when changing tiling_mode.
|
||||
*/
|
||||
__u32 tiling_mode;
|
||||
|
||||
/**
|
||||
* Stride in bytes for the object when in I915_TILING_X or
|
||||
* I915_TILING_Y.
|
||||
*/
|
||||
__u32 stride;
|
||||
|
||||
/**
|
||||
* Returned address bit 6 swizzling required for CPU access through
|
||||
* mmap mapping.
|
||||
*/
|
||||
__u32 swizzle_mode;
|
||||
};
|
||||
|
||||
struct drm_i915_gem_get_tiling {
|
||||
/** Handle of the buffer to get tiling state for. */
|
||||
__u32 handle;
|
||||
|
||||
/**
|
||||
* Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
|
||||
* I915_TILING_Y).
|
||||
*/
|
||||
__u32 tiling_mode;
|
||||
|
||||
/**
|
||||
* Returned address bit 6 swizzling required for CPU access through
|
||||
* mmap mapping.
|
||||
*/
|
||||
__u32 swizzle_mode;
|
||||
};
|
||||
|
||||
struct drm_i915_gem_get_aperture {
|
||||
/** Total size of the aperture used by i915_gem_execbuffer, in bytes */
|
||||
__u64 aper_size;
|
||||
|
||||
/**
|
||||
* Available space in the aperture used by i915_gem_execbuffer, in
|
||||
* bytes
|
||||
*/
|
||||
__u64 aper_available_size;
|
||||
};
|
||||
|
||||
struct drm_i915_get_pipe_from_crtc_id {
|
||||
/** ID of CRTC being requested **/
|
||||
__u32 crtc_id;
|
||||
|
||||
/** pipe of requested CRTC **/
|
||||
__u32 pipe;
|
||||
};
|
||||
|
||||
#define I915_MADV_WILLNEED 0
|
||||
#define I915_MADV_DONTNEED 1
|
||||
#define __I915_MADV_PURGED 2 /* internal state */
|
||||
|
||||
struct drm_i915_gem_madvise {
|
||||
/** Handle of the buffer to change the backing store advice */
|
||||
__u32 handle;
|
||||
|
||||
/* Advice: either the buffer will be needed again in the near future,
|
||||
* or wont be and could be discarded under memory pressure.
|
||||
*/
|
||||
__u32 madv;
|
||||
|
||||
/** Whether the backing store still exists. */
|
||||
__u32 retained;
|
||||
};
|
||||
|
||||
/* flags */
|
||||
#define I915_OVERLAY_TYPE_MASK 0xff
|
||||
#define I915_OVERLAY_YUV_PLANAR 0x01
|
||||
#define I915_OVERLAY_YUV_PACKED 0x02
|
||||
#define I915_OVERLAY_RGB 0x03
|
||||
|
||||
#define I915_OVERLAY_DEPTH_MASK 0xff00
|
||||
#define I915_OVERLAY_RGB24 0x1000
|
||||
#define I915_OVERLAY_RGB16 0x2000
|
||||
#define I915_OVERLAY_RGB15 0x3000
|
||||
#define I915_OVERLAY_YUV422 0x0100
|
||||
#define I915_OVERLAY_YUV411 0x0200
|
||||
#define I915_OVERLAY_YUV420 0x0300
|
||||
#define I915_OVERLAY_YUV410 0x0400
|
||||
|
||||
#define I915_OVERLAY_SWAP_MASK 0xff0000
|
||||
#define I915_OVERLAY_NO_SWAP 0x000000
|
||||
#define I915_OVERLAY_UV_SWAP 0x010000
|
||||
#define I915_OVERLAY_Y_SWAP 0x020000
|
||||
#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000
|
||||
|
||||
#define I915_OVERLAY_FLAGS_MASK 0xff000000
|
||||
#define I915_OVERLAY_ENABLE 0x01000000
|
||||
|
||||
struct drm_intel_overlay_put_image {
|
||||
/* various flags and src format description */
|
||||
__u32 flags;
|
||||
/* source picture description */
|
||||
__u32 bo_handle;
|
||||
/* stride values and offsets are in bytes, buffer relative */
|
||||
__u16 stride_Y; /* stride for packed formats */
|
||||
__u16 stride_UV;
|
||||
__u32 offset_Y; /* offset for packet formats */
|
||||
__u32 offset_U;
|
||||
__u32 offset_V;
|
||||
/* in pixels */
|
||||
__u16 src_width;
|
||||
__u16 src_height;
|
||||
/* to compensate the scaling factors for partially covered surfaces */
|
||||
__u16 src_scan_width;
|
||||
__u16 src_scan_height;
|
||||
/* output crtc description */
|
||||
__u32 crtc_id;
|
||||
__u16 dst_x;
|
||||
__u16 dst_y;
|
||||
__u16 dst_width;
|
||||
__u16 dst_height;
|
||||
};
|
||||
|
||||
/* flags */
|
||||
#define I915_OVERLAY_UPDATE_ATTRS (1<<0)
|
||||
#define I915_OVERLAY_UPDATE_GAMMA (1<<1)
|
||||
struct drm_intel_overlay_attrs {
|
||||
__u32 flags;
|
||||
__u32 color_key;
|
||||
__s32 brightness;
|
||||
__u32 contrast;
|
||||
__u32 saturation;
|
||||
__u32 gamma0;
|
||||
__u32 gamma1;
|
||||
__u32 gamma2;
|
||||
__u32 gamma3;
|
||||
__u32 gamma4;
|
||||
__u32 gamma5;
|
||||
};
|
||||
|
||||
/*
|
||||
* Intel sprite handling
|
||||
*
|
||||
* Color keying works with a min/mask/max tuple. Both source and destination
|
||||
* color keying is allowed.
|
||||
*
|
||||
* Source keying:
|
||||
* Sprite pixels within the min & max values, masked against the color channels
|
||||
* specified in the mask field, will be transparent. All other pixels will
|
||||
* be displayed on top of the primary plane. For RGB surfaces, only the min
|
||||
* and mask fields will be used; ranged compares are not allowed.
|
||||
*
|
||||
* Destination keying:
|
||||
* Primary plane pixels that match the min value, masked against the color
|
||||
* channels specified in the mask field, will be replaced by corresponding
|
||||
* pixels from the sprite plane.
|
||||
*
|
||||
* Note that source & destination keying are exclusive; only one can be
|
||||
* active on a given plane.
|
||||
*/
|
||||
|
||||
#define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */
|
||||
#define I915_SET_COLORKEY_DESTINATION (1<<1)
|
||||
#define I915_SET_COLORKEY_SOURCE (1<<2)
|
||||
struct drm_intel_sprite_colorkey {
|
||||
__u32 plane_id;
|
||||
__u32 min_value;
|
||||
__u32 channel_mask;
|
||||
__u32 max_value;
|
||||
__u32 flags;
|
||||
};
|
||||
|
||||
struct drm_i915_gem_wait {
|
||||
/** Handle of BO we shall wait on */
|
||||
__u32 bo_handle;
|
||||
__u32 flags;
|
||||
/** Number of nanoseconds to wait, Returns time remaining. */
|
||||
__s64 timeout_ns;
|
||||
};
|
||||
|
||||
struct drm_i915_gem_context_create {
|
||||
/* output: id of new context*/
|
||||
__u32 ctx_id;
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
struct drm_i915_gem_context_destroy {
|
||||
__u32 ctx_id;
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
struct drm_i915_reg_read {
|
||||
__u64 offset;
|
||||
__u64 val; /* Return value */
|
||||
};
|
||||
|
||||
struct drm_i915_mask_update {
|
||||
__u32 handle;
|
||||
__u32 width;
|
||||
__u32 height;
|
||||
__u32 bo_size;
|
||||
__u32 bo_pitch;
|
||||
__u32 bo_map;
|
||||
};
|
||||
|
||||
#endif /* _I915_DRM_H_ */
|
||||
@ -75,7 +75,7 @@ search_snoop_cache(struct kgem *kgem, unsigned int num_pages, unsigned flags);
|
||||
#define DEBUG_SYNC 0
|
||||
#endif
|
||||
|
||||
#define SHOW_BATCH 0
|
||||
#define SHOW_BATCH 1
|
||||
|
||||
#if 0
|
||||
#define ASSERT_IDLE(kgem__, handle__) assert(!__kgem_busy(kgem__, handle__))
|
||||
@ -136,7 +136,7 @@ struct local_i915_gem_cacheing {
|
||||
uint32_t cacheing;
|
||||
};
|
||||
|
||||
#define LOCAL_IOCTL_I915_GEM_SET_CACHEING SRV_I915_GEM_SET_CACHEING
|
||||
#define LOCAL_IOCTL_I915_GEM_SET_CACHEING SRV_I915_GEM_SET_CACHING
|
||||
|
||||
struct local_fbinfo {
|
||||
int width;
|
||||
@ -3913,6 +3913,48 @@ static void kgem_trim_vma_cache(struct kgem *kgem, int type, int bucket)
|
||||
}
|
||||
}
|
||||
|
||||
void *kgem_bo_map__async(struct kgem *kgem, struct kgem_bo *bo)
|
||||
{
|
||||
void *ptr;
|
||||
|
||||
DBG(("%s: handle=%d, offset=%d, tiling=%d, map=%p, domain=%d\n", __FUNCTION__,
|
||||
bo->handle, bo->presumed_offset, bo->tiling, bo->map, bo->domain));
|
||||
|
||||
assert(!bo->purged);
|
||||
assert(bo->proxy == NULL);
|
||||
assert(list_is_empty(&bo->list));
|
||||
|
||||
if (bo->tiling == I915_TILING_NONE && !bo->scanout && kgem->has_llc) {
|
||||
DBG(("%s: converting request for GTT map into CPU map\n",
|
||||
__FUNCTION__));
|
||||
return kgem_bo_map__cpu(kgem, bo);
|
||||
}
|
||||
|
||||
if (IS_CPU_MAP(bo->map))
|
||||
kgem_bo_release_map(kgem, bo);
|
||||
|
||||
ptr = bo->map;
|
||||
if (ptr == NULL) {
|
||||
assert(kgem_bo_size(bo) <= kgem->aperture_mappable / 2);
|
||||
|
||||
kgem_trim_vma_cache(kgem, MAP_GTT, bucket(bo));
|
||||
|
||||
ptr = __kgem_bo_map__gtt(kgem, bo);
|
||||
if (ptr == NULL)
|
||||
return NULL;
|
||||
|
||||
/* Cache this mapping to avoid the overhead of an
|
||||
* excruciatingly slow GTT pagefault. This is more an
|
||||
* issue with compositing managers which need to frequently
|
||||
* flush CPU damage to their GPU bo.
|
||||
*/
|
||||
bo->map = ptr;
|
||||
DBG(("%s: caching GTT vma for %d\n", __FUNCTION__, bo->handle));
|
||||
}
|
||||
|
||||
return ptr;
|
||||
}
|
||||
|
||||
|
||||
void *kgem_bo_map(struct kgem *kgem, struct kgem_bo *bo)
|
||||
{
|
||||
@ -4015,6 +4057,10 @@ void *kgem_bo_map__gtt(struct kgem *kgem, struct kgem_bo *bo)
|
||||
return ptr;
|
||||
}
|
||||
|
||||
void *kgem_bo_map__debug(struct kgem *kgem, struct kgem_bo *bo)
|
||||
{
|
||||
return kgem_bo_map__async(kgem, bo);
|
||||
}
|
||||
|
||||
void *kgem_bo_map__cpu(struct kgem *kgem, struct kgem_bo *bo)
|
||||
{
|
||||
|
||||
@ -28,7 +28,7 @@
|
||||
#ifndef KGEM_H
|
||||
#define KGEM_H
|
||||
|
||||
#define HAS_DEBUG_FULL 0
|
||||
#define HAS_DEBUG_FULL 1
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
@ -40,14 +40,6 @@
|
||||
#include "compiler.h"
|
||||
#include "intel_list.h"
|
||||
|
||||
static inline void delay(uint32_t time)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
"int $0x40"
|
||||
::"a"(5), "b"(time)
|
||||
:"memory");
|
||||
};
|
||||
|
||||
#undef DBG
|
||||
|
||||
#if HAS_DEBUG_FULL
|
||||
|
||||
451
drivers/video/Intel-2D/kgem_debug.c
Normal file
451
drivers/video/Intel-2D/kgem_debug.c
Normal file
@ -0,0 +1,451 @@
|
||||
/*
|
||||
* Copyright © 2007-2011 Intel Corporation
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Authors:
|
||||
* Eric Anholt <eric@anholt.net>
|
||||
*
|
||||
*/
|
||||
|
||||
#ifdef HAVE_CONFIG_H
|
||||
#include "config.h"
|
||||
#endif
|
||||
|
||||
//#include <sys/mman.h>
|
||||
#include <assert.h>
|
||||
|
||||
#include "sna.h"
|
||||
#include "sna_reg.h"
|
||||
|
||||
#include "kgem_debug.h"
|
||||
|
||||
#include <kos32sys.h>
|
||||
|
||||
/*
|
||||
void
|
||||
ErrorF(const char *f, ...)
|
||||
{
|
||||
va_list args;
|
||||
|
||||
va_start(args, f);
|
||||
VErrorF(f, args);
|
||||
va_end(args);
|
||||
}
|
||||
*/
|
||||
|
||||
#define ErrorF printf
|
||||
|
||||
struct drm_i915_gem_relocation_entry *
|
||||
kgem_debug_get_reloc_entry(struct kgem *kgem, uint32_t offset)
|
||||
{
|
||||
int i;
|
||||
|
||||
offset *= sizeof(uint32_t);
|
||||
|
||||
for (i = 0; i < kgem->nreloc; i++)
|
||||
if (kgem->reloc[i].offset == offset)
|
||||
return kgem->reloc+i;
|
||||
|
||||
assert(!"valid relocation entry, unknown batch offset");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
struct kgem_bo *
|
||||
kgem_debug_get_bo_for_reloc_entry(struct kgem *kgem,
|
||||
struct drm_i915_gem_relocation_entry *reloc)
|
||||
{
|
||||
struct kgem_bo *bo;
|
||||
|
||||
if (reloc == NULL)
|
||||
return NULL;
|
||||
|
||||
list_for_each_entry(bo, &kgem->next_request->buffers, request)
|
||||
if (bo->target_handle == reloc->target_handle && bo->proxy == NULL)
|
||||
break;
|
||||
|
||||
assert(&bo->request != &kgem->next_request->buffers);
|
||||
|
||||
return bo;
|
||||
}
|
||||
|
||||
static int kgem_debug_handle_is_fenced(struct kgem *kgem, uint32_t handle)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (kgem->has_handle_lut)
|
||||
return kgem->exec[handle].flags & EXEC_OBJECT_NEEDS_FENCE;
|
||||
|
||||
for (i = 0; i < kgem->nexec; i++)
|
||||
if (kgem->exec[i].handle == handle)
|
||||
return kgem->exec[i].flags & EXEC_OBJECT_NEEDS_FENCE;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int kgem_debug_handle_tiling(struct kgem *kgem, uint32_t handle)
|
||||
{
|
||||
struct kgem_bo *bo;
|
||||
|
||||
list_for_each_entry(bo, &kgem->next_request->buffers, request)
|
||||
if (bo->target_handle == handle)
|
||||
return bo->tiling;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void
|
||||
kgem_debug_print(const uint32_t *data,
|
||||
uint32_t offset, unsigned int index,
|
||||
const char *fmt, ...)
|
||||
{
|
||||
va_list va;
|
||||
char buf[240];
|
||||
int len;
|
||||
|
||||
len = snprintf(buf, sizeof(buf),
|
||||
"0x%08x: 0x%08x: %s",
|
||||
(offset + index) * 4,
|
||||
data[index],
|
||||
index == 0 ? "" : " ");
|
||||
|
||||
va_start(va, fmt);
|
||||
vsnprintf(buf + len, sizeof(buf) - len, fmt, va);
|
||||
va_end(va);
|
||||
|
||||
ErrorF("%s", buf);
|
||||
delay(1);
|
||||
}
|
||||
|
||||
static int
|
||||
decode_nop(struct kgem *kgem, uint32_t offset)
|
||||
{
|
||||
uint32_t *data = kgem->batch + offset;
|
||||
kgem_debug_print(data, offset, 0, "UNKNOWN\n");
|
||||
assert(0);
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int
|
||||
decode_mi(struct kgem *kgem, uint32_t offset)
|
||||
{
|
||||
static const struct {
|
||||
uint32_t opcode;
|
||||
int len_mask;
|
||||
int min_len;
|
||||
int max_len;
|
||||
const char *name;
|
||||
} opcodes[] = {
|
||||
{ 0x08, 0, 1, 1, "MI_ARB_ON_OFF" },
|
||||
{ 0x0a, 0, 1, 1, "MI_BATCH_BUFFER_END" },
|
||||
{ 0x30, 0x3f, 3, 3, "MI_BATCH_BUFFER" },
|
||||
{ 0x31, 0x3f, 2, 2, "MI_BATCH_BUFFER_START" },
|
||||
{ 0x14, 0x3f, 3, 3, "MI_DISPLAY_BUFFER_INFO" },
|
||||
{ 0x04, 0, 1, 1, "MI_FLUSH" },
|
||||
{ 0x22, 0x1f, 3, 3, "MI_LOAD_REGISTER_IMM" },
|
||||
{ 0x13, 0x3f, 2, 2, "MI_LOAD_SCAN_LINES_EXCL" },
|
||||
{ 0x12, 0x3f, 2, 2, "MI_LOAD_SCAN_LINES_INCL" },
|
||||
{ 0x00, 0, 1, 1, "MI_NOOP" },
|
||||
{ 0x11, 0x3f, 2, 2, "MI_OVERLAY_FLIP" },
|
||||
{ 0x07, 0, 1, 1, "MI_REPORT_HEAD" },
|
||||
{ 0x18, 0x3f, 2, 2, "MI_SET_CONTEXT" },
|
||||
{ 0x20, 0x3f, 3, 4, "MI_STORE_DATA_IMM" },
|
||||
{ 0x21, 0x3f, 3, 4, "MI_STORE_DATA_INDEX" },
|
||||
{ 0x24, 0x3f, 3, 3, "MI_STORE_REGISTER_MEM" },
|
||||
{ 0x02, 0, 1, 1, "MI_USER_INTERRUPT" },
|
||||
{ 0x03, 0, 1, 1, "MI_WAIT_FOR_EVENT" },
|
||||
{ 0x16, 0x7f, 3, 3, "MI_SEMAPHORE_MBOX" },
|
||||
{ 0x26, 0x1f, 3, 4, "MI_FLUSH_DW" },
|
||||
{ 0x0b, 0, 1, 1, "MI_SUSPEND_FLUSH" },
|
||||
};
|
||||
uint32_t *data = kgem->batch + offset;
|
||||
int op;
|
||||
|
||||
for (op = 0; op < ARRAY_SIZE(opcodes); op++) {
|
||||
if ((data[0] & 0x1f800000) >> 23 == opcodes[op].opcode) {
|
||||
unsigned int len = 1, i;
|
||||
|
||||
kgem_debug_print(data, offset, 0, "%s\n", opcodes[op].name);
|
||||
if (opcodes[op].max_len > 1) {
|
||||
len = (data[0] & opcodes[op].len_mask) + 2;
|
||||
if (len < opcodes[op].min_len ||
|
||||
len > opcodes[op].max_len)
|
||||
{
|
||||
ErrorF("Bad length (%d) in %s, [%d, %d]\n",
|
||||
len, opcodes[op].name,
|
||||
opcodes[op].min_len,
|
||||
opcodes[op].max_len);
|
||||
assert(0);
|
||||
}
|
||||
}
|
||||
|
||||
for (i = 1; i < len; i++)
|
||||
kgem_debug_print(data, offset, i, "dword %d\n", i);
|
||||
|
||||
return len;
|
||||
}
|
||||
}
|
||||
|
||||
kgem_debug_print(data, offset, 0, "MI UNKNOWN\n");
|
||||
assert(0);
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int
|
||||
decode_2d(struct kgem *kgem, uint32_t offset)
|
||||
{
|
||||
static const struct {
|
||||
uint32_t opcode;
|
||||
int min_len;
|
||||
int max_len;
|
||||
const char *name;
|
||||
} opcodes[] = {
|
||||
{ 0x40, 5, 5, "COLOR_BLT" },
|
||||
{ 0x43, 6, 6, "SRC_COPY_BLT" },
|
||||
{ 0x01, 8, 8, "XY_SETUP_BLT" },
|
||||
{ 0x11, 9, 9, "XY_SETUP_MONO_PATTERN_SL_BLT" },
|
||||
{ 0x03, 3, 3, "XY_SETUP_CLIP_BLT" },
|
||||
{ 0x24, 2, 2, "XY_PIXEL_BLT" },
|
||||
{ 0x25, 3, 3, "XY_SCANLINES_BLT" },
|
||||
{ 0x26, 4, 4, "Y_TEXT_BLT" },
|
||||
{ 0x31, 5, 134, "XY_TEXT_IMMEDIATE_BLT" },
|
||||
{ 0x50, 6, 6, "XY_COLOR_BLT" },
|
||||
{ 0x51, 6, 6, "XY_PAT_BLT" },
|
||||
{ 0x76, 8, 8, "XY_PAT_CHROMA_BLT" },
|
||||
{ 0x72, 7, 135, "XY_PAT_BLT_IMMEDIATE" },
|
||||
{ 0x77, 9, 137, "XY_PAT_CHROMA_BLT_IMMEDIATE" },
|
||||
{ 0x52, 9, 9, "XY_MONO_PAT_BLT" },
|
||||
{ 0x59, 7, 7, "XY_MONO_PAT_FIXED_BLT" },
|
||||
{ 0x53, 8, 8, "XY_SRC_COPY_BLT" },
|
||||
{ 0x54, 8, 8, "XY_MONO_SRC_COPY_BLT" },
|
||||
{ 0x71, 9, 137, "XY_MONO_SRC_COPY_IMMEDIATE_BLT" },
|
||||
{ 0x55, 9, 9, "XY_FULL_BLT" },
|
||||
{ 0x55, 9, 137, "XY_FULL_IMMEDIATE_PATTERN_BLT" },
|
||||
{ 0x56, 9, 9, "XY_FULL_MONO_SRC_BLT" },
|
||||
{ 0x75, 10, 138, "XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT" },
|
||||
{ 0x57, 12, 12, "XY_FULL_MONO_PATTERN_BLT" },
|
||||
{ 0x58, 12, 12, "XY_FULL_MONO_PATTERN_MONO_SRC_BLT" },
|
||||
};
|
||||
|
||||
unsigned int op, len;
|
||||
const char *format = NULL;
|
||||
uint32_t *data = kgem->batch + offset;
|
||||
struct drm_i915_gem_relocation_entry *reloc;
|
||||
|
||||
/* Special case the two most common ops that we detail in full */
|
||||
switch ((data[0] & 0x1fc00000) >> 22) {
|
||||
case 0x50:
|
||||
kgem_debug_print(data, offset, 0,
|
||||
"XY_COLOR_BLT (rgb %sabled, alpha %sabled, dst tile %d)\n",
|
||||
(data[0] & (1 << 20)) ? "en" : "dis",
|
||||
(data[0] & (1 << 21)) ? "en" : "dis",
|
||||
(data[0] >> 11) & 1);
|
||||
|
||||
len = (data[0] & 0x000000ff) + 2;
|
||||
assert(len == 6);
|
||||
|
||||
switch ((data[1] >> 24) & 0x3) {
|
||||
case 0:
|
||||
format="8";
|
||||
break;
|
||||
case 1:
|
||||
format="565";
|
||||
break;
|
||||
case 2:
|
||||
format="1555";
|
||||
break;
|
||||
case 3:
|
||||
format="8888";
|
||||
break;
|
||||
}
|
||||
|
||||
kgem_debug_print(data, offset, 1, "format %s, rop %x, pitch %d, "
|
||||
"clipping %sabled\n", format,
|
||||
(data[1] >> 16) & 0xff,
|
||||
(short)(data[1] & 0xffff),
|
||||
data[1] & (1 << 30) ? "en" : "dis");
|
||||
kgem_debug_print(data, offset, 2, "(%d,%d)\n",
|
||||
data[2] & 0xffff, data[2] >> 16);
|
||||
kgem_debug_print(data, offset, 3, "(%d,%d)\n",
|
||||
data[3] & 0xffff, data[3] >> 16);
|
||||
reloc = kgem_debug_get_reloc_entry(kgem, offset+4);
|
||||
kgem_debug_print(data, offset, 4, "dst offset 0x%08x [handle=%d, delta=%d, read=%x, write=%x (fenced? %d, tiling? %d)]\n",
|
||||
data[4],
|
||||
reloc->target_handle, reloc->delta,
|
||||
reloc->read_domains, reloc->write_domain,
|
||||
kgem_debug_handle_is_fenced(kgem, reloc->target_handle),
|
||||
kgem_debug_handle_tiling(kgem, reloc->target_handle));
|
||||
kgem_debug_print(data, offset, 5, "color\n");
|
||||
assert(kgem->gen >= 040 ||
|
||||
kgem_debug_handle_is_fenced(kgem, reloc->target_handle));
|
||||
return len;
|
||||
|
||||
case 0x53:
|
||||
kgem_debug_print(data, offset, 0,
|
||||
"XY_SRC_COPY_BLT (rgb %sabled, alpha %sabled, "
|
||||
"src tile %d, dst tile %d)\n",
|
||||
(data[0] & (1 << 20)) ? "en" : "dis",
|
||||
(data[0] & (1 << 21)) ? "en" : "dis",
|
||||
(data[0] >> 15) & 1,
|
||||
(data[0] >> 11) & 1);
|
||||
|
||||
len = (data[0] & 0x000000ff) + 2;
|
||||
assert(len == 8);
|
||||
|
||||
switch ((data[1] >> 24) & 0x3) {
|
||||
case 0:
|
||||
format="8";
|
||||
break;
|
||||
case 1:
|
||||
format="565";
|
||||
break;
|
||||
case 2:
|
||||
format="1555";
|
||||
break;
|
||||
case 3:
|
||||
format="8888";
|
||||
break;
|
||||
}
|
||||
|
||||
kgem_debug_print(data, offset, 1, "format %s, rop %x, dst pitch %d, "
|
||||
"clipping %sabled\n", format,
|
||||
(data[1] >> 16) & 0xff,
|
||||
(short)(data[1] & 0xffff),
|
||||
data[1] & (1 << 30) ? "en" : "dis");
|
||||
kgem_debug_print(data, offset, 2, "dst (%d,%d)\n",
|
||||
data[2] & 0xffff, data[2] >> 16);
|
||||
kgem_debug_print(data, offset, 3, "dst (%d,%d)\n",
|
||||
data[3] & 0xffff, data[3] >> 16);
|
||||
reloc = kgem_debug_get_reloc_entry(kgem, offset+4);
|
||||
assert(reloc);
|
||||
kgem_debug_print(data, offset, 4, "dst offset 0x%08x [handle=%d, delta=%d, read=%x, write=%x, (fenced? %d, tiling? %d)]\n",
|
||||
data[4],
|
||||
reloc->target_handle, reloc->delta,
|
||||
reloc->read_domains, reloc->write_domain,
|
||||
kgem_debug_handle_is_fenced(kgem, reloc->target_handle),
|
||||
kgem_debug_handle_tiling(kgem, reloc->target_handle));
|
||||
assert(kgem->gen >= 040 ||
|
||||
kgem_debug_handle_is_fenced(kgem, reloc->target_handle));
|
||||
|
||||
kgem_debug_print(data, offset, 5, "src (%d,%d)\n",
|
||||
data[5] & 0xffff, data[5] >> 16);
|
||||
kgem_debug_print(data, offset, 6, "src pitch %d\n",
|
||||
(short)(data[6] & 0xffff));
|
||||
reloc = kgem_debug_get_reloc_entry(kgem, offset+7);
|
||||
assert(reloc);
|
||||
kgem_debug_print(data, offset, 7, "src offset 0x%08x [handle=%d, delta=%d, read=%x, write=%x (fenced? %d, tiling? %d)]\n",
|
||||
data[7],
|
||||
reloc->target_handle, reloc->delta,
|
||||
reloc->read_domains, reloc->write_domain,
|
||||
kgem_debug_handle_is_fenced(kgem, reloc->target_handle),
|
||||
kgem_debug_handle_tiling(kgem, reloc->target_handle));
|
||||
assert(kgem->gen >= 040 ||
|
||||
kgem_debug_handle_is_fenced(kgem, reloc->target_handle));
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
for (op = 0; op < ARRAY_SIZE(opcodes); op++) {
|
||||
if ((data[0] & 0x1fc00000) >> 22 == opcodes[op].opcode) {
|
||||
unsigned int i;
|
||||
|
||||
len = 1;
|
||||
kgem_debug_print(data, offset, 0, "%s\n", opcodes[op].name);
|
||||
if (opcodes[op].max_len > 1) {
|
||||
len = (data[0] & 0x000000ff) + 2;
|
||||
assert(len >= opcodes[op].min_len &&
|
||||
len <= opcodes[op].max_len);
|
||||
}
|
||||
|
||||
for (i = 1; i < len; i++)
|
||||
kgem_debug_print(data, offset, i, "dword %d\n", i);
|
||||
|
||||
return len;
|
||||
}
|
||||
}
|
||||
|
||||
kgem_debug_print(data, offset, 0, "2D UNKNOWN\n");
|
||||
assert(0);
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int (*decode_3d(int gen))(struct kgem*, uint32_t)
|
||||
{
|
||||
return kgem_gen6_decode_3d;
|
||||
/*
|
||||
if (gen >= 0100) {
|
||||
} else if (gen >= 070) {
|
||||
return kgem_gen7_decode_3d;
|
||||
} else if (gen >= 060) {
|
||||
return kgem_gen6_decode_3d;
|
||||
} else if (gen >= 050) {
|
||||
return kgem_gen5_decode_3d;
|
||||
} else if (gen >= 040) {
|
||||
return kgem_gen4_decode_3d;
|
||||
} else if (gen >= 030) {
|
||||
return kgem_gen3_decode_3d;
|
||||
} else if (gen >= 020) {
|
||||
return kgem_gen2_decode_3d;
|
||||
}
|
||||
assert(0);
|
||||
*/
|
||||
}
|
||||
|
||||
static void (*finish_state(int gen))(struct kgem*)
|
||||
{
|
||||
|
||||
return kgem_gen6_finish_state;
|
||||
/*
|
||||
if (gen >= 0100) {
|
||||
} else if (gen >= 070) {
|
||||
return kgem_gen7_finish_state;
|
||||
} else if (gen >= 060) {
|
||||
return kgem_gen6_finish_state;
|
||||
} else if (gen >= 050) {
|
||||
return kgem_gen5_finish_state;
|
||||
} else if (gen >= 040) {
|
||||
return kgem_gen4_finish_state;
|
||||
} else if (gen >= 030) {
|
||||
return kgem_gen3_finish_state;
|
||||
} else if (gen >= 020) {
|
||||
return kgem_gen2_finish_state;
|
||||
}
|
||||
assert(0);
|
||||
*/
|
||||
}
|
||||
|
||||
void __kgem_batch_debug(struct kgem *kgem, uint32_t nbatch)
|
||||
{
|
||||
int (*const decode[])(struct kgem *, uint32_t) = {
|
||||
decode_mi,
|
||||
decode_nop,
|
||||
decode_2d,
|
||||
decode_3d(kgem->gen),
|
||||
};
|
||||
uint32_t offset = 0;
|
||||
|
||||
while (offset < nbatch) {
|
||||
int class = (kgem->batch[offset] & 0xe0000000) >> 29;
|
||||
assert(class < ARRAY_SIZE(decode));
|
||||
offset += decode[class](kgem, offset);
|
||||
}
|
||||
|
||||
finish_state(kgem->gen)(kgem);
|
||||
}
|
||||
34
drivers/video/Intel-2D/kgem_debug.h
Normal file
34
drivers/video/Intel-2D/kgem_debug.h
Normal file
@ -0,0 +1,34 @@
|
||||
#ifndef KGEM_DEBUG_H
|
||||
#define KGEM_DEBUG_H
|
||||
|
||||
void
|
||||
kgem_debug_print(const uint32_t *data,
|
||||
uint32_t offset, unsigned int index,
|
||||
const char *fmt, ...);
|
||||
|
||||
struct drm_i915_gem_relocation_entry *
|
||||
kgem_debug_get_reloc_entry(struct kgem *kgem, uint32_t offset);
|
||||
|
||||
struct kgem_bo *
|
||||
kgem_debug_get_bo_for_reloc_entry(struct kgem *kgem,
|
||||
struct drm_i915_gem_relocation_entry *reloc);
|
||||
|
||||
int kgem_gen7_decode_3d(struct kgem *kgem, uint32_t offset);
|
||||
void kgem_gen7_finish_state(struct kgem *kgem);
|
||||
|
||||
int kgem_gen6_decode_3d(struct kgem *kgem, uint32_t offset);
|
||||
void kgem_gen6_finish_state(struct kgem *kgem);
|
||||
|
||||
int kgem_gen5_decode_3d(struct kgem *kgem, uint32_t offset);
|
||||
void kgem_gen5_finish_state(struct kgem *kgem);
|
||||
|
||||
int kgem_gen4_decode_3d(struct kgem *kgem, uint32_t offset);
|
||||
void kgem_gen4_finish_state(struct kgem *kgem);
|
||||
|
||||
int kgem_gen3_decode_3d(struct kgem *kgem, uint32_t offset);
|
||||
void kgem_gen3_finish_state(struct kgem *kgem);
|
||||
|
||||
int kgem_gen2_decode_3d(struct kgem *kgem, uint32_t offset);
|
||||
void kgem_gen2_finish_state(struct kgem *kgem);
|
||||
|
||||
#endif
|
||||
1077
drivers/video/Intel-2D/kgem_debug_gen6.c
Normal file
1077
drivers/video/Intel-2D/kgem_debug_gen6.c
Normal file
File diff suppressed because it is too large
Load Diff
282
drivers/video/Intel-2D/pixlib2.c
Normal file
282
drivers/video/Intel-2D/pixlib2.c
Normal file
@ -0,0 +1,282 @@
|
||||
|
||||
// -kr -i4 -ts4 -bls -bl -bli0
|
||||
|
||||
#include <stdio.h>
|
||||
#include <malloc.h>
|
||||
#include <stdbool.h>
|
||||
#include <pixlib2.h>
|
||||
#include <kos32sys.h>
|
||||
|
||||
|
||||
#define DISPLAY_VERSION 0x0200 /* 2.00 */
|
||||
|
||||
#define SRV_GETVERSION 0
|
||||
#define SRV_GET_CAPS 3
|
||||
|
||||
|
||||
#define BUFFER_SIZE(n) ((n)*sizeof(uint32_t))
|
||||
#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask))
|
||||
#define ALIGN(x,a) __ALIGN_MASK(x,(typeof(x))(a)-1)
|
||||
|
||||
#define to_surface(x) (surface_t*)((x)->handle)
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t width;
|
||||
uint32_t height;
|
||||
void *data;
|
||||
uint32_t pitch;
|
||||
uint32_t bo;
|
||||
uint32_t bo_size;
|
||||
uint32_t flags;
|
||||
} surface_t;
|
||||
|
||||
|
||||
int sna_init(uint32_t service);
|
||||
void sna_fini();
|
||||
|
||||
int sna_create_bitmap(bitmap_t * bitmap);
|
||||
int sna_destroy_bitmap(bitmap_t * bitmap);
|
||||
int sna_lock_bitmap(bitmap_t * bitmap);
|
||||
int sna_resize_bitmap(bitmap_t *bitmap);
|
||||
//int sna_blit_copy(bitmap_t * src_bitmap, int dst_x, int dst_y,
|
||||
// int w, int h, int src_x, int src_y);
|
||||
int sna_blit_tex(bitmap_t * src_bitmap, bool scale, int dst_x, int dst_y,
|
||||
int w, int h, int src_x, int src_y);
|
||||
|
||||
|
||||
static uint32_t service;
|
||||
static uint32_t hw_caps;
|
||||
|
||||
|
||||
uint32_t init_pixlib(uint32_t caps)
|
||||
{
|
||||
uint32_t api_version;
|
||||
ioctl_t io;
|
||||
|
||||
if (service != 0)
|
||||
return caps & hw_caps;
|
||||
|
||||
service = get_service("DISPLAY");
|
||||
if (service == 0)
|
||||
goto fail;
|
||||
|
||||
io.handle = service;
|
||||
io.io_code = SRV_GETVERSION;
|
||||
io.input = NULL;
|
||||
io.inp_size = 0;
|
||||
io.output = &api_version;
|
||||
io.out_size = BUFFER_SIZE(1);
|
||||
|
||||
if (call_service(&io) != 0)
|
||||
goto fail;
|
||||
|
||||
if ((DISPLAY_VERSION > (api_version & 0xFFFF)) ||
|
||||
(DISPLAY_VERSION < (api_version >> 16)))
|
||||
goto fail;
|
||||
|
||||
hw_caps = sna_init(service);
|
||||
|
||||
if (hw_caps)
|
||||
printf("2D caps %s%s%s\n",
|
||||
(hw_caps & HW_BIT_BLIT) != 0 ? "HW_BIT_BLIT " : "",
|
||||
(hw_caps & HW_TEX_BLIT) != 0 ? "HW_TEX_BLIT " : "",
|
||||
(hw_caps & HW_VID_BLIT) != 0 ? "HW_VID_BLIT " : "");
|
||||
|
||||
return caps & hw_caps;
|
||||
|
||||
fail:
|
||||
service = 0;
|
||||
return 0;
|
||||
};
|
||||
|
||||
void done_pixlib()
|
||||
{
|
||||
if (hw_caps != 0)
|
||||
sna_fini();
|
||||
};
|
||||
|
||||
|
||||
int create_bitmap(bitmap_t * bitmap)
|
||||
{
|
||||
uint32_t size, bo_size;
|
||||
uint32_t pitch, max_pitch;
|
||||
void *buffer;
|
||||
surface_t *sf;
|
||||
|
||||
bitmap->handle = -1;
|
||||
bitmap->data = (void *) -1;
|
||||
bitmap->pitch = -1;
|
||||
|
||||
if (bitmap->flags &= hw_caps)
|
||||
return sna_create_bitmap(bitmap);
|
||||
|
||||
pitch = ALIGN(bitmap->width * 4, 16);
|
||||
max_pitch = ALIGN(bitmap->max_width * 4, 16);
|
||||
|
||||
size = ALIGN(pitch * bitmap->height, 4096);
|
||||
bo_size = ALIGN(max_pitch * bitmap->max_height, 4096);
|
||||
|
||||
if (bo_size < size)
|
||||
bo_size = size;
|
||||
|
||||
sf = malloc(sizeof(*sf));
|
||||
if (sf == NULL)
|
||||
return -1;
|
||||
|
||||
buffer = user_alloc(bo_size);
|
||||
|
||||
if (buffer == NULL)
|
||||
{
|
||||
free(sf);
|
||||
return -1;
|
||||
};
|
||||
|
||||
sf->width = bitmap->width;
|
||||
sf->height = bitmap->height;
|
||||
sf->data = buffer;
|
||||
sf->pitch = pitch;
|
||||
sf->bo = 0;
|
||||
sf->bo_size = bo_size;
|
||||
sf->flags = bitmap->flags;
|
||||
|
||||
bitmap->handle = (uint32_t) sf;
|
||||
|
||||
// printf("create bitmap %p handle %p data %p w %d h%d\n",
|
||||
// bitmap, bitmap->handle, bitmap->data, bitmap->width, bitmap->height);
|
||||
|
||||
return 0;
|
||||
};
|
||||
|
||||
int destroy_bitmap(bitmap_t * bitmap)
|
||||
{
|
||||
surface_t *sf = to_surface(bitmap);
|
||||
|
||||
if (sf->flags & hw_caps)
|
||||
return sna_destroy_bitmap(bitmap);
|
||||
|
||||
user_free(sf->data);
|
||||
free(sf);
|
||||
|
||||
bitmap->handle = -1;
|
||||
bitmap->data = (void *) -1;
|
||||
bitmap->pitch = -1;
|
||||
|
||||
return 0;
|
||||
};
|
||||
|
||||
int lock_bitmap(bitmap_t * bitmap)
|
||||
{
|
||||
surface_t *sf = to_surface(bitmap);
|
||||
|
||||
if (bitmap->data != (void *) -1)
|
||||
return 0;
|
||||
|
||||
if (sf->flags & hw_caps)
|
||||
return sna_lock_bitmap(bitmap);
|
||||
|
||||
bitmap->data = sf->data;
|
||||
bitmap->pitch = sf->pitch;
|
||||
|
||||
return 0;
|
||||
};
|
||||
|
||||
int blit_bitmap(bitmap_t * bitmap, int dst_x, int dst_y,
|
||||
int w, int h, int src_x, int src_y)
|
||||
{
|
||||
struct blit_call bc;
|
||||
int ret;
|
||||
|
||||
surface_t *sf = to_surface(bitmap);
|
||||
|
||||
if (sf->flags & hw_caps & HW_BIT_BLIT)
|
||||
return sna_blit_tex(bitmap, false, dst_x, dst_y, w, h, src_x, src_y);
|
||||
|
||||
bc.dstx = dst_x;
|
||||
bc.dsty = dst_y;
|
||||
bc.w = w;
|
||||
bc.h = h;
|
||||
bc.srcx = 0;
|
||||
bc.srcy = 0;
|
||||
bc.srcw = w;
|
||||
bc.srch = h;
|
||||
bc.stride = sf->pitch;
|
||||
bc.bitmap = sf->data;
|
||||
|
||||
__asm__ __volatile__(
|
||||
"int $0x40":"=a"(ret):"a"(73), "b"(0x00),
|
||||
"c"(&bc):"memory");
|
||||
|
||||
bitmap->data = (void *) -1;
|
||||
bitmap->pitch = -1;
|
||||
|
||||
return ret;
|
||||
};
|
||||
|
||||
int fplay_blit_bitmap(bitmap_t * bitmap, int dst_x, int dst_y, int w, int h)
|
||||
{
|
||||
struct blit_call bc;
|
||||
int ret;
|
||||
|
||||
surface_t *sf = to_surface(bitmap);
|
||||
|
||||
if (sf->flags & hw_caps & HW_TEX_BLIT)
|
||||
return sna_blit_tex(bitmap, true, dst_x, dst_y, w, h, 0, 0);
|
||||
|
||||
bc.dstx = dst_x;
|
||||
bc.dsty = dst_y;
|
||||
bc.w = w;
|
||||
bc.h = h;
|
||||
bc.srcx = 0;
|
||||
bc.srcy = 0;
|
||||
bc.srcw = w;
|
||||
bc.srch = h;
|
||||
bc.stride = sf->pitch;
|
||||
bc.bitmap = sf->data;
|
||||
|
||||
__asm__ __volatile__(
|
||||
"int $0x40":"=a"(ret):"a"(73), "b"(0x00),
|
||||
"c"(&bc):"memory");
|
||||
|
||||
bitmap->data = (void *) -1;
|
||||
bitmap->pitch = -1;
|
||||
|
||||
return ret;
|
||||
};
|
||||
|
||||
int resize_bitmap(bitmap_t * bitmap)
|
||||
{
|
||||
uint32_t size;
|
||||
uint32_t pitch;
|
||||
|
||||
// printf("%s\n", __FUNCTION__);
|
||||
|
||||
surface_t *sf = to_surface(bitmap);
|
||||
|
||||
if (sf->flags & hw_caps)
|
||||
{
|
||||
return sna_resize_bitmap(bitmap);
|
||||
};
|
||||
|
||||
pitch = ALIGN(bitmap->width * 4, 16);
|
||||
size = ALIGN(pitch * bitmap->height, 4096);
|
||||
|
||||
bitmap->pitch = -1;
|
||||
bitmap->data = (void *) -1;
|
||||
|
||||
if (size > sf->bo_size)
|
||||
{
|
||||
sf->data = user_realloc(sf->data, size); /* grow buffer */
|
||||
if (sf->data == NULL)
|
||||
return -1;
|
||||
|
||||
sf->bo_size = size;
|
||||
} else if (size < sf->bo_size)
|
||||
user_unmap(sf->data, size, sf->bo_size - size); /* unmap unused pages */
|
||||
|
||||
sf->width = bitmap->width;
|
||||
sf->height = bitmap->height;
|
||||
sf->pitch = pitch;
|
||||
|
||||
return 0;
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user