move drivers from programs/system/drivers into /drivers

git-svn-id: svn://kolibrios.org@1029 a494cfbc-eb01-0410-851d-a64ba20cac60

drivers/audio/a5536/geode.c

@@ -9,6 +9,8 @@
 
 #include "geode.h"
 
+#define DEBUG
+
 #ifdef DEBUG
   #define DBG(format,...) dbgprintf(format,##__VA_ARGS__)
 #else
@@ -308,9 +310,16 @@ Bool init_device()
        return FALSE;
     }
 
+    u16_t id7c, id7e;
+
+    id7c = snd_hw_CodecRead(AD1819A_VENDORID1);
+    id7e = snd_hw_CodecRead(AD1819A_VENDORID2);
+
+    dbgprintf("codec id 0x7C %x  0x7E %x\n", id7c, id7e);
+
     /*Check which codec is being used */
-    if (snd_hw_CodecRead(AD1819A_VENDORID1) == 0x4144 &&
+    if ( (id7c == 0x4144) &&
-        snd_hw_CodecRead(AD1819A_VENDORID2) == 0x5303)
+         (id7e == 0x5303) )
     {
         geode.fAD1819A = TRUE;
         /*  Enable non-48kHz sample rates. */
@@ -322,16 +331,16 @@ Bool init_device()
     else
     {
         geode.fAD1819A = FALSE;
-        snd_hw_CodecWrite (EXT_AUDIO_CTRL_STAT,
+        snd_hw_CodecWrite(EXT_AUDIO_CTRL_STAT,
         (snd_hw_CodecRead(EXT_AUDIO_CTRL_STAT) | 0x0001));
         /* set the VRA bit to ON*/
     }
 
     /* set default volume*/
-    snd_hw_CodecWrite( MASTER_VOLUME,       0x0B0B);
+    snd_hw_CodecWrite( MASTER_VOLUME,       0x0909);
-    snd_hw_CodecWrite( PCM_OUT_VOL,         0x0808);
+    snd_hw_CodecWrite( PCM_OUT_VOL,         0x0606);
     snd_hw_CodecWrite( PC_BEEP_VOLUME,      0x0000);
-    snd_hw_CodecWrite( PHONE_VOLUME,        0x8000);
+    snd_hw_CodecWrite( PHONE_VOLUME,        0x0606);
     snd_hw_CodecWrite( MIC_VOLUME,          0x8048);
     snd_hw_CodecWrite( LINE_IN_VOLUME,      0x0808);
     snd_hw_CodecWrite( CD_VOLUME,           0x8000);

drivers/audio/a5536/geode.lk

@@ -0,0 +1,23 @@
+IMP
+    _KernelAlloc       core.KernelAlloc,
+    _KernelFree        core.KernelFree,
+    _CommitPages       core.CommitPages,
+    _MapIoMem          core.MapIoMem,
+    _GetPgAddr         core.GetPgAddr,
+    _CreateRingBuffer  core.CreateRingBuffer,
+    _PciApi            core.PciApi,
+    _PciRead8          core.PciRead8,
+    _PciRead16         core.PciRead16,
+    _PciRead32         core.PciRead32,
+    _PciWrite8         core.PciWrite8,
+    _PciWrite16        core.PciWrite16,
+    _PciWrite32        core.PciWrite32,
+    _RegService        core.RegService,
+    _AttachIntHandler  core.AttachIntHandler,
+    _SysMsgBoardStr    core.SysMsgBoardStr,
+    _Delay             core.Delay
+
+
+FIL geode.obj,
+    vsprintf.obj,
+    icompute.obj

drivers/audio/a5536/makefile

@@ -4,12 +4,12 @@ FASM = e:/fasm/fasm.exe
 CFLAGS = -c -O2 -fomit-frame-pointer -fno-builtin-printf 
 LDRHD  = -shared -T ld.x -s --file-alignment 32
 
-INCLUDES = -I ../include
+INCLUDES = -I ../../include
 
-HFILES:=     ../include/types.h		\
+HFILES:=     ../../include/types.h	\
-             ../include/syscall.h	\
+             ../../include/syscall.h	\
-             geode.h			\
+             ../../include/pci.h	\
-             pci.h
+             geode.h			
 
 SRC_DEP:=    
 GEODE_SRC:=    amd_geode.h     

drivers/include/pci.h

@@ -0,0 +1,183 @@
+
+
+#pragma pack(push, 1)
+typedef struct
+{
+     u16_t device;
+     u16_t ChipSet;
+}PciChipset_t;
+#pragma pack(pop)
+
+#define VENDOR_ATI                 0x1002
+
+
+#define PCI_CLASS_DISPLAY_VGA      0x0300
+/*
+ * Under PCI, each device has 256 bytes of configuration address space,
+ * of which the first 64 bytes are standardized as follows:
+ */
+#define PCI_VENDOR_ID                   0x000    /* 16 bits */
+#define PCI_DEVICE_ID                   0x002    /* 16 bits */
+#define PCI_COMMAND                     0x004    /* 16 bits */
+#define  PCI_COMMAND_IO                 0x001    /* Enable response in I/O space */
+#define  PCI_COMMAND_MEMORY             0x002    /* Enable response in Memory space */
+#define  PCI_COMMAND_MASTER             0x004    /* Enable bus mastering */
+#define  PCI_COMMAND_SPECIAL            0x008    /* Enable response to special cycles */
+#define  PCI_COMMAND_INVALIDATE         0x010    /* Use memory write and invalidate */
+#define  PCI_COMMAND_VGA_PALETTE        0x020    /* Enable palette snooping */
+#define  PCI_COMMAND_PARITY             0x040    /* Enable parity checking */
+#define  PCI_COMMAND_WAIT               0x080    /* Enable address/data stepping */
+#define  PCI_COMMAND_SERR               0x100    /* Enable SERR */
+#define  PCI_COMMAND_FAST_BACK          0x200    /* Enable back-to-back writes */
+#define  PCI_COMMAND_INTX_DISABLE       0x400    /* INTx Emulation Disable */
+
+#define PCI_STATUS                      0x006    /* 16 bits */
+#define  PCI_STATUS_CAP_LIST            0x010    /* Support Capability List */
+#define  PCI_STATUS_66MHZ               0x020    /* Support 66 Mhz PCI 2.1 bus */
+#define  PCI_STATUS_UDF                 0x040    /* Support User Definable Features [obsolete] */
+#define  PCI_STATUS_FAST_BACK           0x080    /* Accept fast-back to back */
+#define  PCI_STATUS_PARITY              0x100    /* Detected parity error */
+#define  PCI_STATUS_DEVSEL_MASK         0x600    /* DEVSEL timing */
+#define  PCI_STATUS_DEVSEL_FAST         0x000
+#define  PCI_STATUS_DEVSEL_MEDIUM       0x200
+#define  PCI_STATUS_DEVSEL_SLOW         0x400
+#define  PCI_STATUS_SIG_TARGET_ABORT    0x800    /* Set on target abort */
+#define  PCI_STATUS_REC_TARGET_ABORT    0x1000   /* Master ack of " */
+#define  PCI_STATUS_REC_MASTER_ABORT    0x2000   /* Set on master abort */
+#define  PCI_STATUS_SIG_SYSTEM_ERROR    0x4000   /* Set when we drive SERR */
+#define  PCI_STATUS_DETECTED_PARITY     0x8000   /* Set on parity error */
+
+#define PCI_CLASS_REVISION               0x08    /* High 24 bits are class, low 8 revision */
+#define PCI_REVISION_ID                  0x08    /* Revision ID */
+#define PCI_CLASS_PROG                   0x09    /* Reg. Level Programming Interface */
+#define PCI_CLASS_DEVICE                 0x0a    /* Device class */
+
+#define PCI_CACHE_LINE_SIZE              0x0c    /* 8 bits */
+#define PCI_LATENCY_TIMER                0x0d    /* 8 bits */
+#define PCI_HEADER_TYPE                  0x0e    /* 8 bits */
+#define  PCI_HEADER_TYPE_NORMAL             0
+#define  PCI_HEADER_TYPE_BRIDGE             1
+#define  PCI_HEADER_TYPE_CARDBUS            2
+
+#define PCI_BIST                         0x0f    /* 8 bits */
+#define  PCI_BIST_CODE_MASK              0x0f    /* Return result */
+#define  PCI_BIST_START                  0x40    /* 1 to start BIST, 2 secs or less */
+#define  PCI_BIST_CAPABLE                0x80    /* 1 if BIST capable */
+
+#define PCI_CAPABILITY_LIST              0x34    /* Offset of first capability list entry */
+#define PCI_CB_CAPABILITY_LIST           0x14
+/* Capability lists */
+
+#define PCI_CAP_LIST_ID                  0       /* Capability ID */
+#define  PCI_CAP_ID_PM                   0x01    /* Power Management */
+#define  PCI_CAP_ID_AGP                  0x02    /* Accelerated Graphics Port */
+#define  PCI_CAP_ID_VPD                  0x03    /* Vital Product Data */
+#define  PCI_CAP_ID_SLOTID               0x04    /* Slot Identification */
+#define  PCI_CAP_ID_MSI                  0x05    /* Message Signalled Interrupts */
+#define  PCI_CAP_ID_CHSWP                0x06    /* CompactPCI HotSwap */
+#define  PCI_CAP_ID_PCIX                 0x07    /* PCI-X */
+#define  PCI_CAP_ID_HT                   0x08    /* HyperTransport */
+#define  PCI_CAP_ID_VNDR                 0x09    /* Vendor specific capability */
+#define  PCI_CAP_ID_SHPC                 0x0C    /* PCI Standard Hot-Plug Controller */
+#define  PCI_CAP_ID_EXP                  0x10    /* PCI Express */
+#define  PCI_CAP_ID_MSIX                 0x11    /* MSI-X */
+#define PCI_CAP_LIST_NEXT                1       /* Next capability in the list */
+#define PCI_CAP_FLAGS                    2       /* Capability defined flags (16 bits) */
+#define PCI_CAP_SIZEOF                   4
+
+
+/* AGP registers */
+
+#define PCI_AGP_VERSION                     2   /* BCD version number */
+#define PCI_AGP_RFU                         3   /* Rest of capability flags */
+#define PCI_AGP_STATUS                      4   /* Status register */
+#define  PCI_AGP_STATUS_RQ_MASK        0xff000000  /* Maximum number of requests - 1 */
+#define  PCI_AGP_STATUS_SBA            0x0200   /* Sideband addressing supported */
+#define  PCI_AGP_STATUS_64BIT          0x0020   /* 64-bit addressing supported */
+#define  PCI_AGP_STATUS_FW             0x0010   /* FW transfers supported */
+#define  PCI_AGP_STATUS_RATE4          0x0004   /* 4x transfer rate supported */
+#define  PCI_AGP_STATUS_RATE2          0x0002   /* 2x transfer rate supported */
+#define  PCI_AGP_STATUS_RATE1          0x0001   /* 1x transfer rate supported */
+#define PCI_AGP_COMMAND                     8   /* Control register */
+#define  PCI_AGP_COMMAND_RQ_MASK    0xff000000  /* Master: Maximum number of requests */
+#define  PCI_AGP_COMMAND_SBA           0x0200   /* Sideband addressing enabled */
+#define  PCI_AGP_COMMAND_AGP           0x0100   /* Allow processing of AGP transactions */
+#define  PCI_AGP_COMMAND_64BIT         0x0020   /* Allow processing of 64-bit addresses */
+#define  PCI_AGP_COMMAND_FW            0x0010   /* Force FW transfers */
+#define  PCI_AGP_COMMAND_RATE4         0x0004   /* Use 4x rate */
+#define  PCI_AGP_COMMAND_RATE2         0x0002   /* Use 2x rate */
+#define  PCI_AGP_COMMAND_RATE1         0x0001   /* Use 1x rate */
+#define PCI_AGP_SIZEOF                     12
+
+
+#define PCI_MAP_REG_START                   0x10
+#define PCI_MAP_REG_END                     0x28
+#define PCI_MAP_ROM_REG                     0x30
+
+#define PCI_MAP_MEMORY                0x00000000
+#define PCI_MAP_IO                    0x00000001
+
+#define PCI_MAP_MEMORY_TYPE           0x00000007
+#define PCI_MAP_IO_TYPE               0x00000003
+
+#define PCI_MAP_MEMORY_TYPE_32BIT     0x00000000
+#define PCI_MAP_MEMORY_TYPE_32BIT_1M  0x00000002
+#define PCI_MAP_MEMORY_TYPE_64BIT     0x00000004
+#define PCI_MAP_MEMORY_TYPE_MASK      0x00000006
+#define PCI_MAP_MEMORY_CACHABLE       0x00000008
+#define PCI_MAP_MEMORY_ATTR_MASK      0x0000000e
+#define PCI_MAP_MEMORY_ADDRESS_MASK   0xfffffff0
+
+#define PCI_MAP_IO_ATTR_MASK          0x00000003
+
+
+
+#define PCI_MAP_IS_IO(b)  ((b) & PCI_MAP_IO)
+#define PCI_MAP_IS_MEM(b)	(!PCI_MAP_IS_IO(b))
+
+#define PCI_MAP_IS64BITMEM(b)	\
+	(((b) & PCI_MAP_MEMORY_TYPE_MASK) == PCI_MAP_MEMORY_TYPE_64BIT)
+
+#define PCIGETMEMORY(b)   ((b) & PCI_MAP_MEMORY_ADDRESS_MASK)
+#define PCIGETMEMORY64HIGH(b)	(*((CARD32*)&b + 1))
+#define PCIGETMEMORY64(b)	\
+	(PCIGETMEMORY(b) | ((CARD64)PCIGETMEMORY64HIGH(b) << 32))
+
+#define PCI_MAP_IO_ADDRESS_MASK       0xfffffffc
+
+#define PCIGETIO(b)		((b) & PCI_MAP_IO_ADDRESS_MASK)
+
+#define PCI_MAP_ROM_DECODE_ENABLE     0x00000001
+#define PCI_MAP_ROM_ADDRESS_MASK      0xfffff800
+
+#define PCIGETROM(b)		((b) & PCI_MAP_ROM_ADDRESS_MASK)
+
+
+#ifndef PCI_DOM_MASK
+# define PCI_DOM_MASK 0x0ffu
+#endif
+#define PCI_DOMBUS_MASK (((PCI_DOM_MASK) << 8) | 0x0ffu)
+
+#define PCI_MAKE_TAG(b,d,f)  ((((b) & (PCI_DOMBUS_MASK)) << 16) | \
+			      (((d) & 0x00001fu) << 11) | \
+			      (((f) & 0x000007u) << 8))
+
+#define PCI_BUS_FROM_TAG(tag)  (((tag) >> 16) & (PCI_DOMBUS_MASK))
+#define PCI_DEV_FROM_TAG(tag)  (((tag) & 0x0000f800u) >> 11)
+#define PCI_FUNC_FROM_TAG(tag) (((tag) & 0x00000700u) >> 8)
+#define PCI_DFN_FROM_TAG(tag)  (((tag) & 0x0000ff00u) >> 8)
+
+
+#define PCI_CMD_STAT_REG        0x04
+
+
+typedef unsigned int PCITAG;
+
+extern inline PCITAG
+pciTag(int busnum, int devnum, int funcnum)
+{
+	return(PCI_MAKE_TAG(busnum,devnum,funcnum));
+}
+
+const PciChipset_t *PciDevMatch(u16_t dev,const PciChipset_t *list);
+u32_t pciGetBaseSize(int bus, int devfn, int index, Bool destructive, Bool *min);

drivers/include/syscall.h

@@ -308,3 +308,9 @@ extern inline void delay(int time)
 
 }
 
+extern inline void change_task()
+{
+     __asm__ __volatile__ (
+     "call *__imp__ChangeTask");
+}
+

drivers/usb/uhci/detect.inc

@@ -1,6 +1,6 @@
 
 
-Bool FindPciDevice()
+static Bool FindPciDevice()
 {
     Bool retval = FALSE;
     u32_t bus, last_bus;

drivers/usb/uhci/makefile

@@ -4,12 +4,12 @@ FASM = e:/fasm/fasm.exe
 CFLAGS = -c -O2 -fomit-frame-pointer -fno-builtin-printf 
 LDRHD  = -shared -T ld.x -s --file-alignment 32
 
-INCLUDES = -I ../include
+INCLUDES = -I ../../include
 
-HFILES:=     ../include/types.h		\
+HFILES:=     ../../include/types.h	\
-             ../include/syscall.h	\
+             ../../include/syscall.h	\
-             ../include/link.h        	\
+             ../../include/link.h       \
-             pci.h        		\
+             ../../include/pci.h        \
              usb.h
 
 SRC_DEP:=    pci.inc		\
@@ -27,7 +27,7 @@ USB =        usb.dll
 all: $(USB)
 
 $(USB): $(USB_OBJ) $(SRC_DEP) $(HFILES) Makefile
-	wlink name usb.dll SYS nt_dll lib libdrv op offset=0 op nod op maxe=25 op el op STUB=stub.exe op START=_drvEntry @usb.lk1
+	wlink name usb.dll SYS nt_dll lib libdrv op offset=0 op nod op maxe=25 op el op STUB=stub.exe op START=_drvEntry @usb.lk
 	kpack.exe usb.dll usb.drv
 
 usb.obj : usb.c $(SRC_DEP) $(HFILES) Makefile

drivers/usb/uhci/usb.c

@@ -12,6 +12,7 @@
 #include "syscall.h"
 #include "usb.h"
 
+static Bool FindPciDevice();
 
 int __stdcall srv_usb(ioctl_t *io);
 

drivers/video/agp/agp.h

@@ -138,5 +138,10 @@ typedef struct
 #define max_t(type,x,y) \
 	({ type __x = (x); type __y = (y); __x > __y ? __x: __y; })
 
+#define PCI_ANY_ID (~0)
+
+#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d))!=-1)
+
+
 
 

drivers/video/agp/makefile

@@ -4,12 +4,11 @@ FASM = e:/fasm/fasm.exe
 CFLAGS = -c -O2 -fomit-frame-pointer -fno-builtin-printf 
 LDRHD  = -shared -T ld.x -s --file-alignment 32
 
-INCLUDES = -I ../include
+INCLUDES = -I ../../include
 
-HFILES:=     ../include/types.h		\
+HFILES:=     ../../include/types.h	\
-             ../include/syscall.h	\
+             ../../include/syscall.h	\
-             agp.h			\
+             agp.h
-             pci.h        		\
 
 SRC_DEP:=    pci.inc		\
              detect.inc		\

drivers/video/ati2d/accel_2d.inc

@@ -2,18 +2,17 @@
 
 int ClearPixmap(io_clear_t *io)
 {
-     u32_t ifl;
      u32_t *ring;
 
      local_pixmap_t *dstpixmap;
 
      dstpixmap = (io->dstpix == (void*)-1) ? &scr_pixmap : io->dstpix ;
 
-     ifl = safe_cli();
+     lock_device();
 
 #if R300_PIO
 
-     R5xxFIFOWait(6);
+     FIFOWait(6);
 
      OUTREG(R5XX_DP_GUI_MASTER_CNTL,
             RADEON_GMC_DST_PITCH_OFFSET_CNTL  |
@@ -53,7 +52,7 @@ int ClearPixmap(io_clear_t *io)
 
 #endif
 
-     safe_sti(ifl);
+     unlock_device();
 
      return ERR_OK;
 }
@@ -80,14 +79,13 @@ int Line(io_draw_t *draw)
 
     if ( !LineClip(&clip, &x0, &y0, &x1, &y1 ))
     {
-        u32_t ifl;
         u32_t *ring, write;
 
-        ifl = safe_cli();
+        lock_device();
 
 #if R300_PIO
 
-        R5xxFIFOWait(6);
+        FIFOWait(6);
 
         OUTREG(R5XX_DP_GUI_MASTER_CNTL,
                RADEON_GMC_DST_PITCH_OFFSET_CNTL  |
@@ -124,7 +122,8 @@ int Line(io_draw_t *draw)
          OUT_RING((y1<<16)|x1);
        COMMIT_RING();
 #endif
-        safe_sti(ifl);
+
+        unlock_device();
     };
     return ERR_OK;
 }
@@ -156,17 +155,16 @@ int DrawRect(io_draw_t* draw)
     if( ! BlockClip( &dst_clip, &x0, &y0, &x1, &y1))
     {
         u32_t *ring;
-        u32_t ifl;
         int w, h;
 
         w = x1 - x0 + 1;
         h = y1 - y0 + 1;
 
-        ifl = safe_cli();
+        lock_device();
 
 #if R300_PIO
 
-        R5xxFIFOWait(6);
+        FIFOWait(7);
 
         OUTREG(R5XX_DP_GUI_MASTER_CNTL,
                RADEON_GMC_DST_PITCH_OFFSET_CNTL  |
@@ -190,7 +188,7 @@ int DrawRect(io_draw_t* draw)
 
             if( y0 == draw->y0)
             {
-              R5xxFIFOWait(2);
+                FIFOWait(2);
 
                 OUTREG(R5XX_DST_Y_X,(y0<<16)|x0);
                 OUTREG(R5XX_DST_WIDTH_HEIGHT,(w<<16)|1);
@@ -199,7 +197,7 @@ int DrawRect(io_draw_t* draw)
             }
             if( y1 == yend )
             {
-              R5xxFIFOWait(2);
+                FIFOWait(2);
 
                 OUTREG(R5XX_DST_Y_X,(y1<<16)|x0);
                 OUTREG(R5XX_DST_WIDTH_HEIGHT,(w<<16)|1);
@@ -207,14 +205,14 @@ int DrawRect(io_draw_t* draw)
             }
             if( (h > 0) && (x0 == draw->x0))
             {
-              R5xxFIFOWait(2);
+                FIFOWait(2);
 
                 OUTREG(R5XX_DST_Y_X,(y0<<16)|x0);
                 OUTREG(R5XX_DST_WIDTH_HEIGHT,(1<<16)|h);
             }
             if( (h > 0) && (x1 == xend))
             {
-              R5xxFIFOWait(2);
+                FIFOWait(2);
 
                 OUTREG(R5XX_DST_Y_X,(y0<<16)|x1);
                 OUTREG(R5XX_DST_WIDTH_HEIGHT,(1<<16)|h);
@@ -282,7 +280,6 @@ int DrawRect(io_draw_t* draw)
                 OUT_RING((w<<16)|1);
                 OUT_RING(CP_PACKET2());
                 OUT_RING(CP_PACKET2());
-
             //  h--;
             }
             if( (h > 0) && (x0 == draw->x0)) {
@@ -302,7 +299,6 @@ int DrawRect(io_draw_t* draw)
                 OUT_RING((1<<16)|h);
                 OUT_RING(CP_PACKET2());
                 OUT_RING(CP_PACKET2());
-
             }
             if( (h > 0) && (x1 == xend)) {
                 OUT_RING(CP_PACKET3(RADEON_CNTL_PAINT_MULTI, 4));
@@ -321,7 +317,6 @@ int DrawRect(io_draw_t* draw)
                 OUT_RING((1<<16)|h);
                 OUT_RING(CP_PACKET2());
                 OUT_RING(CP_PACKET2());
-
             }
         };
 
@@ -383,7 +378,7 @@ int DrawRect(io_draw_t* draw)
 
       COMMIT_RING();
 #endif
-        safe_sti(ifl);
+        unlock_device();
     };
     return ERR_OK;
 }
@@ -413,16 +408,15 @@ int FillRect(io_fill_t *fill)
     if( ! BlockClip(&dst_clip, &x0, &y0, &x1, &y1))
     {
         u32_t *ring, write;
-        u32_t ifl;
 
         int w = x1 - x0 + 1;
         int h = y1 - y0 + 1;
 
-        ifl = safe_cli();
+        lock_device();
 
 #if R300_PIO
 
-        R5xxFIFOWait(9);
+        FIFOWait(9);
 
         OUTREG(R5XX_DP_GUI_MASTER_CNTL,
                RADEON_GMC_DST_PITCH_OFFSET_CNTL |
@@ -448,7 +442,7 @@ int FillRect(io_fill_t *fill)
 
         if( (fill->border & 0xFF000000) != 0)
         {
-           R5xxFIFOWait(2);
+            FIFOWait(2);
 
             OUTREG(R5XX_DP_GUI_MASTER_CNTL,
                    RADEON_GMC_DST_PITCH_OFFSET_CNTL  |
@@ -464,7 +458,7 @@ int FillRect(io_fill_t *fill)
 
             if( y0 == fill->y)
             {
-              R5xxFIFOWait(2);
+                FIFOWait(2);
 
                 OUTREG(R5XX_DST_Y_X,(y0<<16)|x0);
                 OUTREG(R5XX_DST_WIDTH_HEIGHT,(w<<16)|1);
@@ -473,7 +467,7 @@ int FillRect(io_fill_t *fill)
             }
             if( y1 == yend )
             {
-              R5xxFIFOWait(2);
+                FIFOWait(2);
 
                 OUTREG(R5XX_DST_Y_X,(y1<<16)|x0);
                 OUTREG(R5XX_DST_WIDTH_HEIGHT,(w<<16)|1);
@@ -481,14 +475,14 @@ int FillRect(io_fill_t *fill)
             }
             if( (h > 0) && (x0 == fill->x))
             {
-              R5xxFIFOWait(2);
+                FIFOWait(2);
 
                 OUTREG(R5XX_DST_Y_X,(y0<<16)|x0);
                 OUTREG(R5XX_DST_WIDTH_HEIGHT,(1<<16)|h);
             }
             if( (h > 0) && (x1 == xend))
             {
-              R5xxFIFOWait(2);
+                FIFOWait(2);
 
                 OUTREG(R5XX_DST_Y_X,(y0<<16)|x1);
                 OUTREG(R5XX_DST_WIDTH_HEIGHT,(1<<16)|h);
@@ -561,7 +555,7 @@ int FillRect(io_fill_t *fill)
       COMMIT_RING();
 
 #endif
-        safe_sti(ifl);
+        unlock_device();
      };
      return ERR_OK;
 };
@@ -574,11 +568,10 @@ static int blit_host(u32_t dstpitch, int dstx, int dsty,
                      u32_t  src, int srcx, int srcy,
                      int w, int h, int srcpitch, Bool trans, color_t key)
 {
-    u32_t     ifl;
     u32_t     dp_cntl;
     color_t  *src_addr;
 
-    ifl = safe_cli();
+    lock_device();
 
 #if R300_PIO
 
@@ -593,10 +586,10 @@ static int blit_host(u32_t dstpitch, int dstx, int dsty,
     if( trans == FALSE )
     {
         dp_cntl|= R5XX_GMC_CLR_CMP_CNTL_DIS;
-        R5xxFIFOWait(5);
+        FIFOWait(5);
     }
     else
-        R5xxFIFOWait(8);
+        FIFOWait(8);
 
     OUTREG(R5XX_DP_GUI_MASTER_CNTL, dp_cntl);
 
@@ -659,7 +652,7 @@ static int blit_host(u32_t dstpitch, int dstx, int dsty,
 
 #endif
 
-    safe_sti(ifl);
+    unlock_device();
 
     return ERR_OK;
 }
@@ -673,6 +666,7 @@ int Blit(io_blit_t *blit)
     local_pixmap_t *dstpixmap;
 
     u32_t  srcpitchoffset;
+    Bool   need_sync = FALSE;
 
     dstpixmap = (blit->dstpix == (void*)-1) ? &scr_pixmap : blit->dstpix ;
     srcpixmap = (blit->srcpix == (void*)-1) ? &scr_pixmap : blit->srcpix ;
@@ -692,7 +686,6 @@ int Blit(io_blit_t *blit)
                    &blit->w, &blit->h) )
     {
         u32_t *ring, write;
-        u32_t ifl;
 /*
         if( (srcpixmap->flags & PX_MEM_MASK)==PX_MEM_SYSTEM)
             return blit_host(dstpixmap->pitch_offset,
@@ -704,16 +697,19 @@ int Blit(io_blit_t *blit)
                              FALSE, 0 );
 */
 
-        if( (srcpixmap->flags & PX_MEM_MASK)==PX_MEM_SYSTEM)
+//        if( (srcpixmap->flags & PX_MEM_MASK)==PX_MEM_SYSTEM)
-            srcpitchoffset =  bind_pixmap(srcpixmap);
+//        {
-        else
+//            srcpitchoffset =  bind_pixmap(srcpixmap);
+//            need_sync = TRUE;
+//        }
+//        else
             srcpitchoffset = srcpixmap->pitch_offset;
 
-        ifl = safe_cli();
+        lock_device();
 
 #if R300_PIO
 
-        R5xxFIFOWait(7);
+        FIFOWait(7);
 
         OUTREG(R5XX_DP_GUI_MASTER_CNTL,
                RADEON_GMC_SRC_PITCH_OFFSET_CNTL  |
@@ -761,16 +757,17 @@ int Blit(io_blit_t *blit)
     COMMIT_RING();
 
 #endif
-        safe_sti(ifl);
 
-       if( (srcpixmap->flags & PX_MEM_MASK)==PX_MEM_SYSTEM)
+       if( need_sync == TRUE )
             R5xx2DIdleLocal();
+
+        unlock_device();
+
      };
      return ERR_OK;
 };
 
 
-
 int BlitTransparent(io_blit_t *blit)
 {
      clip_t src_clip, dst_clip;
@@ -779,6 +776,7 @@ int BlitTransparent(io_blit_t *blit)
      local_pixmap_t *dstpixmap;
 
      u32_t  srcpitchoffset;
+     Bool   need_sync = FALSE;
 
     // dbgprintf("Transblit src: %x dst: %x\n",blit->srcpix, blit->dstpix);
 
@@ -806,19 +804,21 @@ int BlitTransparent(io_blit_t *blit)
                     &blit->w, &blit->h) )
      {
         u32_t *ring, write;
-        u32_t  ifl;
 
 
-        if( (srcpixmap->flags & PX_MEM_MASK)==PX_MEM_SYSTEM)
+//        if( (srcpixmap->flags & PX_MEM_MASK)==PX_MEM_SYSTEM)
-            srcpitchoffset =  bind_pixmap(srcpixmap);
+//        {
-        else
+//            srcpitchoffset =  bind_pixmap(srcpixmap);
+//            need_sync = TRUE;
+//        }
+//        else
             srcpitchoffset = srcpixmap->pitch_offset;
 
-        ifl = safe_cli();
+        lock_device();
 
 #if R300_PIO
 
-        R5xxFIFOWait(10);
+        FIFOWait(10);
 
         OUTREG(R5XX_DP_GUI_MASTER_CNTL,
                RADEON_GMC_SRC_PITCH_OFFSET_CNTL  |
@@ -875,11 +875,12 @@ int BlitTransparent(io_blit_t *blit)
 
 #endif
 
-       safe_sti(ifl);
+       if( need_sync == TRUE )
-
-       if( (srcpixmap->flags & PX_MEM_MASK)==PX_MEM_SYSTEM)
             R5xx2DIdleLocal();
 
+       unlock_device();
+
+
      };
      return ERR_OK;
 }

drivers/video/ati2d/ati2d.c

@@ -1,6 +1,6 @@
 
 
-#define R300_PIO        1
+#define R300_PIO        0
 
 
 #define API_VERSION     0x01000100
@@ -60,6 +60,9 @@ u32_t __stdcall drvEntry(int action)
         return 0;
     };
 
+    dbgprintf("detect %s GART\n",
+               rhd.gart_type == RADEON_IS_PCIE ? "PCIE":"PCI");
+
     for(i=0;i<6;i++)
     {
         if(rhd.memBase[i])
@@ -77,12 +80,8 @@ u32_t __stdcall drvEntry(int action)
 
     R5xx2DInit();
 
-#if !R300_PIO
-
     Init3DEngine(&rhd);
 
-#endif
-
     retval = RegService("HDRAW", srv_2d);
     dbgprintf("reg service %s as: %x\n", "HDRAW", retval);
 
@@ -148,13 +147,10 @@ int __stdcall srv_2d(ioctl_t *io)
                 return BlitTransparent((io_blit_t*)inp);
             break;
 
-#if !R300_PIO
-
         case PX_BLIT_ALPHA:
             if(io->inp_size==9)
                 return RadeonComposite((io_blit_t*)inp);
             break;
-#endif
 
         default:
             return ERR_PARAM;
@@ -168,18 +164,17 @@ int __stdcall srv_2d(ioctl_t *io)
 #include "pci.c"
 #include "ati_mem.c"
 
-#include "init_cp.c"
-
 #include "r500.inc"
 
 #include "clip.inc"
 #include "pixmap.inc"
 #include "accel_2d.inc"
+#include "init_3d.inc"
+#include "blend.inc"
 
 #if !R300_PIO
 
-#include "init_3d.inc"
+#include "init_cp.c"
-#include "blend.inc"
 
 #endif
 

drivers/video/ati2d/ati2d.lk

@@ -3,18 +3,21 @@ IMP
     _KernelFree        core.KernelFree,
     _UserAlloc         core.UserAlloc,
     _UserFree          core.UserFree,
+    _AllocPages        core.AllocPages,
     _CommitPages       core.CommitPages,
     _UnmapPages        core.UnmapPages,
-    _CreateObject      core.CreateObject,
-    _DestroyObject     core.DestroyObject,
     _MapIoMem          core.MapIoMem,
     _GetPgAddr         core.GetPgAddr,
     _CreateRingBuffer  core.CreateRingBuffer,
     _PciApi            core.PciApi,
     _PciRead8          core.PciRead8,
+    _PciRead16         core.PciRead16,
     _PciRead32         core.PciRead32,
     _PciWrite32        core.PciWrite32,
     _RegService        core.RegService,
+    _WaitMutex         core.WaitMutex,
+    _Delay             core.Delay,
+    _ChangeTask        core.ChangeTask,
     _SysMsgBoardStr    core.SysMsgBoardStr
 
 

drivers/video/ati2d/atihw.h

@@ -96,6 +96,21 @@ typedef enum {
 	CARD_PCIE
 } RADEONCardType;
 
+enum radeon_chip_flags {
+    RADEON_FAMILY_MASK  =  0x0000ffffUL,
+    RADEON_FLAGS_MASK   =  0xffff0000UL,
+    RADEON_IS_MOBILITY  =  0x00010000UL,
+    RADEON_IS_IGP       =  0x00020000UL,
+    RADEON_SINGLE_CRTC  =  0x00040000UL,
+    RADEON_IS_AGP       =  0x00080000UL,
+    RADEON_HAS_HIERZ    =  0x00100000UL,
+    RADEON_IS_PCIE      =  0x00200000UL,
+    RADEON_NEW_MEMMAP   =  0x00400000UL,
+    RADEON_IS_PCI       =  0x00800000UL,
+    RADEON_IS_IGPGART   =  0x01000000UL,
+};
+
+
 /*
  * Errata workarounds
  */
@@ -135,11 +150,17 @@ typedef struct
 
 #define RADEON_PCIGART_TABLE_SIZE      (32*1024)
 
+#define RADEON_IDLE_RETRY      16 /* Fall out of idle loops after this count */
+#define RADEON_TIMEOUT    4000000 /* Fall out of wait loops after this count */
+
+
 typedef struct RHDRec
 {
   addr_t            MMIOBase;
   size_t            MMIOMapSize;
 
+  u32_t             lock;
+
   addr_t            FbFreeStart;
   addr_t            FbFreeSize;
 
@@ -193,6 +214,7 @@ typedef struct RHDRec
   u32_t             displayWidth;
   u32_t             displayHeight;
 
+  u32_t             gart_type;
   u32_t            *gart_table;
   addr_t            gart_table_dma;
   addr_t            gart_vm_start;
@@ -239,7 +261,26 @@ typedef struct RHDRec
 
 extern RHD_t rhd;
 
+#define RADEON_CP_PACKET0              0x00000000
+#define RADEON_CP_PACKET1              0x40000000
+#define RADEON_CP_PACKET2              0x80000000
+#define RADEON_CP_PACKET3              0xC0000000
 
+# define RADEON_CNTL_PAINT             0x00009100
+# define RADEON_CNTL_BITBLT            0x00009200
+# define RADEON_CNTL_TRANBLT           0x00009C00
+
+# define RADEON_CNTL_PAINT_POLYLINE    0x00009500
+# define RADEON_CNTL_PAINT_MULTI       0x00009A00
+
+#if R300_PIO
+
+#define BEGIN_ACCEL(n)      FIFOWait(n)
+#define FINISH_ACCEL()
+#define COMMIT_RING()
+#define OUT_ACCEL_REG(reg, val) OUTREG(reg, val)
+
+#else
 
 #define CP_PACKET0(reg, n)            \
     (RADEON_CP_PACKET0 | ((n - 1 ) << 16) | ((reg) >> 2))
@@ -263,12 +304,12 @@ extern RHD_t rhd;
         avail = rhd.ring_rp-rhd.ring_wp;                           \
         if (avail <= 0) avail+= 0x4000;                            \
         if( (req)+128 > avail){                                    \
-           safe_sti(ifl);                                          \
+           unlock_device();                                        \
            return 0;                                               \
         };                                                         \
      }                                                             \
      ring = &rhd.ringBase[rhd.ring_wp];                            \
-}while(0);
+}while(0)
 
 #define ADVANCE_RING()
 
@@ -298,6 +339,7 @@ do {                                     \
 
 #define OUT_ACCEL_REG(reg, val) CP_REG((reg), (val))
 
+#endif
 
 typedef struct {
     int			token;		/* id of the token */
@@ -305,6 +347,17 @@ typedef struct {
 } SymTabRec, *SymTabPtr;
 
 
+extern inline void lock_device()
+{
+     __asm__ __volatile__ (
+     "call *__imp__WaitMutex"
+     ::"b" (&rhd.lock));
+};
+
+extern inline void unlock_device()
+{
+    rhd.lock = 0;
+}
 
 extern inline void
 OUTREG8(u16_t offset, u8_t value)
@@ -372,8 +425,6 @@ _RHDRegMask(RHDPtr rhdPtr, u16_t offset, u32_t value, u32_t mask)
 #define RHDRegMask(ptr, offset, value, mask) _RHDRegMask((ptr)->rhdPtr, (offset), (value), (mask))
 
 
-
-
 #define RHDFUNC(ptr)
 
 #define DBG(x) x
@@ -408,7 +459,6 @@ void __stdcall r500_SetCursor(cursor_t *cursor, int x, int y);
 void __stdcall r500_CursorRestore(int x, int y);
 
 
-
 typedef struct {
     u32_t x ;
     u32_t y ;
@@ -502,6 +552,10 @@ void dump_mem();
 
 RHDPtr  FindPciDevice();
 
+static __inline__ int drm_device_is_pcie(PCITAG pciTag);
+static void init_pipes(RHDPtr info);
+Bool   init_cp(RHDPtr info);
+
 Bool    RHDPreInit();
 
 void    R5xx2DInit();

drivers/video/ati2d/blend.inc

@@ -34,69 +34,11 @@ static struct blendinfo RadeonBlendOp[] = {
     {0, 0, RADEON_SRC_BLEND_GL_ONE                 | RADEON_DST_BLEND_GL_ONE},
 };
 
-static Bool R200PrepareComposite(local_pixmap_t *dstpix, int dstX, int dstY,
-                                 local_pixmap_t *srcpix, int srcX, int srcY,
-                                 int w, int h, int alpha)
-{
-    u32_t tex_size = 0, txformat, blend_cntl;
-    int dst_pitch;
-
-    if ((w > 2048) || (h > 2048))
-        return FALSE;
-
-    txformat = RADEON_TXFORMAT_ARGB8888      |
-               RADEON_TXFORMAT_ALPHA_IN_MAP  |
-               RADEON_TXFORMAT_NON_POWER2;
-
-    blend_cntl = RADEON_SRC_BLEND_GL_SRC_ALPHA |
-                 RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA;
-
-    tex_size = ((h - 1) << 16) | (w - 1);
-    {
-        u32_t *ring;
-        u32_t ifl  = safe_cli();
-
-        BEGIN_ACCEL(168);
-        OUT_ACCEL_REG(R200_PP_TXFORMAT_0, txformat);
-        OUT_ACCEL_REG(R200_PP_TXFORMAT_X_0, 0);
-        OUT_ACCEL_REG(R200_PP_TXSIZE_0, tex_size);
-        OUT_ACCEL_REG(R200_PP_TXPITCH_0, srcpix->pitch - 32);
-        OUT_ACCEL_REG(R200_PP_TXOFFSET_0, (u32_t)srcpix->local);
-        OUT_ACCEL_REG(R200_PP_TXFILTER_0, R200_MAG_FILTER_NEAREST |
-				      R200_MIN_FILTER_NEAREST |
-				      R200_CLAMP_S_WRAP |
-				      R200_CLAMP_T_WRAP);
-
-        OUT_ACCEL_REG(RADEON_RB3D_CNTL, RADEON_COLOR_FORMAT_ARGB8888 |
-                                        RADEON_ALPHA_BLEND_ENABLE);
-        OUT_ACCEL_REG(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE |
-                                      RADEON_TEX_BLEND_0_ENABLE);
-        OUT_ACCEL_REG(R200_PP_TFACTOR_0, alpha << 24);
-        OUT_ACCEL_REG(R200_PP_TXCBLEND_0, R200_TXC_ARG_A_TFACTOR_COLOR |
-                                          R200_TXC_ARG_B_R0_ALPHA);
-        OUT_ACCEL_REG(R200_PP_TXCBLEND2_0,R200_TXC_OUTPUT_REG_R0);
-        OUT_ACCEL_REG(R200_PP_TXABLEND_0, R200_TXA_ARG_A_TFACTOR_ALPHA |
-                                          R200_TXA_ARG_B_R0_ALPHA);
-        OUT_ACCEL_REG(R200_PP_TXABLEND2_0, R200_TXA_OUTPUT_REG_R0);
-        OUT_ACCEL_REG(R200_SE_VTX_FMT_0, 0);
-        OUT_ACCEL_REG(R200_SE_VTX_FMT_1, (2 << R200_VTX_TEX0_COMP_CNT_SHIFT));
-        OUT_ACCEL_REG(RADEON_RB3D_BLENDCNTL, blend_cntl);
-
-        OUT_ACCEL_REG(RADEON_RB3D_COLORPITCH, dstpix->pitch >> 2);
-        OUT_ACCEL_REG(RADEON_RB3D_COLOROFFSET, (u32_t)dstpix->local);
-
-        COMMIT_RING();
-        safe_sti(ifl);
-    };
-
-    return TRUE;
-}
 
 static Bool R300TextureSetup(RHDPtr info,local_pixmap_t *srcpix, int w, int h, int unit)
 {
     u32_t txfilter, txformat0, txformat1, txoffset, txpitch;
- //   int w = pPict->pDrawable->width;
+
- //   int h = pPict->pDrawable->height;
     int i, pixel_shift;
 
 
@@ -113,17 +55,6 @@ static Bool R300TextureSetup(RHDPtr info,local_pixmap_t *srcpix, int w, int h, i
     txpitch >>= pixel_shift;
     txpitch -= 1;
 
-  //  if (RADEONPixmapIsColortiled(pPix))
-  //      txoffset |= R300_MACRO_TILE;
-
- //   for (i = 0; i < sizeof(R300TexFormats) / sizeof(R300TexFormats[0]); i++)
- //   {
- //       if (R300TexFormats[i].fmt == pPict->format)
- //           break;
- //   }
-
-    //txformat1 = R300TexFormats[i].card_fmt;
-
     txformat1 = R300_TX_FORMAT_A8R8G8B8;
 
     txformat0 = ((((w - 1) & 0x7ff) << R300_TXWIDTH_SHIFT) |
@@ -141,35 +72,17 @@ static Bool R300TextureSetup(RHDPtr info,local_pixmap_t *srcpix, int w, int h, i
      */
     txformat0 |= R300_TXPITCH_EN;
 
-  //  info->texW[unit] = w;
-  //  info->texH[unit] = h;
-
-  //  if (pPict->repeat && !(unit == 0 && need_src_tile_x))
-  //    txfilter = R300_TX_CLAMP_S(R300_TX_CLAMP_WRAP);
-  //  else
     txfilter = R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_GL);
 
-  //  if (pPict->repeat && !(unit == 0 && need_src_tile_y))
-  //    txfilter |= R300_TX_CLAMP_T(R300_TX_CLAMP_WRAP);
-  //  else
     txfilter |= R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_GL);
 
     txfilter |= (unit << R300_TX_ID_SHIFT);
 
-//    switch (pPict->filter) {
-//    case PictFilterNearest:
 	txfilter |= (R300_TX_MAG_FILTER_NEAREST | R300_TX_MIN_FILTER_NEAREST);
-//        break;
+
-//    case PictFilterBilinear:
-//        txfilter |= (R300_TX_MAG_FILTER_LINEAR | R300_TX_MIN_FILTER_LINEAR);
-//        break;
-//    default:
-//        RADEON_FALLBACK(("Bad filter 0x%x\n", pPict->filter));
-//    }
 
     {
         u32_t *ring;
-        u32_t ifl  = safe_cli();
 
         BEGIN_ACCEL(7);
 
@@ -183,14 +96,7 @@ static Bool R300TextureSetup(RHDPtr info,local_pixmap_t *srcpix, int w, int h, i
         OUT_ACCEL_REG(R300_TX_BORDER_COLOR_0 + (unit * 4), 0);
 
         COMMIT_RING();
-        safe_sti(ifl);
     }
-//    if (pPict->transform != 0) {
-//        is_transform[unit] = TRUE;
-//        transform[unit] = pPict->transform;
-//    } else {
-//        is_transform[unit] = FALSE;
-//    }
 
     return TRUE;
 }
@@ -199,20 +105,6 @@ static u32_t RADEONGetBlendCntl(int op, u32_t dst_format)
 {
     u32_t sblend, dblend;
 
-   // sblend = RadeonBlendOp[op].blend_cntl & RADEON_SRC_BLEND_MASK;
-   // dblend = RadeonBlendOp[op].blend_cntl & RADEON_DST_BLEND_MASK;
-
-    /* If there's no dst alpha channel, adjust the blend op so that we'll treat
-     * it as always 1.
-     */
-  //  if ( RadeonBlendOp[op].dst_alpha) {
-  //      if (sblend == RADEON_SRC_BLEND_GL_DST_ALPHA)
-  //          sblend = RADEON_SRC_BLEND_GL_ONE;
-  //      else if (sblend == RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA)
-  //          sblend = RADEON_SRC_BLEND_GL_ZERO;
-  //  }
-
-    //return sblend | dblend;
 
     return RADEON_SRC_BLEND_GL_SRC_ALPHA | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA;
 }
@@ -222,15 +114,12 @@ Bool R300PrepareComposite(local_pixmap_t *dstpix, int dstX, int dstY,
                           local_pixmap_t *srcpix, int srcX, int srcY,
                           int w, int h, int op)
 {
-  //  RINFO_FROM_SCREEN(pDst->drawable.pScreen);
     u32_t dst_format, dst_offset, dst_pitch;
     u32_t txenable, colorpitch;
     u32_t blendcntl;
     int pixel_shift;
     u32_t *ring;
 
-    u32_t ifl;
-
     RHDPtr info = &rhd;
 
     dst_format = R300_COLORFORMAT_ARGB8888;
@@ -243,9 +132,6 @@ Bool R300PrepareComposite(local_pixmap_t *dstpix, int dstX, int dstY,
 
     colorpitch = dst_pitch >> pixel_shift;
 
-  //  if (RADEONPixmapIsColortiled(pDst))
-  //      colorpitch |= R300_COLORTILE;
-
     colorpitch |= dst_format;
 
     if ((dst_offset & 0x0f) != 0)
@@ -253,8 +139,6 @@ Bool R300PrepareComposite(local_pixmap_t *dstpix, int dstX, int dstY,
     if (((dst_pitch >> pixel_shift) & 0x7) != 0)
         dbgprintf("Bad destination pitch 0x%x\n", (int)dst_pitch);
 
-  //  if (!RADEONSetupSourceTile(pSrcPicture, pSrc, TRUE, FALSE))
-  //      return FALSE;
 
     if (!R300TextureSetup(&rhd, srcpix, w, h, 0))
 	return FALSE;
@@ -265,12 +149,7 @@ Bool R300PrepareComposite(local_pixmap_t *dstpix, int dstX, int dstY,
 
     /* setup the VAP */
 
-    ifl = safe_cli();
+    BEGIN_ACCEL(7);
-
-    BEGIN_RING(32*2);
-
-    OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_HOST_IDLECLEAN |
-                                     RADEON_WAIT_3D_IDLECLEAN);
 
     /* These registers define the number, type, and location of data submitted
      * to the PVS unit of GA input (when PVS is disabled)
@@ -373,7 +252,7 @@ Bool R300PrepareComposite(local_pixmap_t *dstpix, int dstX, int dstY,
                R300_TEX_SIZE(0)  |
 			   R300_RGBA_OUT));
 
-        OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* highest temp used */
+//        OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* highest temp used */
 	/* shader output swizzling */
         OUT_ACCEL_REG(R300_US_OUT_FMT_0, output_fmt);
 
@@ -445,18 +324,10 @@ Bool R300PrepareComposite(local_pixmap_t *dstpix, int dstX, int dstY,
         u32_t src_color, src_alpha;
         u32_t mask_color, mask_alpha;
 
-//        if (PICT_FORMAT_RGB(PICT_a8r8g8b8) == 0)
-//            src_color = (R500_ALU_RGB_R_SWIZ_A_0 |
-//                         R500_ALU_RGB_G_SWIZ_A_0 |
-//                         R500_ALU_RGB_B_SWIZ_A_0);
-//        else
 	    src_color = (R500_ALU_RGB_R_SWIZ_A_R |
                      R500_ALU_RGB_G_SWIZ_A_G |
                      R500_ALU_RGB_B_SWIZ_A_B);
 
-//        if (PICT_FORMAT_A(PICT_a8r8g8b8) == 0)
-//            src_alpha = R500_ALPHA_SWIZ_A_1;
-//        else
 	    src_alpha = R500_ALPHA_SWIZ_A_A;
 
         mask_color = (R500_ALU_RGB_R_SWIZ_B_1 |
@@ -588,8 +459,6 @@ Bool R300PrepareComposite(local_pixmap_t *dstpix, int dstX, int dstY,
 
     FINISH_ACCEL();
 
-    safe_sti(ifl);
-
     return TRUE;
 }
 
@@ -601,11 +470,25 @@ static __inline__ u32_t F_TO_DW(float val)
     union {
       float f;
       u32_t l;
-    } tmp;
+    }tmp;
     tmp.f = val;
     return tmp.l;
 }
 
+#if R300_PIO
+
+#define OUT_ACCEL_REG_F(reg, val) OUTREG(reg, F_TO_DW(val))
+
+#define VTX_OUT(_dstX, _dstY, _srcX, _srcY) \
+do {								\
+    OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _dstX);		\
+    OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _dstY);		\
+    OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _srcX);		\
+    OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _srcY);		\
+} while (0)
+
+#else
+
 #define OUT_RING_F(x) OUT_RING(F_TO_DW(x))
 
 #define VTX_OUT(_dstX, _dstY, _srcX, _srcY)     \
@@ -616,28 +499,20 @@ do {                                            \
     OUT_RING_F(_srcY);                          \
 } while (0)
 
-
+#endif
 
 static int R300CompositeTile(int srcX, int srcY,
                                 int dstX, int dstY,
                                 int w, int h)
 {
-  //  RINFO_FROM_SCREEN(pDst->drawable.pScreen);
     int vtx_count;
     xPointFixed srcTopLeft, srcTopRight, srcBottomLeft, srcBottomRight;
     xPointFixed maskTopLeft, maskTopRight, maskBottomLeft, maskBottomRight;
 
+    RHDPtr info = &rhd;
+
     u32_t *ring;
 
-    u32_t ifl;
-
- //   ACCEL_PREAMBLE();
-
- //   ENTER_DRAW(0);
-
-    /* ErrorF("RadeonComposite (%d,%d) (%d,%d) (%d,%d) (%d,%d)\n",
-       srcX, srcY, maskX, maskY,dstX, dstY, w, h); */
-
     srcTopLeft.x     = IntToxFixed(srcX);
     srcTopLeft.y     = IntToxFixed(srcY);
     srcTopRight.x    = IntToxFixed(srcX + w);
@@ -647,27 +522,19 @@ static int R300CompositeTile(int srcX, int srcY,
     srcBottomRight.x = IntToxFixed(srcX + w);
     srcBottomRight.y = IntToxFixed(srcY + h);
 
-/*
-    if (is_transform[0]) {
-	transformPoint(transform[0], &srcTopLeft);
-	transformPoint(transform[0], &srcTopRight);
-	transformPoint(transform[0], &srcBottomLeft);
-	transformPoint(transform[0], &srcBottomRight);
-    }
-    if (is_transform[1]) {
-	transformPoint(transform[1], &maskTopLeft);
-	transformPoint(transform[1], &maskTopRight);
-	transformPoint(transform[1], &maskBottomLeft);
-	transformPoint(transform[1], &maskBottomRight);
-    }
-*/
     vtx_count = VTX_COUNT;
 
+#if R300_PIO
 
-    ifl = safe_cli();
+    BEGIN_ACCEL(6 + vtx_count * 4);
-
+    OUT_ACCEL_REG(R300_VAP_VTX_SIZE, vtx_count);
-    BEGIN_RING(7 + 4 * vtx_count);
+    OUT_ACCEL_REG(RADEON_SE_VF_CNTL,
+                  (RADEON_VF_PRIM_TYPE_QUAD_LIST |
+                   RADEON_VF_PRIM_WALK_DATA |
+                   (4 << RADEON_VF_NUM_VERTICES_SHIFT)));
 
+#else
+    BEGIN_ACCEL(7 + 4 * vtx_count);
     OUT_ACCEL_REG(R300_VAP_VTX_SIZE, vtx_count);
 
     OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2,
@@ -676,6 +543,7 @@ static int R300CompositeTile(int srcX, int srcY,
               RADEON_CP_VC_CNTL_PRIM_WALK_RING |
               (4 << RADEON_CP_VC_CNTL_NUM_SHIFT));
 
+#endif
 
       VTX_OUT((float)dstX, (float)dstY,
               xFixedToFloat(srcTopLeft.x) / w,      // info->texW[0],
@@ -695,67 +563,13 @@ static int R300CompositeTile(int srcX, int srcY,
 
           /* flushing is pipelined, free/finish is not */
       OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D);
-
+      OUT_ACCEL_REG(R300_SC_CLIP_RULE, 0xAAAA);
- //     OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
+      OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DC_FLUSH_ALL);
-
-    COMMIT_RING();
-
-    safe_sti(ifl);
-
- //   LEAVE_DRAW(0);
-}
-
-
-static int R200CompositeTile(int srcX, int srcY,
-                             int dstX, int dstY,
-                             int w, int h)
-{
-    xPointFixed srcTopLeft, srcTopRight, srcBottomLeft, srcBottomRight;
-    xPointFixed maskTopLeft, maskTopRight, maskBottomLeft, maskBottomRight;
-
-    srcTopLeft.x     = IntToxFixed(srcX);
-    srcTopLeft.y     = IntToxFixed(srcY);
-    srcTopRight.x    = IntToxFixed(srcX + w);
-    srcTopRight.y    = IntToxFixed(srcY);
-    srcBottomLeft.x  = IntToxFixed(srcX);
-    srcBottomLeft.y  = IntToxFixed(srcY + h);
-    srcBottomRight.x = IntToxFixed(srcX + w);
-    srcBottomRight.y = IntToxFixed(srcY + h);
-
-    {
-        u32_t *ring;
-        u32_t  ifl = safe_cli();
-
-        BEGIN_RING(4 + 4 * VTX_COUNT);
-
-        OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2, 4 * VTX_COUNT));
-        OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN |
-                 RADEON_CP_VC_CNTL_PRIM_WALK_RING |
-                (4 << RADEON_CP_VC_CNTL_NUM_SHIFT));
-
-
-        VTX_OUT((float)dstX, (float)dstY,
-              xFixedToFloat(srcTopLeft.x) / w,      // info->texW[0],
-              xFixedToFloat(srcTopLeft.y) / h);     // info->texH[0]);
-
-        VTX_OUT((float)dstX, (float)(dstY + h),
-              xFixedToFloat(srcBottomLeft.x) / w,   // info->texW[0],
-              xFixedToFloat(srcBottomLeft.y) / h);  // info->texH[0]);
-
-        VTX_OUT((float)(dstX + w), (float)(dstY + h),
-              xFixedToFloat(srcBottomRight.x) / w,  // info->texW[0],
-              xFixedToFloat(srcBottomRight.y) / h); // info->texH[0]);
-
-        VTX_OUT((float)(dstX + w), (float)dstY,
-              xFixedToFloat(srcTopRight.x) / w,     // info->texW[0],
-              xFixedToFloat(srcTopRight.y) / h);    // info->texH[0]);
-
       OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
 
     COMMIT_RING();
-        safe_sti(ifl);
+}
-    };
+
-};
 
 #undef VTX_OUT
 #undef VTX_OUT_MASK
@@ -774,10 +588,39 @@ int RadeonComposite( io_blit_t *blit)
     dstpixmap = (blit->dstpix == (void*)-1) ? &scr_pixmap : blit->dstpix ;
     srcpixmap = (blit->srcpix == (void*)-1) ? &scr_pixmap : blit->srcpix ;
 
+    lock_device();
+
     {
         u32_t *ring;
-        u32_t ifl = safe_cli();
 
+#if R300_PIO
+
+        FIFOWait(10);
+
+        OUTREG(R5XX_DP_GUI_MASTER_CNTL,
+            RADEON_GMC_DST_PITCH_OFFSET_CNTL  |
+            RADEON_GMC_BRUSH_SOLID_COLOR      |
+            RADEON_GMC_DST_32BPP              |
+            RADEON_GMC_SRC_DATATYPE_COLOR     |
+            R5XX_GMC_CLR_CMP_CNTL_DIS         |
+            R5XX_ROP3_P
+           );
+
+        OUTREG(R5XX_DST_PITCH_OFFSET, srcpixmap->pitch_offset);
+        OUTREG(R5XX_DP_BRUSH_FRGD_CLR, blit->alpha<<24);
+        OUTREG(R5XX_DP_WRITE_MASK, 0xFF000000);
+        OUTREG(R5XX_DP_CNTL, R5XX_DST_X_LEFT_TO_RIGHT | R5XX_DST_Y_TOP_TO_BOTTOM);
+        OUTREG(R5XX_DST_Y_X, 0);
+        OUTREG(R5XX_DST_WIDTH_HEIGHT,(srcpixmap->width<<16)|srcpixmap->height);
+
+        OUTREG( RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN
+                                  | RADEON_WAIT_HOST_IDLECLEAN );
+
+        OUTREG(R5XX_DP_WRITE_MASK, 0xFFFFFFFF);
+        OUTREG(RADEON_WAIT_UNTIL, RADEON_WAIT_HOST_IDLECLEAN |
+                                  RADEON_WAIT_2D_IDLECLEAN);
+
+#else
         BEGIN_RING(2 + 6);
 
         CP_REG(R5XX_DP_WRITE_MASK, 0xFF000000);
@@ -798,16 +641,18 @@ int RadeonComposite( io_blit_t *blit)
         OUT_RING((srcpixmap->width<<16)|srcpixmap->height);
 
         COMMIT_RING();
-
+#endif
         RHDPtr info = &rhd;
 
+        FIFOWait(64);
+        delay(2);
+
         if( IS_R300_3D || IS_R500_3D )
         {
             R300PrepareComposite(dstpixmap, blit->dst_x, blit->dst_y,
                                  srcpixmap, blit->src_x, blit->src_y,
                                  blit->w, blit->h, 3);
 
-//    if (!need_src_tile_x && !need_src_tile_y) {
             R300CompositeTile( blit->src_x, blit->src_y,
                                blit->dst_x, blit->dst_y,
                                blit->w, blit->h);
@@ -817,64 +662,16 @@ int RadeonComposite( io_blit_t *blit)
                  (info->ChipFamily == CHIP_FAMILY_RS300) ||
                  (info->ChipFamily == CHIP_FAMILY_R200))
         {
-            R200PrepareComposite(dstpixmap, blit->dst_x, blit->dst_y,
-                                 srcpixmap, blit->src_x, blit->src_y,
-                                 blit->w, blit->h, blit->alpha);
-            R200CompositeTile( blit->src_x, blit->src_y,
-                               blit->dst_x, blit->dst_y,
-                               blit->w, blit->h);
         };
 
-
-        safe_sti(ifl);
     };
 
+    FIFOWait(64);
+    delay(2);
 
+    unlock_device();
 
     return 0;
-  //  }
+};
 
-    /* Tiling logic borrowed from exaFillRegionTiled */
 
-#if 0
-    modulus(srcY, src_tile_height, tileSrcY);
-    tileMaskY = maskY;
-    tileDstY = dstY;
-
-    remainingHeight = height;
-    while (remainingHeight > 0) {
-	int remainingWidth = width;
-	int tileSrcX, tileMaskX, tileDstX;
-	int h = src_tile_height - tileSrcY;
-
-	if (h > remainingHeight)
-	    h = remainingHeight;
-	remainingHeight -= h;
-
-	modulus(srcX, src_tile_width, tileSrcX);
-	tileMaskX = maskX;
-	tileDstX = dstX;
-
-	while (remainingWidth > 0) {
-	    int w = src_tile_width - tileSrcX;
-	    if (w > remainingWidth)
-		w = remainingWidth;
-	    remainingWidth -= w;
-
-	    FUNC_NAME(RadeonCompositeTile)(pDst,
-					   tileSrcX, tileSrcY,
-					   tileMaskX, tileMaskY,
-					   tileDstX, tileDstY,
-					   w, h);
-
-	    tileSrcX = 0;
-	    tileMaskX += w;
-	    tileDstX += w;
-	}
-	tileSrcY = 0;
-	tileMaskY += h;
-	tileDstY += h;
-    }
-#endif
-
-}

drivers/video/ati2d/init.c

@@ -971,7 +971,6 @@ Bool RHDPreInit()
         return FALSE;
     };
 
-
     if( !RADEONPreInitChipType(&rhd))
        return FALSE;
 
@@ -987,6 +986,9 @@ Bool RHDPreInit()
     }
     dbgprintf("VideoRAM: %d kByte\n",rhd.videoRam);
 
+ /* setup the raster pipes */
+    init_pipes(&rhd);
+
     init_gart(&rhd);
 
     rhd.FbFreeSize = rhd.videoRam << 10;
@@ -1225,23 +1227,27 @@ void init_gart(RHDPtr info)
 
     info->gart_vm_start = info->fbLocation + (info->videoRam << 10);
 
-//    info->gart_vm_start = info->fbLocation - info->gart_size;
 
-//    info->gart_table = (u32_t*)KernelAlloc( RADEON_PCIGART_TABLE_SIZE );
+    if( info->gart_type == RADEON_IS_PCIE)
+        info->gart_table_dma = info->gart_vm_start
+                               - RADEON_PCIGART_TABLE_SIZE;
+    else
+        info->gart_table_dma = AllocPages(RADEON_PCIGART_TABLE_SIZE >> 12);
 
-//    if ( ! info->gart_table) {
+    if ( ! info->gart_table_dma) {
-//        dbgprintf("cannot allocate PCI GART page!\n");
+        dbgprintf("cannot allocate PCI GART page!\n");
-//        return;
+        return;
-//    }
+    }
-
-//    info->gart_table_dma = GetPgAddr(info->gart_table);
-
-    info->gart_table_dma = info->gart_vm_start - RADEON_PCIGART_TABLE_SIZE;
 
     info->gart_table = (u32_t*)MapIoMem(info->gart_table_dma,
                                         RADEON_PCIGART_TABLE_SIZE,
                                         PG_SW | PG_NOCACHE);
 
+    if ( ! info->gart_table) {
+        dbgprintf("cannot map PCI GART page!\n");
+        return;
+    }
+
     pci_gart = info->gart_table;
 
     memset(pci_gart, 0, RADEON_PCIGART_TABLE_SIZE);
@@ -1250,7 +1256,10 @@ void init_gart(RHDPtr info)
     "wbinvd"
     :::"memory");
 
+    if( info->gart_type == RADEON_IS_PCIE)
         radeon_set_pciegart(info, 1);
+    else
+        radeon_set_pcigart(info, 1);
 
     dbgprintf("gart size 0x%x\n", info->gart_size);
     dbgprintf("gart base 0x%x\n", info->gart_vm_start);

drivers/video/ati2d/init_3d.inc

@@ -1,3 +1,30 @@
+/*
+ * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
+ *                VA Linux Systems Inc., Fremont, California.
+ *
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation on the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial
+ * portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT.  IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
+ * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
 
 
 int Init3DEngine(RHDPtr info)
@@ -11,6 +38,9 @@ int Init3DEngine(RHDPtr info)
 
     ifl = safe_cli();
 
+    FIFOWait(64);
+    delay(2);
+
     if (IS_R300_3D || IS_R500_3D) {
 
 	BEGIN_ACCEL(3);
@@ -123,10 +153,9 @@ int Init3DEngine(RHDPtr info)
             vap_cntl |= (4 << R300_PVS_NUM_FPUS_SHIFT);
 
     if (info->has_tcl)
-        BEGIN_ACCEL(15)
+        BEGIN_ACCEL(15);
 	else
 	    BEGIN_ACCEL(9);
-
         OUT_ACCEL_REG(R300_VAP_VTX_STATE_CNTL, 0);
         OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0);
 
@@ -467,44 +496,9 @@ int Init3DEngine(RHDPtr info)
         }
 	FINISH_ACCEL();
 
-	/* pre-load FS tex instructions */
+	if (IS_R300_3D)
-        if (IS_R300_3D) {
+	    BEGIN_ACCEL(4);
-	    BEGIN_ACCEL(2);
+	else {
-	    /* tex inst for src texture */
-           OUT_ACCEL_REG(R300_US_TEX_INST_0,
-			  (R300_TEX_SRC_ADDR(0) |
-			   R300_TEX_DST_ADDR(0) |
-			   R300_TEX_ID(0) |
-			   R300_TEX_INST(R300_TEX_INST_LD)));
-
-	    /* tex inst for mask texture */
-          OUT_ACCEL_REG(R300_US_TEX_INST_1,
-			  (R300_TEX_SRC_ADDR(1) |
-			   R300_TEX_DST_ADDR(1) |
-			   R300_TEX_ID(1) |
-			   R300_TEX_INST(R300_TEX_INST_LD)));
-	    FINISH_ACCEL();
-        }
-
-	if (IS_R300_3D) {
-	    BEGIN_ACCEL(8);
-            OUT_ACCEL_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX);
-            OUT_ACCEL_REG(R300_US_CODE_ADDR_0,
-			  (R300_ALU_START(0) |
-			   R300_ALU_SIZE(0) |
-			   R300_TEX_START(0) |
-			   R300_TEX_SIZE(0)));
-            OUT_ACCEL_REG(R300_US_CODE_ADDR_1,
-			  (R300_ALU_START(0) |
-			   R300_ALU_SIZE(0) |
-			   R300_TEX_START(0) |
-			   R300_TEX_SIZE(0)));
-            OUT_ACCEL_REG(R300_US_CODE_ADDR_2,
-			  (R300_ALU_START(0) |
-			   R300_ALU_SIZE(0) |
-			   R300_TEX_START(0) |
-			   R300_TEX_SIZE(0)));
-	} else {
 	    BEGIN_ACCEL(6);
             OUT_ACCEL_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO);
             OUT_ACCEL_REG(R500_US_FC_CTRL, 0);
@@ -554,13 +548,8 @@ int Init3DEngine(RHDPtr info)
         OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D);
 	FINISH_ACCEL();
 
-	BEGIN_ACCEL(7);
+	BEGIN_ACCEL(5);
         OUT_ACCEL_REG(R300_SC_EDGERULE, 0xA5294A5);
-        OUT_ACCEL_REG(R300_SC_SCISSOR0, ((0 << R300_SCISSOR_X_SHIFT) |
-					 (0 << R300_SCISSOR_Y_SHIFT)));
-        OUT_ACCEL_REG(R300_SC_SCISSOR1, ((8191 << R300_SCISSOR_X_SHIFT) |
-					 (8191 << R300_SCISSOR_Y_SHIFT)));
-
         if (IS_R300_3D) {
 	    /* clip has offset 1440 */
             OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((1088 << R300_CLIP_X_SHIFT) |
@@ -581,7 +570,7 @@ int Init3DEngine(RHDPtr info)
              (info->ChipFamily == CHIP_FAMILY_RS300) ||
 	       (info->ChipFamily == CHIP_FAMILY_R200)) {
 
-	BEGIN_ACCEL(7);
+	BEGIN_ACCEL(6);
         if (info->ChipFamily == CHIP_FAMILY_RS300) {
             OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, RADEON_TCL_BYPASS);
         } else {
@@ -590,7 +579,6 @@ int Init3DEngine(RHDPtr info)
         OUT_ACCEL_REG(R200_PP_CNTL_X, 0);
         OUT_ACCEL_REG(R200_PP_TXMULTI_CTL_0, 0);
         OUT_ACCEL_REG(R200_SE_VTX_STATE_CNTL, 0);
-        OUT_ACCEL_REG(R200_RE_CNTL, 0x0);
         OUT_ACCEL_REG(R200_SE_VTE_CNTL, 0);
         OUT_ACCEL_REG(R200_SE_VAP_CNTL, R200_VAP_FORCE_W_TO_ONE |
                         R200_VAP_VF_MAX_VTX_NUM);
@@ -615,7 +603,8 @@ int Init3DEngine(RHDPtr info)
             OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, 0);
         else
             OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, RADEON_TCL_BYPASS);
-    OUT_ACCEL_REG(RADEON_SE_COORD_FMT, RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
+	OUT_ACCEL_REG(RADEON_SE_COORD_FMT,
+	    RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
                                        RADEON_VTX_ST0_NONPARAMETRIC     |
                                        RADEON_VTX_ST1_NONPARAMETRIC     |
                                        RADEON_TEX1_W_ROUTING_USE_W0);
@@ -634,8 +623,9 @@ int Init3DEngine(RHDPtr info)
 				       RADEON_ROUND_PREC_4TH_PIX));
 	FINISH_ACCEL();
     }
-
     safe_sti(ifl);
+    FIFOWait(64);
+    delay(2);
 
 }
 

drivers/video/ati2d/init_cp.c

@@ -19,11 +19,6 @@
 #	define RADEON_ISYNC_CPSCRATCH_IDLEGUI	(1 << 5)
 
 
-#define RADEON_IDLE_RETRY      16 /* Fall out of idle loops after this count */
-#define RADEON_TIMEOUT    4000000 /* Fall out of wait loops after this count */
-
-
-
 void RADEONEngineFlush(RHDPtr info)
 {
      int i;
@@ -56,17 +51,6 @@ void RADEONEngineFlush(RHDPtr info)
      }
 }
 
-static Bool R5xxFIFOWaitLocal(u32_t required)             //R100-R500
-{
-     int i;
-
-     for (i = 0; i < RADEON_TIMEOUT; i++)
-        if (required <= (INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK))
-           return TRUE;
-
-     dbgprintf("%s: Timeout 0x%08X.\n", __func__, (u32_t) INREG(RADEON_RBBM_STATUS));
-     return FALSE;
-}
 
 static int radeon_do_wait_for_idle()
 {
@@ -244,55 +228,6 @@ void init_ring_buffer(RHDPtr info)
 }
 
 
-void radeon_engine_reset(RHDPtr info)
-{
-    u32_t  clock_cntl_index;
-    u32_t  mclk_cntl;
-    u32_t  rbbm_soft_reset;
-    u32_t  host_path_cntl;
-
-    if (info->ChipFamily <= CHIP_FAMILY_RV410)
-    {
-	        /* may need something similar for newer chips */
-        clock_cntl_index = INREG(RADEON_CLOCK_CNTL_INDEX);
-        mclk_cntl = INPLL( RADEON_MCLK_CNTL);
-
-        OUTPLL(RADEON_MCLK_CNTL, (mclk_cntl |
-						    RADEON_FORCEON_MCLKA |
-						    RADEON_FORCEON_MCLKB |
-						    RADEON_FORCEON_YCLKA |
-						    RADEON_FORCEON_YCLKB |
-						    RADEON_FORCEON_MC |
-						    RADEON_FORCEON_AIC));
-	}
-
-    rbbm_soft_reset = INREG(RADEON_RBBM_SOFT_RESET);
-
-    OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
-					      RADEON_SOFT_RESET_CP |
-					      RADEON_SOFT_RESET_HI |
-					      RADEON_SOFT_RESET_SE |
-					      RADEON_SOFT_RESET_RE |
-					      RADEON_SOFT_RESET_PP |
-					      RADEON_SOFT_RESET_E2 |
-					      RADEON_SOFT_RESET_RB));
-    INREG(RADEON_RBBM_SOFT_RESET);
-    OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
-					      ~(RADEON_SOFT_RESET_CP |
-						RADEON_SOFT_RESET_HI |
-						RADEON_SOFT_RESET_SE |
-						RADEON_SOFT_RESET_RE |
-						RADEON_SOFT_RESET_PP |
-						RADEON_SOFT_RESET_E2 |
-						RADEON_SOFT_RESET_RB)));
-    INREG(RADEON_RBBM_SOFT_RESET);
-
-    if (info->ChipFamily <= CHIP_FAMILY_RV410) {
-        OUTPLL(RADEON_MCLK_CNTL, mclk_cntl);
-        OUTREG(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
-        OUTREG(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
-	}
- };
 
 #define RADEON_WAIT_UNTIL_IDLE() do {                   \
     OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 1 ) );         \
@@ -382,9 +317,6 @@ Bool init_cp(RHDPtr info)
 
      radeon_engine_reset(&rhd);
 
-    /* setup the raster pipes */
-     init_pipes(&rhd);
-
      rhd.ring_rp = rhd.ring_wp = INREG(RADEON_CP_RB_RPTR);
      OUTREG(RADEON_CP_RB_WPTR, rhd.ring_rp);
 

drivers/video/ati2d/makefile

@@ -4,12 +4,12 @@ FASM = e:/fasm/fasm.exe
 CFLAGS = -c -O2 -fomit-frame-pointer -fno-builtin-printf 
 LDRHD  = -shared -T ld.x -s --file-alignment 32
 
-INCLUDES = -I ../include
+INCLUDES = -I ../../include
 
-HFILES:=     ../include/types.h		\
+HFILES:=     ../../include/types.h	\
-             ../include/syscall.h	\
+             ../../include/syscall.h	\
+             ../../include/pci.h	\
              atihw.h      		\
-             pci.h        		\
              accel_2d.h   		\
              r5xx_regs.h 		\
              radeon_microcode.h
@@ -38,7 +38,7 @@ ATI2D =  ati2d.dll
 all: $(ATI2D)
 
 $(ATI2D): $(ATI_OBJ) $(SRC_DEP) $(HFILES) Makefile
-	wlink name ati2d.dll SYS nt_dll lib libdrv op offset=0 op nod op maxe=25 op el op STUB=stub.exe op START=_drvEntry @rhd.lk1
+	wlink name ati2d.dll SYS nt_dll lib libdrv op offset=0 op nod op maxe=25 op el op STUB=stub.exe op START=_drvEntry @ati2d.lk
 	kpack.exe ati2d.dll ati2d.drv
 
 ati2d.obj : ati2d.c $(SRC_DEP) $(HFILES) Makefile

drivers/video/ati2d/pci.c

@@ -84,6 +84,10 @@ RHDPtr FindPciDevice()
                 if (rhd.ChipFamily >= CHIP_FAMILY_R600)
                     dbgprintf("R600 unsupported yet.\nExit\n");
 
+                if( rhd.ChipFamily >= CHIP_FAMILY_R420)
+                    rhd.gart_type = RADEON_IS_PCIE;
+                else
+                    rhd.gart_type = RADEON_IS_PCI;
 
                 for (i = 0; i < 6; i++)
                 {
@@ -210,3 +214,75 @@ u32_t pciGetBaseSize(int bus, int devfn, int index, Bool destructive, Bool *min)
 }
 
 
+
+#define PCI_FIND_CAP_TTL    48
+
+static int __pci_find_next_cap_ttl(PCITAG pciTag, u8_t pos,
+                                   int cap, int *ttl)
+{
+    u8_t id;
+
+    while ((*ttl)--)
+    {
+        pos = pciReadByte(pciTag, pos);
+		if (pos < 0x40)
+			break;
+		pos &= ~3;
+        id = pciReadByte(pciTag, pos + PCI_CAP_LIST_ID);
+		if (id == 0xff)
+			break;
+		if (id == cap)
+			return pos;
+		pos += PCI_CAP_LIST_NEXT;
+	}
+	return 0;
+}
+
+static int __pci_find_next_cap(PCITAG pciTag, u8_t pos, int cap)
+{
+	int ttl = PCI_FIND_CAP_TTL;
+
+    return __pci_find_next_cap_ttl(pciTag, pos, cap, &ttl);
+}
+
+static int __pci_bus_find_cap_start(PCITAG pciTag)
+{
+    u16_t status;
+    u8_t  hdr_type;
+
+    status = pciReadWord(pciTag, PCI_STATUS);
+	if (!(status & PCI_STATUS_CAP_LIST))
+		return 0;
+
+    hdr_type = pciReadByte(pciTag, 0x0E);
+    switch (hdr_type)
+    {
+        case PCI_HEADER_TYPE_NORMAL:
+        case PCI_HEADER_TYPE_BRIDGE:
+            return PCI_CAPABILITY_LIST;
+        case PCI_HEADER_TYPE_CARDBUS:
+            return PCI_CB_CAPABILITY_LIST;
+        default:
+            return 0;
+	}
+	return 0;
+}
+
+
+int pci_find_capability(PCITAG pciTag, int cap)
+{
+	int pos;
+
+    pos = __pci_bus_find_cap_start(pciTag);
+	if (pos)
+        pos = __pci_find_next_cap(pciTag, pos, cap);
+
+	return pos;
+}
+
+
+static __inline__ int drm_device_is_pcie(PCITAG pciTag)
+{
+    return pci_find_capability(pciTag, PCI_CAP_ID_EXP);
+}
+

drivers/video/ati2d/pixmap.inc

@@ -129,28 +129,12 @@ int DestroyPixmap( pixmap_t *io )
 #define upper_32_bits(n) ((u32_t)(((n) >> 16) >> 16))
 
 
-static addr_t bind_pixmap(local_pixmap_t *pixmap)
+static void bind_pcie(u32_t *gart, addr_t base, count_t pages)
 {
-    count_t  pages;
+    addr_t page_base;
-    addr_t   base;
-
-    u32_t    tmp;
-
-    u32_t  *gart = rhd.gart_table;
-
-    pages = ((pixmap->height * pixmap->pitch+4095)&~4095)>>12;
-    base = pixmap->local;
-
-        //    tmp = INREG(RADEON_AIC_CNTL);
-        //    OUTREG(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 
     while(pages--)
     {
-        addr_t page_base;
-
-              //  *gart = base & ATI_PCIGART_PAGE_MASK;
-              //  base+= 4096;
-              //  gart++;
         page_base = base & ATI_PCIGART_PAGE_MASK;
 
         page_base >>= 8;
@@ -163,11 +147,40 @@ static addr_t bind_pixmap(local_pixmap_t *pixmap)
     }
     __asm__ __volatile("sfence":::"memory");
 
-         //   OUTREG(RADEON_AIC_CNTL, tmp | RADEON_PCIGART_TRANSLATE_EN);
-         //   OUTREG(RADEON_AIC_PT_BASE, rhd.gart_table_dma);
     RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
                       RADEON_PCIE_TX_GART_EN
                      | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
+}
+
+static void bind_pci(u32_t *gart, addr_t base, count_t pages)
+{
+    u32_t tmp;
+
+    tmp = INREG(RADEON_AIC_CNTL);
+    OUTREG(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
+
+    while(pages--)
+    {
+        *gart = base & ATI_PCIGART_PAGE_MASK;
+         base+= 4096;
+         gart++;
+    }
+    __asm__ __volatile("sfence":::"memory");
+
+    OUTREG(RADEON_AIC_CNTL, tmp | RADEON_PCIGART_TRANSLATE_EN);
+    OUTREG(RADEON_AIC_PT_BASE, rhd.gart_table_dma);
+}
+
+static addr_t bind_pixmap(local_pixmap_t *pixmap)
+{
+    u32_t   *gart = rhd.gart_table;
+    count_t  pages = ((pixmap->height * pixmap->pitch+4095)&~4095)>>12;
+    addr_t   base = pixmap->local;
+
+    if( rhd.gart_type == RADEON_IS_PCIE)
+        bind_pcie(gart, base, pages);
+    else
+        bind_pci(gart, base, pages);
 
     return ((pixmap->pitch / 64) << 22) | (rhd.gart_vm_start >> 10);
 }

drivers/video/ati2d/r500.inc

@@ -23,7 +23,79 @@
 #       define R300_DISABLE_MC_MCLKA        (1 << 21)
 #       define R300_DISABLE_MC_MCLKB        (1 << 21)
 
+void radeon_engine_reset(RHDPtr info)
+{
+    u32_t  clock_cntl_index;
+    u32_t  mclk_cntl;
+    u32_t  rbbm_soft_reset;
+    u32_t  host_path_cntl;
 
+    if (info->ChipFamily <= CHIP_FAMILY_RV410)
+    {
+	        /* may need something similar for newer chips */
+        clock_cntl_index = INREG(RADEON_CLOCK_CNTL_INDEX);
+        mclk_cntl = INPLL( RADEON_MCLK_CNTL);
+
+        OUTPLL(RADEON_MCLK_CNTL, (mclk_cntl |
+						    RADEON_FORCEON_MCLKA |
+						    RADEON_FORCEON_MCLKB |
+						    RADEON_FORCEON_YCLKA |
+						    RADEON_FORCEON_YCLKB |
+						    RADEON_FORCEON_MC |
+						    RADEON_FORCEON_AIC));
+	}
+
+    rbbm_soft_reset = INREG(RADEON_RBBM_SOFT_RESET);
+
+    OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
+					      RADEON_SOFT_RESET_CP |
+					      RADEON_SOFT_RESET_HI |
+					      RADEON_SOFT_RESET_SE |
+					      RADEON_SOFT_RESET_RE |
+					      RADEON_SOFT_RESET_PP |
+					      RADEON_SOFT_RESET_E2 |
+					      RADEON_SOFT_RESET_RB));
+    INREG(RADEON_RBBM_SOFT_RESET);
+    OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
+					      ~(RADEON_SOFT_RESET_CP |
+						RADEON_SOFT_RESET_HI |
+						RADEON_SOFT_RESET_SE |
+						RADEON_SOFT_RESET_RE |
+						RADEON_SOFT_RESET_PP |
+						RADEON_SOFT_RESET_E2 |
+						RADEON_SOFT_RESET_RB)));
+    INREG(RADEON_RBBM_SOFT_RESET);
+
+    if (info->ChipFamily <= CHIP_FAMILY_RV410) {
+        OUTPLL(RADEON_MCLK_CNTL, mclk_cntl);
+        OUTREG(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
+        OUTREG(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
+	}
+ };
+
+static Bool R5xxFIFOWaitLocal(u32_t required)             //R100-R500
+{
+     int i;
+
+     for (i = 0; i < RADEON_TIMEOUT; i++)
+        if (required <= (INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK))
+           return TRUE;
+
+     dbgprintf("%s: Timeout 0x%08X.\n", __func__, (u32_t) INREG(RADEON_RBBM_STATUS));
+     return FALSE;
+}
+
+void FIFOWait(u32_t required)
+{
+    int i;
+    for (i = 0; i < 200; i++)
+    {
+        if (required <= (INREG(RADEON_RBBM_STATUS) &
+                        RADEON_RBBM_FIFOCNT_MASK))
+           return ;
+        delay(2);
+    };
+};
 
 
 /*
@@ -116,7 +188,7 @@ R5xx2DSetup()
 void R5xxFIFOWait(u32_t required)
 {
     if (!R5xxFIFOWaitLocal(required)) {
- //     R5xx2DReset();
+      radeon_engine_reset(&rhd);
       R5xx2DSetup();
     }
 }
@@ -130,7 +202,6 @@ void R5xx2DIdle()
 }
 
 
-
 void  R5xx2DInit()
 {
     u32_t base;

drivers/video/radeonhd/Xmd.h

@@ -160,6 +160,7 @@ typedef CARD8		BOOL;
 #define BOOL	CARD8
 #endif
 
+typedef unsigned long long CARD64;
 /*
  * definitions for sign-extending bitfields on 64-bit architectures
  */

drivers/video/radeonhd/makefile

@@ -50,7 +50,7 @@ RHD_SRC:=	rhd.c			\
            	dbg.c            	\
            	pci.c			
 
-DBG_DEFINES = -DDBG_NONE
+DBG_DEFINES = -DDBG_CALL
 
 ATOM_BIOS_PARSER_SRCS = rhd_atomwrapper.c         \
                         AtomBios/CD_Operations.c      \

drivers/video/radeonhd/pci.h

@@ -0,0 +1,196 @@
+
+
+typedef struct {
+    int       vendor;
+    int       devtype;
+    int       devRev;
+    int       subsysVendor;
+    int       subsysCard;
+    int       bus;
+    int       devfn;
+//    int       func;
+    int       class;
+    int       subclass;
+    int       interface;
+    memType   memBase[6];
+    memType   ioBase[6];
+    int       size[6];
+    unsigned char	type[6];
+    memType   biosBase;
+    int       biosSize;
+//    pointer   thisCard;
+    Bool      validSize;
+//    Bool      validate;
+//    CARD32    listed_class;
+} pciVideoRec, *pciVideoPtr;
+
+#define PCI_CLASS_DISPLAY_VGA      0x0300
+/*
+ * Under PCI, each device has 256 bytes of configuration address space,
+ * of which the first 64 bytes are standardized as follows:
+ */
+#define PCI_VENDOR_ID                   0x000    /* 16 bits */
+#define PCI_DEVICE_ID                   0x002    /* 16 bits */
+#define PCI_COMMAND                     0x004    /* 16 bits */
+#define  PCI_COMMAND_IO                 0x001    /* Enable response in I/O space */
+#define  PCI_COMMAND_MEMORY             0x002    /* Enable response in Memory space */
+#define  PCI_COMMAND_MASTER             0x004    /* Enable bus mastering */
+#define  PCI_COMMAND_SPECIAL            0x008    /* Enable response to special cycles */
+#define  PCI_COMMAND_INVALIDATE         0x010    /* Use memory write and invalidate */
+#define  PCI_COMMAND_VGA_PALETTE        0x020    /* Enable palette snooping */
+#define  PCI_COMMAND_PARITY             0x040    /* Enable parity checking */
+#define  PCI_COMMAND_WAIT               0x080    /* Enable address/data stepping */
+#define  PCI_COMMAND_SERR               0x100    /* Enable SERR */
+#define  PCI_COMMAND_FAST_BACK          0x200    /* Enable back-to-back writes */
+#define  PCI_COMMAND_INTX_DISABLE       0x400    /* INTx Emulation Disable */
+
+#define PCI_STATUS                      0x006    /* 16 bits */
+#define  PCI_STATUS_CAP_LIST            0x010    /* Support Capability List */
+#define  PCI_STATUS_66MHZ               0x020    /* Support 66 Mhz PCI 2.1 bus */
+#define  PCI_STATUS_UDF                 0x040    /* Support User Definable Features [obsolete] */
+#define  PCI_STATUS_FAST_BACK           0x080    /* Accept fast-back to back */
+#define  PCI_STATUS_PARITY              0x100    /* Detected parity error */
+#define  PCI_STATUS_DEVSEL_MASK         0x600    /* DEVSEL timing */
+#define  PCI_STATUS_DEVSEL_FAST         0x000
+#define  PCI_STATUS_DEVSEL_MEDIUM       0x200
+#define  PCI_STATUS_DEVSEL_SLOW         0x400
+#define  PCI_STATUS_SIG_TARGET_ABORT    0x800    /* Set on target abort */
+#define  PCI_STATUS_REC_TARGET_ABORT    0x1000   /* Master ack of " */
+#define  PCI_STATUS_REC_MASTER_ABORT    0x2000   /* Set on master abort */
+#define  PCI_STATUS_SIG_SYSTEM_ERROR    0x4000   /* Set when we drive SERR */
+#define  PCI_STATUS_DETECTED_PARITY     0x8000   /* Set on parity error */
+
+#define PCI_CLASS_REVISION               0x08    /* High 24 bits are class, low 8 revision */
+#define PCI_REVISION_ID                  0x08    /* Revision ID */
+#define PCI_CLASS_PROG                   0x09    /* Reg. Level Programming Interface */
+#define PCI_CLASS_DEVICE                 0x0a    /* Device class */
+
+#define PCI_CACHE_LINE_SIZE              0x0c    /* 8 bits */
+#define PCI_LATENCY_TIMER                0x0d    /* 8 bits */
+#define PCI_HEADER_TYPE                  0x0e    /* 8 bits */
+#define  PCI_HEADER_TYPE_NORMAL             0
+#define  PCI_HEADER_TYPE_BRIDGE             1
+#define  PCI_HEADER_TYPE_CARDBUS            2
+
+#define PCI_BIST                         0x0f    /* 8 bits */
+#define  PCI_BIST_CODE_MASK              0x0f    /* Return result */
+#define  PCI_BIST_START                  0x40    /* 1 to start BIST, 2 secs or less */
+#define  PCI_BIST_CAPABLE                0x80    /* 1 if BIST capable */
+
+#define PCI_CAPABILITY_LIST              0x34    /* Offset of first capability list entry */
+#define PCI_CB_CAPABILITY_LIST           0x14
+/* Capability lists */
+
+#define PCI_CAP_LIST_ID                  0       /* Capability ID */
+#define  PCI_CAP_ID_PM                   0x01    /* Power Management */
+#define  PCI_CAP_ID_AGP                  0x02    /* Accelerated Graphics Port */
+#define  PCI_CAP_ID_VPD                  0x03    /* Vital Product Data */
+#define  PCI_CAP_ID_SLOTID               0x04    /* Slot Identification */
+#define  PCI_CAP_ID_MSI                  0x05    /* Message Signalled Interrupts */
+#define  PCI_CAP_ID_CHSWP                0x06    /* CompactPCI HotSwap */
+#define  PCI_CAP_ID_PCIX                 0x07    /* PCI-X */
+#define  PCI_CAP_ID_HT                   0x08    /* HyperTransport */
+#define  PCI_CAP_ID_VNDR                 0x09    /* Vendor specific capability */
+#define  PCI_CAP_ID_SHPC                 0x0C    /* PCI Standard Hot-Plug Controller */
+#define  PCI_CAP_ID_EXP                  0x10    /* PCI Express */
+#define  PCI_CAP_ID_MSIX                 0x11    /* MSI-X */
+#define PCI_CAP_LIST_NEXT                1       /* Next capability in the list */
+#define PCI_CAP_FLAGS                    2       /* Capability defined flags (16 bits) */
+#define PCI_CAP_SIZEOF                   4
+
+
+/* AGP registers */
+
+#define PCI_AGP_VERSION                     2   /* BCD version number */
+#define PCI_AGP_RFU                         3   /* Rest of capability flags */
+#define PCI_AGP_STATUS                      4   /* Status register */
+#define  PCI_AGP_STATUS_RQ_MASK        0xff000000  /* Maximum number of requests - 1 */
+#define  PCI_AGP_STATUS_SBA            0x0200   /* Sideband addressing supported */
+#define  PCI_AGP_STATUS_64BIT          0x0020   /* 64-bit addressing supported */
+#define  PCI_AGP_STATUS_FW             0x0010   /* FW transfers supported */
+#define  PCI_AGP_STATUS_RATE4          0x0004   /* 4x transfer rate supported */
+#define  PCI_AGP_STATUS_RATE2          0x0002   /* 2x transfer rate supported */
+#define  PCI_AGP_STATUS_RATE1          0x0001   /* 1x transfer rate supported */
+#define PCI_AGP_COMMAND                     8   /* Control register */
+#define  PCI_AGP_COMMAND_RQ_MASK    0xff000000  /* Master: Maximum number of requests */
+#define  PCI_AGP_COMMAND_SBA           0x0200   /* Sideband addressing enabled */
+#define  PCI_AGP_COMMAND_AGP           0x0100   /* Allow processing of AGP transactions */
+#define  PCI_AGP_COMMAND_64BIT         0x0020   /* Allow processing of 64-bit addresses */
+#define  PCI_AGP_COMMAND_FW            0x0010   /* Force FW transfers */
+#define  PCI_AGP_COMMAND_RATE4         0x0004   /* Use 4x rate */
+#define  PCI_AGP_COMMAND_RATE2         0x0002   /* Use 2x rate */
+#define  PCI_AGP_COMMAND_RATE1         0x0001   /* Use 1x rate */
+#define PCI_AGP_SIZEOF                     12
+
+
+#define PCI_MAP_REG_START   0x10
+#define PCI_MAP_REG_END			0x28
+#define PCI_MAP_ROM_REG			0x30
+
+#define PCI_MAP_MEMORY			0x00000000
+#define PCI_MAP_IO			0x00000001
+
+#define PCI_MAP_MEMORY_TYPE		0x00000007
+#define PCI_MAP_IO_TYPE			0x00000003
+
+#define PCI_MAP_MEMORY_TYPE_32BIT	0x00000000
+#define PCI_MAP_MEMORY_TYPE_32BIT_1M	0x00000002
+#define PCI_MAP_MEMORY_TYPE_64BIT	0x00000004
+#define PCI_MAP_MEMORY_TYPE_MASK	0x00000006
+#define PCI_MAP_MEMORY_CACHABLE		0x00000008
+#define PCI_MAP_MEMORY_ATTR_MASK	0x0000000e
+#define PCI_MAP_MEMORY_ADDRESS_MASK	0xfffffff0
+
+#define PCI_MAP_IO_ATTR_MASK		0x00000003
+
+#define PCI_MAP_IS_IO(b)  ((b) & PCI_MAP_IO)
+#define PCI_MAP_IS_MEM(b)	(!PCI_MAP_IS_IO(b))
+
+#define PCI_MAP_IS64BITMEM(b)	\
+	(((b) & PCI_MAP_MEMORY_TYPE_MASK) == PCI_MAP_MEMORY_TYPE_64BIT)
+
+#define PCIGETMEMORY(b)   ((b) & PCI_MAP_MEMORY_ADDRESS_MASK)
+#define PCIGETMEMORY64HIGH(b)	(*((CARD32*)&b + 1))
+#define PCIGETMEMORY64(b)	\
+	(PCIGETMEMORY(b) | ((CARD64)PCIGETMEMORY64HIGH(b) << 32))
+
+#define PCI_MAP_IO_ADDRESS_MASK		0xfffffffc
+
+#define PCIGETIO(b)		((b) & PCI_MAP_IO_ADDRESS_MASK)
+
+#define PCI_MAP_ROM_DECODE_ENABLE	0x00000001
+#define PCI_MAP_ROM_ADDRESS_MASK	0xfffff800
+
+#define PCIGETROM(b)		((b) & PCI_MAP_ROM_ADDRESS_MASK)
+
+int pciGetBaseSize(int bus, int devfn, int index, Bool destructive, Bool *min);
+int pciGetInfo(pciVideoPtr pci);
+
+
+
+#ifndef PCI_DOM_MASK
+# define PCI_DOM_MASK 0x0ffu
+#endif
+#define PCI_DOMBUS_MASK (((PCI_DOM_MASK) << 8) | 0x0ffu)
+
+#define PCI_MAKE_TAG(b,d,f)  ((((b) & (PCI_DOMBUS_MASK)) << 16) | \
+			      (((d) & 0x00001fu) << 11) | \
+			      (((f) & 0x000007u) << 8))
+
+#define PCI_BUS_FROM_TAG(tag)  (((tag) >> 16) & (PCI_DOMBUS_MASK))
+#define PCI_DEV_FROM_TAG(tag)  (((tag) & 0x0000f800u) >> 11)
+#define PCI_FUNC_FROM_TAG(tag) (((tag) & 0x00000700u) >> 8)
+#define PCI_DFN_FROM_TAG(tag)  (((tag) & 0x0000ff00u) >> 8)
+
+
+#define PCI_CMD_STAT_REG        0x04
+
+
+typedef unsigned int PCITAG;
+
+extern inline PCITAG
+pciTag(int busnum, int devnum, int funcnum)
+{
+	return(PCI_MAKE_TAG(busnum,devnum,funcnum));
+}
+

drivers/video/radeonhd/rhd.c

@@ -1,3 +1,27 @@
+/*
+ * Copyright 2007  Luc Verhaegen <lverhaegen@novell.com>
+ * Copyright 2007  Matthias Hopf <mhopf@novell.com>
+ * Copyright 2007  Egbert Eich   <eich@novell.com>
+ * Copyright 2007  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
 
 //ld -T ld.x -s --shared --image-base 0 --file-alignment 32 -o test.exe test.obj core.lib
 
@@ -8,8 +32,10 @@
 #include "rhd_atombios.h"
 #include "rhd_regs.h"
 #include "rhd_mc.h"
+#include "rhd_atombios.h"
 #include "rhd_connector.h"
 #include "rhd_output.h"
+#include "rhd_biosscratch.h"
 #include "rhd_card.h"
 #include "rhd_vga.h"
 #include "rhd_crtc.h"
@@ -28,12 +54,16 @@ static void rhdModeInit(ScrnInfoPtr pScrn, DisplayModePtr mode);
 static void rhdSetMode(ScrnInfoPtr pScrn, DisplayModePtr mode);
 static void RHDAdjustFrame(RHDPtr rhdPtr, int x, int y, int flags);
 static Bool rhdMapFB(RHDPtr rhdPtr);
+static void rhdGetIGPNorthBridgeInfo(RHDPtr rhdPtr);
 
 Bool OldSetupConnectors(RHDPtr rhdPtr);
 Bool OldConnectorsInit(RHDPtr rhdPtr);
 
 int rhdInitHeap(RHDPtr rhdPtr);
 
+static enum rhdCardType rhdGetCardType(RHDPtr rhdPtr);
+
+
 static u32_t _PciApi(int cmd);
 static int SupportedModes;
 
@@ -287,6 +317,9 @@ rhdOutputConnectorCheck(struct rhdConnector *Connector)
     }
 }
 
+/*
+ *
+ */
 static Bool
 rhdModeLayoutSelect(RHDPtr rhdPtr)
 {
@@ -323,7 +356,8 @@ rhdModeLayoutSelect(RHDPtr rhdPtr)
   {
     ConnectorIsDMS59 = rhdPtr->Card->flags & RHD_CARD_FLAG_DMS59;
     if (ConnectorIsDMS59)
-      dbgprintf("Card %s has a DMS-59 connector.\n", rhdPtr->Card->name);
+	    xf86DrvMsg(rhdPtr->scrnIndex, X_INFO, "Card %s has a DMS-59"
+		       " connector.\n", rhdPtr->Card->name);
   }
 
     /* Check on the basis of Connector->HPD */
@@ -334,42 +368,34 @@ rhdModeLayoutSelect(RHDPtr rhdPtr)
     if (!Connector)
 	    continue;
 
-    if (Connector->HPDCheck)
+
-    {
+	if (Connector->HPDCheck) {
-        if (Connector->HPDCheck(Connector))
+	    if (Connector->HPDCheck(Connector)) {
-        {
           Connector->HPDAttached = TRUE;
           rhdOutputConnectorCheck(Connector);
-        }
+	    } else {
-        else
-        {
           Connector->HPDAttached = FALSE;
           if (ConnectorIsDMS59)
             rhdOutputConnectorCheck(Connector);
 	    }
-    }
+	} else
-    else
       rhdOutputConnectorCheck(Connector);
   }
 
   i = 0; /* counter for CRTCs */
   for (Output = rhdPtr->Outputs; Output; Output = Output->Next)
-    if (Output->Connector)
+	if (Output->Connector) {
-    {
       struct rhdMonitor *Monitor = NULL;
 
       Connector = Output->Connector;
 
       Monitor = RHDMonitorInit(Connector);
 
-      if (!Monitor && (Connector->Type == RHD_CONNECTOR_PANEL))
+	    if (!Monitor && (Connector->Type == RHD_CONNECTOR_PANEL)) {
-      {
 		xf86DrvMsg(rhdPtr->scrnIndex, X_WARNING, "Unable to attach a"
 			   " monitor to connector \"%s\"\n", Connector->Name);
         Output->Active = FALSE;
-      }
+	    } else if (!Output->AllocFree || Output->AllocFree(Output, RHD_OUTPUT_ALLOC)){
-      else
-      {
         Connector->Monitor = Monitor;
 
         Output->Active = TRUE;
@@ -379,8 +405,7 @@ rhdModeLayoutSelect(RHDPtr rhdPtr)
 
         Output->Crtc->Active = TRUE;
 
-        if (RHDScalePolicy(Monitor, Connector))
+		if (RHDScalePolicy(Monitor, Connector)) {
-        {
 		    Output->Crtc->ScaledToMode = RHDModeCopy(Monitor->NativeMode);
 		    xf86DrvMsg(rhdPtr->scrnIndex, X_INFO,
 			       "Crtc[%i]: found native mode from Monitor[%s]: ",
@@ -389,8 +414,7 @@ rhdModeLayoutSelect(RHDPtr rhdPtr)
 		}
         Found = TRUE;
 
-        if (Monitor)
+		if (Monitor) {
-        {
   /* If this is a DVI attached monitor, enable reduced blanking.
    * TODO: iiyama vm pro 453: CRT with DVI-D == No reduced.
    */
@@ -409,8 +433,7 @@ rhdModeLayoutSelect(RHDPtr rhdPtr)
                      "Connector \"%s\" uses Monitor \"%s\":\n",
                       Connector->Name, Monitor->Name);
           RHDMonitorPrint(Monitor);
-        }
+		} else
-        else
           xf86DrvMsg(rhdPtr->scrnIndex, X_WARNING,
                      "Connector \"%s\": Failed to retrieve Monitor"
                      " information.\n", Connector->Name);
@@ -418,20 +441,22 @@ rhdModeLayoutSelect(RHDPtr rhdPtr)
     }
 
     /* Now validate the scaled modes attached to crtcs */
-    for (i = 0; i < 2; i++)
+    for (i = 0; i < 2; i++) {
-    {
       struct rhdCrtc *crtc = rhdPtr->Crtc[i];
-      if (crtc->ScaledToMode && RHDValidateScaledToMode(crtc, crtc->ScaledToMode) != MODE_OK)
+	if (crtc->ScaledToMode && RHDValidateScaledToMode(crtc, crtc->ScaledToMode) != MODE_OK) {
-      {
 	    xf86DrvMsg(rhdPtr->scrnIndex, X_ERROR, "Crtc[%i]: scaled mode invalid.\n", crtc->Id);
 	    xfree(crtc->ScaledToMode);
 	    crtc->ScaledToMode = NULL;
       }
-    };
+    }
   return Found;
 }
 
-void rhdModeLayoutPrint(RHDPtr rhdPtr)
+     /*
+ *
+ */
+static void
+rhdModeLayoutPrint(RHDPtr rhdPtr)
 {
     struct rhdCrtc *Crtc;
     struct rhdOutput *Output;
@@ -509,6 +534,7 @@ void rhdModeLayoutPrint(RHDPtr rhdPtr)
     xf86Msg(X_NONE, "\n");
 }
 
+
 DisplayModePtr
 rhdCreateModesListAndValidate(ScrnInfoPtr pScrn, Bool Silent);
 void RHDPrintModeline(DisplayModePtr mode);
@@ -516,13 +542,7 @@ void RHDPrintModeline(DisplayModePtr mode);
 int RHDPreInit()
 {
     RHDI2CDataArg i2cArg;
-
+    RHDPtr rhdPtr = &rhd;
-  if (rhd.Card && rhd.Card->flags & RHD_CARD_FLAG_HPDSWAP &&
-      rhd.hpdUsage == RHD_HPD_USAGE_AUTO)
-    rhd.hpdUsage = RHD_HPD_USAGE_AUTO_SWAP;
-  if (rhd.Card && rhd.Card->flags & RHD_CARD_FLAG_HPDOFF &&
-      rhd.hpdUsage == RHD_HPD_USAGE_AUTO)
-    rhd.hpdUsage = RHD_HPD_USAGE_AUTO_OFF;
 
     /* We need access to IO space already */
     if (!rhdMapMMIO()) {
@@ -530,18 +550,26 @@ int RHDPreInit()
         return 0;
     };
 
-  rhd.videoRam = rhdGetVideoRamSize(&rhd);
-  if (!rhd.videoRam)
-  {
-    dbgprintf("No Video RAM detected.\n");
-	    goto error1;
-	}
-  dbgprintf("VideoRAM: %d kByte\n",rhd.videoRam);
 
-  rhd.FbFreeStart = 0;
+    if (RHDIsIGP(rhd.ChipSet))
-  rhd.FbFreeSize = rhd.videoRam << 10;
+        rhdGetIGPNorthBridgeInfo(&rhd);
+
+    rhd.Card = RHDCardIdentify(&rhd);
+    if (rhd.Card)
+        dbgprintf("Detected an %s on a %s\n", rhd.chipset_name, rhd.Card->name);
+    else
+        dbgprintf("Detected an %s on an unidentified card\n", rhd.chipset_name);
+
+    if (rhdPtr->Card && rhdPtr->Card->flags & RHD_CARD_FLAG_HPDSWAP &&
+	rhdPtr->hpdUsage == RHD_HPD_USAGE_AUTO)
+	rhdPtr->hpdUsage = RHD_HPD_USAGE_AUTO_SWAP;
+    if (rhdPtr->Card && rhdPtr->Card->flags & RHD_CARD_FLAG_HPDOFF &&
+	rhdPtr->hpdUsage == RHD_HPD_USAGE_AUTO)
+	rhdPtr->hpdUsage = RHD_HPD_USAGE_AUTO_OFF;
+
+    rhdPtr->cardType = rhdGetCardType(rhdPtr);
+
 
-#ifdef ATOM_BIOS
     {
         AtomBiosArgRec atomBiosArg;
 
@@ -551,13 +579,20 @@ int RHDPreInit()
 
    // rhd.UseAtomFlags = 0;
 
-    if (RHDAtomBiosFunc(&rhd, NULL, ATOMBIOS_INIT, &atomBiosArg)
+        if (RHDAtomBiosFunc(&rhd, NULL, ATOMBIOS_INIT, &atomBiosArg) == ATOM_SUCCESS)
-        == ATOM_SUCCESS)
         {
             rhd.atomBIOS = atomBiosArg.atomhandle;
         }
     }
 
+    rhd.videoRam = rhdGetVideoRamSize(&rhd);
+    if (!rhd.videoRam)
+    {
+        dbgprintf("No Video RAM detected.\n");
+	    goto error1;
+	}
+    dbgprintf("VideoRAM: %d kByte\n",rhd.videoRam);
+
     if (rhd.atomBIOS)                        /* for testing functions */
     {
         AtomBiosArgRec atomBiosArg;
@@ -579,7 +614,11 @@ int RHDPreInit()
         RHDAtomBiosFunc(&rhd, rhd.atomBIOS, GET_MAX_PIXEL_CLK, &atomBiosArg);
         RHDAtomBiosFunc(&rhd, rhd.atomBIOS, GET_REF_CLOCK, &atomBiosArg);
     }
-#endif
+
+
+    rhd.FbFreeStart = 0;
+    rhd.FbFreeSize = rhd.videoRam << 10;
+
 
     if (RHDI2CFunc((int)&rhd, NULL, RHD_I2C_INIT, &i2cArg) == RHD_I2C_SUCCESS)
         rhd.I2C = i2cArg.I2CBusList;
@@ -595,7 +634,7 @@ int RHDPreInit()
         return 0;
     }
 
-  rhdMapFB(&rhd);
+//  rhdMapFB(&rhd);
 
     Scrn.rhdPtr       = &rhd;
     Scrn.driverName   = "Radeon HD driver";
@@ -616,6 +655,7 @@ int RHDPreInit()
 
     RHDVGAInit(&rhd);
     RHDMCInit(&rhd);
+
     if (!RHDCrtcsInit(&rhd))
         RHDAtomCrtcsInit(&rhd);
     if (!RHDPLLsInit(&rhd))
@@ -629,11 +669,69 @@ int RHDPreInit()
         goto error1;
     }
 
+    {
+        struct rhdAtomOutputDeviceList *OutputDeviceList = NULL;
+
+        if (rhdPtr->Card
+            && rhdPtr->Card->ConnectorInfo[0].Type != RHD_CONNECTOR_NONE
+            && (rhdPtr->Card->DeviceInfo[0][0] != atomNone
+            || rhdPtr->Card->DeviceInfo[0][1] != atomNone))
+        {
+            int i, k = 0;
+
+            for (i = 0; i < RHD_CONNECTORS_MAX; i++)
+            {
+                int j;
+                if (rhdPtr->Card->ConnectorInfo[i].Type == RHD_CONNECTOR_NONE)
+                    break;
+                for (j = 0; j < MAX_OUTPUTS_PER_CONNECTOR; j++)
+                {
+                    if (rhdPtr->Card->ConnectorInfo[i].Output[j] != RHD_OUTPUT_NONE)
+                    {
+                        if (!(OutputDeviceList =
+                             (struct rhdAtomOutputDeviceList *)
+                              xrealloc(OutputDeviceList,
+                                       sizeof (struct rhdAtomOutputDeviceList) * (k + 1))))
+                            break;
+                        OutputDeviceList[k].ConnectorType = rhdPtr->Card->ConnectorInfo[i].Type;
+                        OutputDeviceList[k].DeviceId = rhdPtr->Card->DeviceInfo[i][j];
+                        OutputDeviceList[k].OutputType = rhdPtr->Card->ConnectorInfo[i].Output[j];
+                        dbgprintf("OutputDevice: C: 0x%2.2x O: 0x%2.2x DevID: 0x%2.2x\n",
+                                   OutputDeviceList[k].ConnectorType,
+                                   OutputDeviceList[k].OutputType,
+                                   OutputDeviceList[k].DeviceId);
+                        k++;
+                    }
+                }
+            }
+        }
+        else
+        {
+            AtomBiosArgRec data;
+
+            data.chipset = rhdPtr->ChipSet;
+            if (RHDAtomBiosFunc(rhdPtr, rhdPtr->atomBIOS,
+				ATOMBIOS_GET_OUTPUT_DEVICE_LIST, &data) == ATOM_SUCCESS)
+                OutputDeviceList = data.OutputDeviceList;
+        }
+
+        if (OutputDeviceList)
+        {
+            struct rhdOutput *Output;
+
+            for (Output = rhdPtr->Outputs; Output; Output = Output->Next)
+                RHDAtomSetupOutputDriverPrivate(OutputDeviceList, Output);
+            xfree(OutputDeviceList);
+        }
+    }
+
+
     if (!rhdModeLayoutSelect(&rhd))
     {
         dbgprintf("Failed to detect a connected monitor\n");
         goto error1;
 	}
+
     RHDConfigMonitorSet(&rhd, FALSE);
     rhdModeLayoutPrint(&rhd);
 
@@ -669,9 +767,9 @@ int __stdcall drvEntry(int action)
     if(action != 1)
         return 0;
 
-  if(!dbg_open("/rd/1/ati.txt"))
+    if(!dbg_open("/rd/1/drivers/ati.txt"))
     {
-     printf("Can't open /rd/1/ati.txt\nExit\n");
+        printf("Can't open /rd/1/drivers/ati.txt\nExit\n");
         return 0;
     }
     if(!FindPciDevice())
@@ -679,12 +777,6 @@ int __stdcall drvEntry(int action)
 
     rhd.scrnIndex = (int)&rhd;
 
-  rhd.Card = RHDCardIdentify(&rhd);
-  if (rhd.Card)
-    dbgprintf("Detected an %s on a %s\n", rhd.chipset_name, rhd.Card->name);
-  else
-    dbgprintf("Detected an %s on an unidentified card\n", rhd.chipset_name);
-
     for(i=0;i<6;i++)
     {
         if(rhd.pci.memBase[i])
@@ -707,7 +799,7 @@ int __stdcall drvEntry(int action)
 void usleep(u32_t delay)
 {
   if(!delay) delay++;
-  delay*=2000;
+  delay*=1000;
 
   asm(
      "1:\n\t"
@@ -738,37 +830,20 @@ rhdPrepareMode(RHDPtr rhdPtr)
 
     /* no active outputs == no mess */
     RHDOutputsPower(rhdPtr, RHD_POWER_RESET);
-
-    /* Disable CRTCs to stop noise from appearing. */
-    rhdPtr->Crtc[0]->Power(rhdPtr->Crtc[0], RHD_POWER_RESET);
-    rhdPtr->Crtc[1]->Power(rhdPtr->Crtc[1], RHD_POWER_RESET);
 }
 
-
+/*
-static void
+ * */static void
 rhdModeInit(ScrnInfoPtr pScrn, DisplayModePtr mode)
 {
     RHDPtr rhdPtr = pScrn->rhdPtr;
 
     RHDFUNC(rhdPtr);
-//    pScrn->vtSema = TRUE;
-
-    /* Stop crap from being shown: gets reenabled through SaveScreen */
-//    rhdPtr->Crtc[0]->Blank(rhdPtr->Crtc[0], TRUE);
-//    rhdPtr->Crtc[1]->Blank(rhdPtr->Crtc[1], TRUE);
-
-    rhdPrepareMode(rhdPtr);
-
-    /* now disable our VGA Mode */
-    RHDVGADisable(rhdPtr);
-
-    /* now set up the MC */
-    RHDMCSetup(rhdPtr);
 
     rhdSetMode(pScrn, mode);
 }
 
-static void
+/* * */static void
 rhdSetMode(ScrnInfoPtr pScrn, DisplayModePtr mode)
 {
     RHDPtr rhdPtr = RHDPTR(pScrn);
@@ -1033,3 +1108,57 @@ _RHDWriteMC(int scrnIndex, CARD32 addr, CARD32 data)
     }
 }
 
+/*
+ *
+ */
+static void
+rhdGetIGPNorthBridgeInfo(RHDPtr rhdPtr)
+{
+    switch (rhdPtr->ChipSet)
+    {
+        case RHD_RS600:
+            break;
+        case RHD_RS690:
+        case RHD_RS740:
+        case RHD_RS780:
+            rhdPtr->NBPciTag = pciTag(0,0,0);
+            break;
+        default:
+            break;
+    }
+}
+
+static enum rhdCardType
+rhdGetCardType(RHDPtr rhdPtr)
+{
+    CARD32 cmd_stat;
+
+    if (rhdPtr->ChipSet == RHD_RS780)
+        return RHD_CARD_PCIE;
+
+    cmd_stat = pciReadLong(rhdPtr->PciTag, PCI_CMD_STAT_REG);
+
+    if (cmd_stat & 0x100000) {
+        CARD32 cap_ptr, cap_id;
+
+        cap_ptr = pciReadLong(rhdPtr->PciTag, 0x34);
+        cap_ptr &= 0xfc;
+
+        while (cap_ptr)
+        {
+            cap_id = pciReadLong(rhdPtr->PciTag, cap_ptr);
+            switch (cap_id & 0xff) {
+                case RHD_PCI_CAPID_AGP:
+                    xf86DrvMsg(rhdPtr->scrnIndex, X_INFO, "AGP Card Detected\n");
+                    return RHD_CARD_AGP;
+                case RHD_PCI_CAPID_PCIE:
+                    xf86DrvMsg(rhdPtr->scrnIndex, X_INFO, "PCIE Card Detected\n");
+                    return RHD_CARD_PCIE;
+            }
+            cap_ptr = (cap_id >> 8) & 0xff;
+        }
+    }
+    return RHD_CARD_NONE;
+}
+
+

drivers/video/radeonhd/rhd.h

@@ -1,4 +1,6 @@
+
 #include "pci.h"
+
 #include "rhd_regs.h"
 
 typedef struct _ScrnInfoRec *ScrnInfoPtr;
@@ -425,6 +427,8 @@ typedef struct RHDRec
 
   CARD32                 FbBase;            /* map base of fb   */
   CARD32                 FbIntAddress;      /* card internal address of FB */
+ CARD32                  FbIntSize;         /* card internal FB aperture size */
+
   CARD32                 FbMapSize;
 
   CARD32                 FbFreeStart;
@@ -453,6 +457,8 @@ typedef struct RHDRec
   PCITAG                 NBPciTag;
 
   CARD16                 PciDeviceID;
+  enum rhdCardType       cardType;
+
   CARD16                 subvendor_id;
   CARD16                 subdevice_id;
   pciVideoRec            pci;
@@ -555,25 +561,7 @@ extern void _RHDWriteMC(int scrnIndex, CARD32 addr, CARD32 data);
 
 char * RhdAppendString(char *s1, const char *s2);
 
-#ifndef PCI_DOM_MASK
-# define PCI_DOM_MASK 0x0ffu
-#endif
-#define PCI_DOMBUS_MASK (((PCI_DOM_MASK) << 8) | 0x0ffu)
 
-#define PCI_MAKE_TAG(b,d,f)  ((((b) & (PCI_DOMBUS_MASK)) << 16) | \
-			      (((d) & 0x00001fu) << 11) | \
-			      (((f) & 0x000007u) << 8))
-
-#define PCI_BUS_FROM_TAG(tag)  (((tag) >> 16) & (PCI_DOMBUS_MASK))
-#define PCI_DEV_FROM_TAG(tag)  (((tag) & 0x0000f800u) >> 11)
-#define PCI_FUNC_FROM_TAG(tag) (((tag) & 0x00000700u) >> 8)
-#define PCI_DFN_FROM_TAG(tag)  (((tag) & 0x0000ff00u) >> 8)
-
-extern inline PCITAG
-pciTag(int busnum, int devnum, int funcnum)
-{
-	return(PCI_MAKE_TAG(busnum,devnum,funcnum));
-}
 
 #define  LOG_DEBUG    0
 

drivers/video/radeonhd/rhd_atombios.c

@@ -27,11 +27,11 @@
 #ifdef HAVE_CONFIG_H
 # include "config.h"
 #endif
+#include "xf86.h"
 
 
 /* only for testing now */
 
-#include "common.h"
 #include "rhd.h"
 #include "edid.h"
 #include "rhd_atombios.h"

drivers/video/radeonhd/rhd_atomcrtc.c

@@ -140,7 +140,7 @@ rhdAtomScaleSet(struct rhdCrtc *Crtc, enum rhdCrtcScaleType Type,
     data.Address = NULL;
     RHDAtomBiosFunc(rhdPtr->scrnIndex, rhdPtr->atomBIOS, ATOM_SET_REGISTER_LIST_LOCATION, &data);
 
-    RHDTuneMCAccessForDisplay(rhdPtr, Crtc->Id, Mode,
+    RHDMCTuneAccessForDisplay(rhdPtr, Crtc->Id, Mode,
 			      ScaledToMode ? ScaledToMode : Mode);
 }
 
@@ -254,7 +254,7 @@ rhdAtomModeSet(struct rhdCrtc *Crtc, DisplayModePtr Mode)
 /*
  *
  */
-static void
+static Bool
 rhdAtomCrtcPower(struct rhdCrtc *Crtc, int Power)
 {
     RHDPtr rhdPtr = RHDPTRI(Crtc);
@@ -292,6 +292,13 @@ rhdAtomCrtcPower(struct rhdCrtc *Crtc, int Power)
     }
     data.Address = NULL;
     RHDAtomBiosFunc(Crtc->scrnIndex, rhdPtr->atomBIOS, ATOM_SET_REGISTER_LIST_LOCATION, &data);
+
+    /*
+     * we always claim we succeeded here, after all, we know, AtomBIOS knows
+     * how to do things, right?
+     * Err, no, when we use AtomBIOS we should not have a clue how to find out.
+     */
+    return TRUE;
 }
 
 /*