forked from KolibriOS/kolibrios
715 lines
17 KiB
C++
715 lines
17 KiB
C++
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// This file is part of the Cyclone 68000 Emulator
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// Copyright (c) 2004,2011 FinalDave (emudave (at) gmail.com)
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// Copyright (c) 2005-2011 Gražvydas "notaz" Ignotas (notasas (at) gmail.com)
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// This code is licensed under the GNU General Public License version 2.0 and the MAME License.
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// You can choose the license that has the most advantages for you.
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// SVN repository can be found at http://code.google.com/p/cyclone68000/
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#include "app.h"
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// --------------------- Opcodes 0x0100+ ---------------------
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// Emit a Btst (Register) opcode 0000nnn1 ttaaaaaa
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int OpBtstReg(int op)
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{
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int use=0;
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int type=0,sea=0,tea=0;
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int size=0;
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type=(op>>6)&3; // Btst/Bchg/Bclr/Bset
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// Get source and target EA
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sea=(op>>9)&7;
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tea=op&0x003f;
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if (tea<0x10) size=2; // For registers, 32-bits
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if ((tea&0x38)==0x08) return 1; // movep
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// See if we can do this opcode:
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if (EaCanRead(tea,0)==0) return 1;
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if (type>0)
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{
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if (EaCanWrite(tea)==0) return 1;
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}
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use=OpBase(op,size);
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use&=~0x0e00; // Use same handler for all registers
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if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
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OpStart(op,tea);
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if(type==1||type==3) {
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Cycles=8;
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} else {
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Cycles=type?8:4;
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if(size>=2) Cycles+=2;
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}
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EaCalcReadNoSE(-1,11,sea,0,0x0e00);
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EaCalcReadNoSE((type>0)?8:-1,0,tea,size,0x003f);
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if (tea>=0x10)
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ot(" and r11,r11,#7 ;@ mem - do mod 8\n"); // size always 0
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else ot(" and r11,r11,#31 ;@ reg - do mod 32\n"); // size always 2
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ot("\n");
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ot(" mov r1,#1\n");
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ot(" tst r0,r1,lsl r11 ;@ Do arithmetic\n");
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ot(" bicne r10,r10,#0x40000000\n");
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ot(" orreq r10,r10,#0x40000000 ;@ Get Z flag\n");
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ot("\n");
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if (type>0)
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{
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if (type==1) ot(" eor r1,r0,r1,lsl r11 ;@ Toggle bit\n");
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if (type==2) ot(" bic r1,r0,r1,lsl r11 ;@ Clear bit\n");
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if (type==3) ot(" orr r1,r0,r1,lsl r11 ;@ Set bit\n");
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ot("\n");
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EaWrite(8,1,tea,size,0x003f,0,0);
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}
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OpEnd(tea);
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return 0;
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}
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// --------------------- Opcodes 0x0800+ ---------------------
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// Emit a Btst/Bchg/Bclr/Bset (Immediate) opcode 00001000 ttaaaaaa nn
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int OpBtstImm(int op)
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{
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int type=0,sea=0,tea=0;
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int use=0;
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int size=0;
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type=(op>>6)&3;
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// Get source and target EA
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sea= 0x003c;
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tea=op&0x003f;
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if (tea<0x10) size=2; // For registers, 32-bits
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// See if we can do this opcode:
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if (EaCanRead(tea,0)==0||EaAn(tea)||tea==0x3c) return 1;
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if (type>0)
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{
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if (EaCanWrite(tea)==0) return 1;
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}
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use=OpBase(op,size);
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if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
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OpStart(op,sea,tea);
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ot("\n");
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EaCalcReadNoSE(-1,0,sea,0,0);
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ot(" mov r11,#1\n");
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ot(" bic r10,r10,#0x40000000 ;@ Blank Z flag\n");
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if (tea>=0x10)
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ot(" and r0,r0,#7 ;@ mem - do mod 8\n"); // size always 0
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else ot(" and r0,r0,#0x1F ;@ reg - do mod 32\n"); // size always 2
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ot(" mov r11,r11,lsl r0 ;@ Make bit mask\n");
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ot("\n");
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if(type==1||type==3) {
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Cycles=12;
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} else {
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Cycles=type?12:8;
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if(size>=2) Cycles+=2;
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}
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EaCalcReadNoSE((type>0)?8:-1,0,tea,size,0x003f);
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ot(" tst r0,r11 ;@ Do arithmetic\n");
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ot(" orreq r10,r10,#0x40000000 ;@ Get Z flag\n");
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ot("\n");
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if (type>0)
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{
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if (type==1) ot(" eor r1,r0,r11 ;@ Toggle bit\n");
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if (type==2) ot(" bic r1,r0,r11 ;@ Clear bit\n");
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if (type==3) ot(" orr r1,r0,r11 ;@ Set bit\n");
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ot("\n");
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EaWrite(8, 1,tea,size,0x003f,0,0);
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#if CYCLONE_FOR_GENESIS && !MEMHANDLERS_CHANGE_CYCLES
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// this is a bit hacky (device handlers might modify cycles)
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if (tea==0x38||tea==0x39)
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ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");
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#endif
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}
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OpEnd(sea,tea);
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return 0;
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}
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// --------------------- Opcodes 0x4000+ ---------------------
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int OpNeg(int op)
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{
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// 01000tt0 xxeeeeee (tt=negx/clr/neg/not, xx=size, eeeeee=EA)
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int type=0,size=0,ea=0,use=0;
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type=(op>>9)&3;
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ea =op&0x003f;
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size=(op>>6)&3; if (size>=3) return 1;
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// See if we can do this opcode:
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if (EaCanRead (ea,size)==0||EaAn(ea)) return 1;
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if (EaCanWrite(ea )==0) return 1;
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use=OpBase(op,size);
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if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
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OpStart(op,ea); Cycles=size<2?4:6;
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if(ea >= 0x10) Cycles*=2;
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EaCalc (11,0x003f,ea,size,0,0);
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if (type!=1) EaRead (11,0,ea,size,0x003f,0,0); // Don't need to read for 'clr' (or do we, for a dummy read?)
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if (type==1) ot("\n");
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if (type==0)
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{
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ot(";@ Negx:\n");
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GetXBit(1);
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if(size!=2) ot(" mov r0,r0,asl #%i\n",size?16:24);
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ot(" rscs r1,r0,#0 ;@ do arithmetic\n");
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ot(" orr r3,r10,#0xb0000000 ;@ for old Z\n");
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OpGetFlags(1,1,0);
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if(size!=2) {
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ot(" movs r1,r1,asr #%i\n",size?16:24);
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ot(" orreq r10,r10,#0x40000000 ;@ possily missed Z\n");
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}
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ot(" andeq r10,r10,r3 ;@ fix Z\n");
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ot("\n");
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}
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if (type==1)
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{
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ot(";@ Clear:\n");
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ot(" mov r1,#0\n");
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ot(" mov r10,#0x40000000 ;@ NZCV=0100\n");
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ot("\n");
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}
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if (type==2)
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{
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ot(";@ Neg:\n");
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if(size!=2) ot(" mov r0,r0,asl #%i\n",size?16:24);
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ot(" rsbs r1,r0,#0\n");
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OpGetFlags(1,1);
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if(size!=2) ot(" mov r1,r1,asr #%i\n",size?16:24);
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ot("\n");
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}
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if (type==3)
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{
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ot(";@ Not:\n");
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if(size!=2) {
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ot(" mov r0,r0,asl #%i\n",size?16:24);
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ot(" mvn r1,r0,asr #%i\n",size?16:24);
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}
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else
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ot(" mvn r1,r0\n");
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ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");
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OpGetFlags(0,0);
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ot("\n");
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}
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if (type==1) eawrite_check_addrerr=1;
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EaWrite(11, 1,ea,size,0x003f,0,0);
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OpEnd(ea);
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return 0;
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}
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// --------------------- Opcodes 0x4840+ ---------------------
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// Swap, 01001000 01000nnn swap Dn
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int OpSwap(int op)
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{
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int ea=0,use=0;
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ea=op&7;
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use=op&~0x0007; // Use same opcode for all An
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if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
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OpStart(op); Cycles=4;
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EaCalc (11,0x0007,ea,2,1);
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EaRead (11, 0,ea,2,0x0007,1);
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ot(" mov r1,r0,ror #16\n");
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ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");
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OpGetFlags(0,0);
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EaWrite(11, 1,8,2,0x0007,1);
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OpEnd();
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return 0;
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}
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// --------------------- Opcodes 0x4a00+ ---------------------
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// Emit a Tst opcode, 01001010 xxeeeeee
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int OpTst(int op)
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{
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int sea=0;
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int size=0,use=0;
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sea=op&0x003f;
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size=(op>>6)&3; if (size>=3) return 1;
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// See if we can do this opcode:
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if (EaCanWrite(sea)==0||EaAn(sea)) return 1;
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use=OpBase(op,size);
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if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
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OpStart(op,sea); Cycles=4;
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EaCalc ( 0,0x003f,sea,size,1);
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EaRead ( 0, 0,sea,size,0x003f,1);
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ot(" adds r0,r0,#0 ;@ Defines NZ, clears CV\n");
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ot(" mrs r10,cpsr ;@ r10=flags\n");
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ot("\n");
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OpEnd(sea);
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return 0;
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}
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// --------------------- Opcodes 0x4880+ ---------------------
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// Emit an Ext opcode, 01001000 1x000nnn
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int OpExt(int op)
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{
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int ea=0;
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int size=0,use=0;
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int shift=0;
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ea=op&0x0007;
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size=(op>>6)&1;
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shift=32-(8<<size);
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use=OpBase(op,size);
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if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
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OpStart(op); Cycles=4;
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EaCalc (11,0x0007,ea,size+1,0,0);
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EaRead (11, 0,ea,size+1,0x0007,0,0);
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ot(" mov r0,r0,asl #%d\n",shift);
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ot(" adds r0,r0,#0 ;@ Defines NZ, clears CV\n");
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ot(" mrs r10,cpsr ;@ r10=flags\n");
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ot(" mov r1,r0,asr #%d\n",shift);
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ot("\n");
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EaWrite(11, 1,ea,size+1,0x0007,0,0);
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OpEnd();
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return 0;
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}
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// --------------------- Opcodes 0x50c0+ ---------------------
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// Emit a Set cc opcode, 0101cccc 11eeeeee
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int OpSet(int op)
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{
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int cc=0,ea=0;
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int size=0,use=0,changed_cycles=0;
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static const char * const cond[16]=
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{
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"al","", "hi","ls","cc","cs","ne","eq",
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"vc","vs","pl","mi","ge","lt","gt","le"
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};
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cc=(op>>8)&15;
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ea=op&0x003f;
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if ((ea&0x38)==0x08) return 1; // dbra, not scc
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// See if we can do this opcode:
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if (EaCanWrite(ea)==0) return 1;
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use=OpBase(op,size);
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if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
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changed_cycles=ea<8 && cc>=2;
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OpStart(op,ea,0,changed_cycles); Cycles=8;
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if (ea<8) Cycles=4;
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if (cc)
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ot(" mov r1,#0\n");
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switch (cc)
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{
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case 0: // T
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ot(" mvn r1,#0\n");
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if (ea<8) Cycles+=2;
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break;
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case 1: // F
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break;
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case 2: // hi
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ot(" tst r10,#0x60000000 ;@ hi: !C && !Z\n");
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ot(" mvneq r1,r1\n");
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if (ea<8) ot(" subeq r5,r5,#2 ;@ Extra cycles\n");
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break;
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case 3: // ls
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ot(" tst r10,#0x60000000 ;@ ls: C || Z\n");
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ot(" mvnne r1,r1\n");
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if (ea<8) ot(" subne r5,r5,#2 ;@ Extra cycles\n");
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break;
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default:
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ot(";@ Is the condition true?\n");
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ot(" msr cpsr_flg,r10 ;@ ARM flags = 68000 flags\n");
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ot(" mvn%s r1,r1\n",cond[cc]);
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if (ea<8) ot(" sub%s r5,r5,#2 ;@ Extra cycles\n",cond[cc]);
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break;
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}
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ot("\n");
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eawrite_check_addrerr=1;
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EaCalc (0,0x003f, ea,size,0,0);
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EaWrite(0, 1, ea,size,0x003f,0,0);
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opend_op_changes_cycles=changed_cycles;
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OpEnd(ea,0);
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return 0;
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}
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// Emit a Asr/Lsr/Roxr/Ror opcode
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static int EmitAsr(int op,int type,int dir,int count,int size,int usereg)
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{
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char pct[8]=""; // count
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int shift=32-(8<<size);
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if (count>=1) sprintf(pct,"#%d",count); // Fixed count
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if (usereg)
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{
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ot(";@ Use Dn for count:\n");
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ot(" and r2,r8,#0x0e00\n");
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ot(" ldr r2,[r7,r2,lsr #7]\n");
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ot(" and r2,r2,#63\n");
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ot("\n");
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strcpy(pct,"r2");
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}
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else if (count<0)
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{
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ot(" mov r2,r8,lsr #9 ;@ Get 'n'\n");
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ot(" and r2,r2,#7\n\n"); strcpy(pct,"r2");
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}
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// Take 2*n cycles:
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if (count<0) ot(" sub r5,r5,r2,asl #1 ;@ Take 2*n cycles\n\n");
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else Cycles+=count<<1;
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if (type<2)
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{
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// Asr/Lsr
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if (dir==0 && size<2)
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{
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ot(";@ For shift right, use loworder bits for the operation:\n");
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ot(" mov r0,r0,%s #%d\n",type?"lsr":"asr",32-(8<<size));
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ot("\n");
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}
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if (type==0 && dir) ot(" adds r3,r0,#0 ;@ save old value for V flag calculation, also clear V\n");
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ot(";@ Shift register:\n");
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if (type==0) ot(" movs r0,r0,%s %s\n",dir?"asl":"asr",pct);
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if (type==1) ot(" movs r0,r0,%s %s\n",dir?"lsl":"lsr",pct);
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OpGetFlags(0,0);
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if (usereg) { // store X only if count is not 0
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ot(" cmp %s,#0 ;@ shifting by 0?\n",pct);
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ot(" biceq r10,r10,#0x20000000 ;@ if so, clear carry\n");
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ot(" strne r10,[r7,#0x4c] ;@ else Save X bit\n");
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} else {
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// count will never be 0 if we use immediate
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ot(" str r10,[r7,#0x4c] ;@ Save X bit\n");
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}
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ot("\n");
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if (dir==0 && size<2)
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{
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ot(";@ restore after right shift:\n");
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ot(" movs r0,r0,lsl #%d\n",32-(8<<size));
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if (type)
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ot(" orrmi r10,r10,#0x80000000 ;@ Potentially missed N flag\n");
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ot("\n");
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}
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if (type==0 && dir) {
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ot(";@ calculate V flag (set if sign bit changes at anytime):\n");
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ot(" mov r1,#0x80000000\n");
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ot(" ands r3,r3,r1,asr %s\n", pct);
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ot(" cmpne r3,r1,asr %s\n", pct);
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ot(" eoreq r1,r0,r3\n"); // above check doesn't catch (-1)<<(32+), so we need this
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ot(" tsteq r1,#0x80000000\n");
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ot(" orrne r10,r10,#0x10000000\n");
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ot("\n");
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}
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}
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// --------------------------------------
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if (type==2)
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{
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int wide=8<<size;
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// Roxr
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if(count == 1)
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{
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if(dir==0) {
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if(size!=2) {
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ot(" orr r0,r0,r0,lsr #%i\n", size?16:24);
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ot(" bic r0,r0,#0x%x\n", 1<<(32-wide));
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}
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GetXBit(0);
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ot(" movs r0,r0,rrx\n");
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OpGetFlags(0,1);
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} else {
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ot(" ldr r3,[r7,#0x4c]\n");
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ot(" movs r0,r0,lsl #1\n");
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OpGetFlags(0,1);
|
|
ot(" tst r3,#0x20000000\n");
|
|
ot(" orrne r0,r0,#0x%x\n", 1<<(32-wide));
|
|
ot(" bicne r10,r10,#0x40000000 ;@ clear Z in case it got there\n");
|
|
}
|
|
ot(" bic r10,r10,#0x10000000 ;@ make suve V is clear\n");
|
|
return 0;
|
|
}
|
|
|
|
if (usereg)
|
|
{
|
|
if (size==2)
|
|
{
|
|
ot(" subs r2,r2,#33\n");
|
|
ot(" addmis r2,r2,#33 ;@ Now r2=0-%d\n",wide);
|
|
}
|
|
else
|
|
{
|
|
ot(";@ Reduce r2 until <0:\n");
|
|
ot("Reduce_%.4x%s\n",op,ms?"":":");
|
|
ot(" subs r2,r2,#%d\n",wide+1);
|
|
ot(" bpl Reduce_%.4x\n",op);
|
|
ot(" adds r2,r2,#%d ;@ Now r2=0-%d\n",wide+1,wide);
|
|
}
|
|
ot(" beq norotx_%.4x\n",op);
|
|
ot("\n");
|
|
}
|
|
|
|
if (usereg||count < 0)
|
|
{
|
|
if (dir) ot(" rsb r2,r2,#%d ;@ Reverse direction\n",wide+1);
|
|
}
|
|
else
|
|
{
|
|
if (dir) ot(" mov r2,#%d ;@ Reversed\n",wide+1-count);
|
|
else ot(" mov r2,#%d\n",count);
|
|
}
|
|
|
|
if (shift) ot(" mov r0,r0,lsr #%d ;@ Shift down\n",shift);
|
|
|
|
ot("\n");
|
|
ot(";@ First get X bit (middle):\n");
|
|
ot(" ldr r3,[r7,#0x4c]\n");
|
|
ot(" rsb r1,r2,#%d\n",wide);
|
|
ot(" and r3,r3,#0x20000000\n");
|
|
ot(" mov r3,r3,lsr #29\n");
|
|
ot(" mov r3,r3,lsl r1\n");
|
|
|
|
ot(";@ Rotate bits:\n");
|
|
ot(" orr r3,r3,r0,lsr r2 ;@ Orr right part\n");
|
|
ot(" rsbs r2,r2,#%d ;@ should also clear ARM V\n",wide+1);
|
|
ot(" orrs r0,r3,r0,lsl r2 ;@ Orr left part, set flags\n");
|
|
ot("\n");
|
|
|
|
if (shift) ot(" movs r0,r0,lsl #%d ;@ Shift up and get correct NC flags\n",shift);
|
|
OpGetFlags(0,!usereg);
|
|
if (usereg) { // store X only if count is not 0
|
|
ot(" str r10,[r7,#0x4c] ;@ if not 0, Save X bit\n");
|
|
ot(" b nozerox%.4x\n",op);
|
|
ot("norotx_%.4x%s\n",op,ms?"":":");
|
|
ot(" ldr r2,[r7,#0x4c]\n");
|
|
ot(" adds r0,r0,#0 ;@ Defines NZ, clears CV\n");
|
|
OpGetFlags(0,0);
|
|
ot(" and r2,r2,#0x20000000\n");
|
|
ot(" orr r10,r10,r2 ;@ C = old_X\n");
|
|
ot("nozerox%.4x%s\n",op,ms?"":":");
|
|
}
|
|
|
|
ot("\n");
|
|
}
|
|
|
|
// --------------------------------------
|
|
if (type==3)
|
|
{
|
|
// Ror
|
|
if (size<2)
|
|
{
|
|
ot(";@ Mirror value in whole 32 bits:\n");
|
|
if (size<=0) ot(" orr r0,r0,r0,lsr #8\n");
|
|
if (size<=1) ot(" orr r0,r0,r0,lsr #16\n");
|
|
ot("\n");
|
|
}
|
|
|
|
ot(";@ Rotate register:\n");
|
|
if (!dir) ot(" adds r0,r0,#0 ;@ first clear V and C\n"); // ARM does not clear C if rot count is 0
|
|
if (count<0)
|
|
{
|
|
if (dir) ot(" rsb %s,%s,#32\n",pct,pct);
|
|
ot(" movs r0,r0,ror %s\n",pct);
|
|
}
|
|
else
|
|
{
|
|
int ror=count;
|
|
if (dir) ror=32-ror;
|
|
if (ror&31) ot(" movs r0,r0,ror #%d\n",ror);
|
|
}
|
|
|
|
OpGetFlags(0,0);
|
|
if (dir)
|
|
{
|
|
ot(" bic r10,r10,#0x30000000 ;@ clear CV\n");
|
|
ot(";@ Get carry bit from bit 0:\n");
|
|
if (usereg)
|
|
{
|
|
ot(" cmp %s,#32 ;@ rotating by 0?\n",pct);
|
|
ot(" tstne r0,#1 ;@ no, check bit 0\n");
|
|
}
|
|
else
|
|
ot(" tst r0,#1\n");
|
|
ot(" orrne r10,r10,#0x20000000\n");
|
|
}
|
|
ot("\n");
|
|
|
|
}
|
|
// --------------------------------------
|
|
|
|
return 0;
|
|
}
|
|
|
|
// Emit a Asr/Lsr/Roxr/Ror opcode - 1110cccd xxuttnnn
|
|
// (ccc=count, d=direction(r,l) xx=size extension, u=use reg for count, tt=type, nnn=register Dn)
|
|
int OpAsr(int op)
|
|
{
|
|
int ea=0,use=0;
|
|
int count=0,dir=0;
|
|
int size=0,usereg=0,type=0;
|
|
|
|
count =(op>>9)&7;
|
|
dir =(op>>8)&1;
|
|
size =(op>>6)&3;
|
|
if (size>=3) return 1; // use OpAsrEa()
|
|
usereg=(op>>5)&1;
|
|
type =(op>>3)&3;
|
|
|
|
if (usereg==0) count=((count-1)&7)+1; // because ccc=000 means 8
|
|
|
|
// Use the same opcode for target registers:
|
|
use=op&~0x0007;
|
|
|
|
// As long as count is not 8, use the same opcode for all shift counts:
|
|
if (usereg==0 && count!=8 && !(count==1&&type==2)) { use|=0x0e00; count=-1; }
|
|
if (usereg) { use&=~0x0e00; count=-1; } // Use same opcode for all Dn
|
|
|
|
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
|
|
|
|
OpStart(op,ea,0,count<0); Cycles=size<2?6:8;
|
|
|
|
EaCalc(11,0x0007, ea,size,1);
|
|
EaRead(11, 0, ea,size,0x0007,1);
|
|
|
|
EmitAsr(op,type,dir,count, size,usereg);
|
|
|
|
EaWrite(11, 0, ea,size,0x0007,1);
|
|
|
|
opend_op_changes_cycles = (count<0);
|
|
OpEnd(ea,0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
// Asr/Lsr/Roxr/Ror etc EA - 11100ttd 11eeeeee
|
|
int OpAsrEa(int op)
|
|
{
|
|
int use=0,type=0,dir=0,ea=0,size=1;
|
|
|
|
type=(op>>9)&3;
|
|
dir =(op>>8)&1;
|
|
ea = op&0x3f;
|
|
|
|
if (ea<0x10) return 1;
|
|
// See if we can do this opcode:
|
|
if (EaCanRead(ea,0)==0) return 1;
|
|
if (EaCanWrite(ea)==0) return 1;
|
|
|
|
use=OpBase(op,size);
|
|
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
|
|
|
|
OpStart(op,ea); Cycles=6; // EmitAsr() will add 2
|
|
|
|
EaCalc (11,0x003f,ea,size,1);
|
|
EaRead (11, 0,ea,size,0x003f,1);
|
|
|
|
EmitAsr(op,type,dir,1,size,0);
|
|
|
|
EaWrite(11, 0,ea,size,0x003f,1);
|
|
|
|
OpEnd(ea);
|
|
return 0;
|
|
}
|
|
|
|
int OpTas(int op, int gen_special)
|
|
{
|
|
int ea=0;
|
|
int use=0;
|
|
|
|
ea=op&0x003f;
|
|
|
|
// See if we can do this opcode:
|
|
if (EaCanWrite(ea)==0 || EaAn(ea)) return 1;
|
|
|
|
use=OpBase(op,0);
|
|
if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
|
|
|
|
if (!gen_special) OpStart(op,ea);
|
|
else
|
|
ot("Op%.4x_%s\n", op, ms?"":":");
|
|
|
|
Cycles=4;
|
|
if(ea>=8) Cycles+=10;
|
|
|
|
EaCalc (11,0x003f,ea,0,1);
|
|
EaRead (11, 1,ea,0,0x003f,1);
|
|
|
|
ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");
|
|
OpGetFlags(0,0);
|
|
ot("\n");
|
|
|
|
#if CYCLONE_FOR_GENESIS
|
|
// the original Sega hardware ignores write-back phase (to memory only)
|
|
if (ea < 0x10 || gen_special) {
|
|
#endif
|
|
ot(" orr r1,r1,#0x80000000 ;@ set bit7\n");
|
|
|
|
EaWrite(11, 1,ea,0,0x003f,1);
|
|
#if CYCLONE_FOR_GENESIS
|
|
}
|
|
#endif
|
|
|
|
OpEnd(ea);
|
|
|
|
#if (CYCLONE_FOR_GENESIS == 2)
|
|
if (!gen_special && ea >= 0x10) {
|
|
OpTas(op, 1);
|
|
}
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|