mirror of
https://git.missingno.dev/kolibrios-nvme-driver/
synced 2024-11-12 19:27:28 +01:00
lots of refactoring
This commit is contained in:
parent
7782f762ef
commit
8f806cfb6f
@ -181,10 +181,6 @@ proc is_active_namespace stdcall, pci:dword, nsid:dword
|
||||
invoke GetPhysAddr
|
||||
DEBUGF DBG_INFO, "Identify Namespace: %u\n", [nsid]
|
||||
stdcall nvme_identify, [pci], [nsid], eax, CNS_IDNS
|
||||
push esi
|
||||
mov esi, 130
|
||||
invoke Sleep
|
||||
pop esi
|
||||
xor ecx, ecx
|
||||
|
||||
@@:
|
||||
@ -203,9 +199,9 @@ proc is_active_namespace stdcall, pci:dword, nsid:dword
|
||||
ret
|
||||
|
||||
.is_active_nsid:
|
||||
DEBUGF DBG_INFO, "ACTIVE NSID: %u\n", [nsid]
|
||||
cmp [nsid], 1
|
||||
jne @b
|
||||
;DEBUGF DBG_INFO, "ACTIVE NSID: %u\n", [nsid]
|
||||
;cmp [nsid], 1
|
||||
;jne @b
|
||||
invoke KernelFree, esi
|
||||
pop edi esi
|
||||
xor eax, eax
|
||||
@ -625,8 +621,11 @@ proc nvme_init stdcall, pci:dword
|
||||
mov dword [edi + NVME_MMIO.ACQ], eax
|
||||
and dword [edi + NVME_MMIO.ACQ + 4], 0
|
||||
|
||||
stdcall memset, dword [esi + NVM_QUEUE_ENTRY.sq_ptr], 0, sizeof.SQ_ENTRY * NVM_CMDS
|
||||
stdcall memset, dword [esi + NVM_QUEUE_ENTRY.cq_ptr], 0, sizeof.CQ_ENTRY * NVM_CMDS
|
||||
stdcall memset, dword [esi + NVM_QUEUE_ENTRY.sq_ptr], 0, sizeof.SQ_ENTRY * NVM_ASQS
|
||||
stdcall memset, dword [esi + NVM_QUEUE_ENTRY.cq_ptr], 0, sizeof.CQ_ENTRY * NVM_ACQS
|
||||
mov dword [esi + NVM_QUEUE_ENTRY.phase_tag], CQ_PHASE_TAG
|
||||
|
||||
; TODO: memset the I/O queues as well
|
||||
|
||||
pop esi
|
||||
|
||||
@ -740,7 +739,7 @@ proc get_new_cid stdcall, pci:dword, y:dword
|
||||
mov esi, [esi + pcidev.queue_entries]
|
||||
mov ecx, [y]
|
||||
imul ecx, sizeof.NVM_QUEUE_ENTRY
|
||||
mov eax, dword [esi + ecx + NVM_QUEUE_ENTRY.tail]
|
||||
movzx eax, word [esi + ecx + NVM_QUEUE_ENTRY.tail]
|
||||
pop esi
|
||||
ret
|
||||
|
||||
@ -768,7 +767,7 @@ proc nvme_controller_start stdcall, mmio:dword
|
||||
DEBUGF DBG_INFO, "(NVMe) Starting Controller...\n"
|
||||
push edi
|
||||
mov edi, dword [mmio]
|
||||
or dword [edi + NVME_MMIO.CC], 1 ;; CC.EN = 1
|
||||
or dword [edi + NVME_MMIO.CC], 1 ; CC.EN = 1
|
||||
|
||||
; Wait for controller to be brought into active state, CSTS.RDY should be set to 1 when this happens
|
||||
.wait:
|
||||
@ -796,13 +795,13 @@ proc nvme_wait stdcall, mmio:dword
|
||||
endp
|
||||
|
||||
; Writes to completion queue 'y' head doorbell
|
||||
proc cqyhdbl_write stdcall, pci:dword, y:word, cqh:word
|
||||
proc cqyhdbl_write stdcall, pci:dword, y:dword, cqh:word
|
||||
|
||||
push esi edi
|
||||
mov esi, [pci]
|
||||
|
||||
; 1000h + ((2y + 1) * (4 << CAP.DSTRD))
|
||||
movzx eax, [y]
|
||||
mov eax, [y]
|
||||
shl al, 1
|
||||
inc al
|
||||
mov edx, 4
|
||||
@ -810,7 +809,7 @@ proc cqyhdbl_write stdcall, pci:dword, y:word, cqh:word
|
||||
shl dx, cl
|
||||
imul dx, ax
|
||||
add dx, 0x1000
|
||||
movzx ecx, [y]
|
||||
mov ecx, [y]
|
||||
imul ecx, sizeof.NVM_QUEUE_ENTRY
|
||||
mov edi, dword [esi + pcidev.queue_entries]
|
||||
lea edi, dword [edi + ecx]
|
||||
@ -843,7 +842,7 @@ proc sqytdbl_write stdcall, pci:dword, y:word, cmd:dword
|
||||
mov edi, [pci]
|
||||
mov esi, dword [edi + pcidev.io_addr]
|
||||
mov edi, dword [edi + pcidev.queue_entries]
|
||||
mov ax, word [edi + NVM_QUEUE_ENTRY.tail]
|
||||
movzx eax, word [edi + NVM_QUEUE_ENTRY.tail]
|
||||
cmp ax, NVM_ASQS
|
||||
jl @f
|
||||
xor ax, ax
|
||||
@ -890,7 +889,7 @@ proc pow2 stdcall, x:byte
|
||||
|
||||
endp
|
||||
|
||||
proc nvme_cmd_wait stdcall, pci:dword, y:dword, cid:dword
|
||||
proc nvme_cmd_wait stdcall, pci:dword, y:dword, cid:word
|
||||
|
||||
push esi
|
||||
mov esi, [pci]
|
||||
@ -900,12 +899,20 @@ proc nvme_cmd_wait stdcall, pci:dword, y:dword, cid:dword
|
||||
mov esi, dword [esi + pcidev.queue_entries]
|
||||
lea esi, [esi + edx]
|
||||
imul ecx, sizeof.CQ_ENTRY
|
||||
mov eax, dword [esi + NVM_QUEUE_ENTRY.phase_tag]
|
||||
mov esi, dword [esi + NVM_QUEUE_ENTRY.cq_ptr]
|
||||
|
||||
; WARNING: status bit flips on each pass, count for this later...
|
||||
test eax, CQ_PHASE_TAG
|
||||
jnz .phase_tag_1
|
||||
|
||||
@@:
|
||||
test byte [esi + ecx + CQ_ENTRY.status], CQ_PHASE_TAG
|
||||
jnz @b
|
||||
pop esi
|
||||
ret
|
||||
|
||||
.phase_tag_1:
|
||||
test byte [esi + ecx + CQ_ENTRY.status], CQ_PHASE_TAG
|
||||
jz @b
|
||||
jz .phase_tag_1
|
||||
pop esi
|
||||
ret
|
||||
|
||||
@ -942,10 +949,10 @@ proc irq_handler
|
||||
jz .ok
|
||||
|
||||
.error:
|
||||
jmp @b
|
||||
; we have to initiate a controller reset if a admin command encounters
|
||||
; a fatal error or if a completion is not received for a deletion
|
||||
; of a submission or completion queue (section 10.1 - page 400 of NVMe 1.4 spec)
|
||||
jmp @b
|
||||
;mov esi, dword [p_nvme_devices]
|
||||
;mov esi, dword [esi + pcidev.io_addr]
|
||||
;stdcall nvme_controller_reset, esi
|
||||
@ -957,7 +964,16 @@ proc irq_handler
|
||||
inc ecx
|
||||
cmp ecx, NVM_ACQS
|
||||
jng @f
|
||||
mov esi, dword [p_nvme_devices]
|
||||
mov esi, dword [esi + pcidev.queue_entries]
|
||||
mov eax, dword [esi + NVM_QUEUE_ENTRY.phase_tag]
|
||||
not eax
|
||||
and eax, 0x1
|
||||
DEBUGF DBG_INFO, "eax: %u\n", eax
|
||||
mov dword [esi + NVM_QUEUE_ENTRY.phase_tag], eax
|
||||
xor ecx, ecx
|
||||
inc ecx
|
||||
|
||||
@@:
|
||||
; TODO: Check how many commands were consumed later
|
||||
stdcall cqyhdbl_write, dword [p_nvme_devices], 0, ecx
|
||||
|
||||
@ -332,6 +332,7 @@ struct NVM_QUEUE_ENTRY
|
||||
sq_ptr dd ?
|
||||
cq_ptr dd ?
|
||||
cid_slots dq ?
|
||||
phase_tag dd ?
|
||||
ends
|
||||
|
||||
; Identify Controller Data Structure
|
||||
|
||||
Loading…
Reference in New Issue
Block a user