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https://git.missingno.dev/kolibrios-nvme-driver/
synced 2024-11-10 02:20:27 +01:00
refactor some stuff
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@ -31,3 +31,4 @@
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/drivers/*.inc
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/drivers/*.asm
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/drivers/**/*.sys
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/nvme.c
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@ -555,11 +555,11 @@ proc nvme_init stdcall, pci:dword
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stdcall memset, dword [esi + pcidev.cq_ptr], 0, sizeof.CQ_ENTRY * NVM_ACQS
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; Allocate list of queues
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invoke KernelAlloc, sizeof.NVM_QUEUE * NVM_ASQS
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invoke KernelAlloc, sizeof.NVM_QUEUE_ENTRY * NVM_ASQS
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test eax, eax
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jz .exit_fail
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mov dword [esi + pcidev.queue_ptr], eax
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stdcall memset, eax, 0, sizeof.NVM_QUEUE * NVM_ASQS
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mov dword [esi + pcidev.queue_entries], eax
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stdcall memset, eax, 0, sizeof.NVM_QUEUE_ENTRY * NVM_ASQS
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; we want to disable all interrupts for now, since the controller randomly
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; generates interrupts while starting up
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@ -598,6 +598,40 @@ proc nvme_init stdcall, pci:dword
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endp
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proc get_avl_cmd stdcall, pci:dword, y:dword
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push esi ebx
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mov esi, [pci]
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mov ecx, [y]
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mov eax, dword [esi + ecx * pcidev.queue_entries + NVM_QUEUE_ENTRY.cid_slots]
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xor edx, edx
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cmp eax, 0xffffffff
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jne @f
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mov eax, dword [esi + ecx * pcidev.queue_entries + NVM_QUEUE_ENTRY.cid_slots + 4]
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add edx, 4
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cmp eax, 0xffffffff
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jne @f
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pop esi
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mov eax, -1
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ret
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@@:
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mov ebx, eax
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; Equivalant to (~(-X) & ~(X)), retrieves first free bit
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not eax
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mov ecx, eax
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neg ecx
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and eax, ecx
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or ebx, eax
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mov ecx, [y]
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mov dword [esi + ecx * pcidev.queue_entries + NVM_QUEUE_ENTRY.cid_slots + edx], ebx
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pop ebx esi
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ret
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endp
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proc nvme_controller_reset stdcall, mmio:dword
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DEBUGF DBG_INFO, "(NVMe) Resetting Controller...\n"
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@ -642,7 +676,7 @@ proc nvme_wait stdcall, mmio:dword
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mov esi, dword [esi + NVME_MMIO.CAP]
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and esi, CAP_TO
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shr esi, 24
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imul esi, 100 ; TODO: bad time delay, set to appropriate value later
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imul esi, 150 ; TODO: bad time delay, set to appropriate value later
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invoke Sleep
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pop esi
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ret
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@ -675,7 +709,7 @@ proc sqytdbl_write stdcall, pci:dword, y:byte, sqt:word
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endp
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; Writes to completion queue 'y' head doorbell
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proc cqyhdbl_write stdcall, pci:dword, y:byte
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proc cqyhdbl_write stdcall, pci:dword, y:byte, cqh:word
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push esi edi
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mov esi, [pci]
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@ -684,25 +718,18 @@ proc cqyhdbl_write stdcall, pci:dword, y:byte
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movzx eax, [y]
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shl al, 1
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inc al
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mov dx, 4
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mov edx, 4
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mov cl, byte [esi + pcidev.dstrd]
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shl dx, cl
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imul dx, ax
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add dx, 0x1000
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movzx ecx, [y]
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mov edi, dword [esi + pcidev.queue_ptr]
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mov ax, word [edi + ecx * sizeof.NVM_QUEUE + NVM_QUEUE.head] ; get head for completion queue Y
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cmp ax, NVM_ACQS
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jl @f
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xor ax, ax
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@@:
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inc ax
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mov edi, dword [esi + pcidev.queue_entries]
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mov esi, dword [esi + pcidev.io_addr]
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mov ax, [cqh]
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DEBUGF DBG_INFO, "(NVMe) Writing to completion queue doorbell register 0x%x: %u\n", dx, ax
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mov word [esi + edx], ax ; Write to CQyHDBL
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mov word [edi + ecx * sizeof.NVM_QUEUE + NVM_QUEUE.head], ax
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mov word [edi + ecx * sizeof.NVM_QUEUE_ENTRY + NVM_QUEUE_ENTRY.head], ax
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pop edi esi
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ret
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@ -712,8 +739,8 @@ proc write_admin_cmd stdcall, pci:dword
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push esi
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mov esi, [pci]
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mov esi, dword [esi + pcidev.queue_ptr]
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mov ax, word [esi + NVM_QUEUE.tail]
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mov esi, dword [esi + pcidev.queue_entries]
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mov ax, word [esi + NVM_QUEUE_ENTRY.tail]
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cmp ax, NVM_ASQS
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jl @f
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xor ax, ax
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@ -723,7 +750,7 @@ proc write_admin_cmd stdcall, pci:dword
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mov esi, dword [esi + pcidev.io_addr]
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inc ax
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mov word [esi + 0x1000], ax
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mov word [esi + NVM_QUEUE.tail], ax
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mov word [esi + NVM_QUEUE_ENTRY.tail], ax
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pop esi
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ret
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@ -773,7 +800,7 @@ proc irq_handler
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@@:
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mov dword [esi + NVME_MMIO.INTMC], 0x1
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stdcall cqyhdbl_write, [p_nvme_devices], 0
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stdcall cqyhdbl_write, [p_nvme_devices], 0x0, 0x1
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.exit:
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; Interrupt handled by driver, return 1
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@ -16,6 +16,7 @@ VS121 = 0x00010201 ; (v1.2.1)
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VS130 = 0x00010300 ; (v1.3.0)
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VS140 = 0x00010400 ; (v1.4.0)
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NVM_CMDS = 64 ; Number of Commands
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NVM_MPS = 0 ; Memory Page Size (2 ^ (12 + MPS))
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NVM_ASQS = 2 ; Admin Submission Queue Size
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NVM_ACQS = NVM_ASQS ; Admin Completion Queue Size
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@ -301,7 +302,7 @@ struct pcidev
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io_addr dd ?
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sq_ptr dd ?
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cq_ptr dd ?
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queue_ptr dd ?
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queue_entries dd ?
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pc db ?
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dstrd db ?
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rb 2 ; align
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@ -309,9 +310,16 @@ ends
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TOTAL_PCIDEVS = 4
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TOTAL_PCIDEVS_MALLOC_SZ = TOTAL_PCIDEVS * sizeof.pcidev
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struct NVM_QUEUE
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struct DPTR
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prp1 dd ?
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prp2 dd ?
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ends
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struct NVM_QUEUE_ENTRY
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tail dw ?
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head dw ?
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dptr dd ?
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;cid_slots dq ?
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ends
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; Identify Controller Data Structure
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