refactor some stuff

.gitignore

@@ -31,3 +31,4 @@
 /drivers/*.inc
 /drivers/*.asm
 /drivers/**/*.sys
+/nvme.c

drivers/nvme/nvme.asm

@@ -555,11 +555,11 @@ proc nvme_init stdcall, pci:dword
 		stdcall memset, dword [esi + pcidev.cq_ptr], 0, sizeof.CQ_ENTRY * NVM_ACQS
 
 		; Allocate list of queues
-		invoke  KernelAlloc, sizeof.NVM_QUEUE * NVM_ASQS
+		invoke  KernelAlloc, sizeof.NVM_QUEUE_ENTRY * NVM_ASQS
 		test 	eax, eax
 		jz 		.exit_fail
-		mov 	dword [esi + pcidev.queue_ptr], eax
+		mov 	dword [esi + pcidev.queue_entries], eax
-		stdcall memset, eax, 0, sizeof.NVM_QUEUE * NVM_ASQS
+		stdcall memset, eax, 0, sizeof.NVM_QUEUE_ENTRY * NVM_ASQS
 
 		; we want to disable all interrupts for now, since the controller randomly
 	    ; generates interrupts while starting up
@@ -598,6 +598,40 @@ proc nvme_init stdcall, pci:dword
 
 endp
 
+proc get_avl_cmd stdcall, pci:dword, y:dword
+		
+		push 	esi ebx
+		mov 	esi, [pci]
+		mov 	ecx, [y]
+		mov 	eax, dword [esi + ecx * pcidev.queue_entries + NVM_QUEUE_ENTRY.cid_slots]
+		xor 	edx, edx
+		cmp 	eax, 0xffffffff
+		jne		@f      	
+		mov 	eax, dword [esi + ecx * pcidev.queue_entries + NVM_QUEUE_ENTRY.cid_slots + 4]
+		add 	edx, 4
+		cmp 	eax, 0xffffffff
+		jne 	@f
+		pop 	esi
+		mov 	eax, -1
+		ret
+
+@@:
+		mov 	ebx, eax
+
+		; Equivalant to (~(-X) & ~(X)), retrieves first free bit
+		not 	eax
+		mov 	ecx, eax
+		neg 	ecx
+		and 	eax, ecx
+		or 		ebx, eax
+
+		mov 	ecx, [y]
+		mov 	dword [esi + ecx * pcidev.queue_entries + NVM_QUEUE_ENTRY.cid_slots + edx], ebx
+		pop 	ebx esi
+		ret
+
+endp
+
 proc nvme_controller_reset stdcall, mmio:dword
 
 		DEBUGF  DBG_INFO, "(NVMe) Resetting Controller...\n"
@@ -642,7 +676,7 @@ proc nvme_wait stdcall, mmio:dword
 		mov 	esi, dword [esi + NVME_MMIO.CAP]
 		and 	esi, CAP_TO
 		shr 	esi, 24
-		imul 	esi, 100 ; TODO: bad time delay, set to appropriate value later
+		imul 	esi, 150 ; TODO: bad time delay, set to appropriate value later
 		invoke  Sleep
 		pop 	esi
 		ret
@@ -675,7 +709,7 @@ proc sqytdbl_write stdcall, pci:dword, y:byte, sqt:word
 endp
 
 ; Writes to completion queue 'y' head doorbell
-proc cqyhdbl_write stdcall, pci:dword, y:byte
+proc cqyhdbl_write stdcall, pci:dword, y:byte, cqh:word
 
 		push 	esi edi
 		mov 	esi, [pci]
@@ -684,25 +718,18 @@ proc cqyhdbl_write stdcall, pci:dword, y:byte
 		movzx 	eax, [y]
 		shl 	al, 1
 		inc 	al
-		mov 	dx, 4
+		mov 	edx, 4
 		mov 	cl, byte [esi + pcidev.dstrd]
 		shl 	dx, cl
 		imul 	dx, ax
 		add 	dx, 0x1000
-
 		movzx 	ecx, [y]
-		mov 	edi, dword [esi + pcidev.queue_ptr]
+		mov 	edi, dword [esi + pcidev.queue_entries]
-		mov 	ax, word [edi + ecx * sizeof.NVM_QUEUE + NVM_QUEUE.head] ; get head for completion queue Y
-		cmp 	ax, NVM_ACQS
-		jl 		@f
-		xor 	ax, ax
-
-@@:
-		inc 	ax
 		mov 	esi, dword [esi + pcidev.io_addr]
+		mov 	ax, [cqh]
 		DEBUGF  DBG_INFO, "(NVMe) Writing to completion queue doorbell register 0x%x: %u\n", dx, ax
 		mov 	word [esi + edx], ax ; Write to CQyHDBL
-		mov 	word [edi + ecx * sizeof.NVM_QUEUE + NVM_QUEUE.head], ax
+		mov 	word [edi + ecx * sizeof.NVM_QUEUE_ENTRY + NVM_QUEUE_ENTRY.head], ax
 		pop 	edi esi
 		ret
 
@@ -712,8 +739,8 @@ proc write_admin_cmd stdcall, pci:dword
 
 		push 	esi
 		mov 	esi, [pci]
-		mov 	esi, dword [esi + pcidev.queue_ptr]
+		mov 	esi, dword [esi + pcidev.queue_entries]
-		mov 	ax, word [esi + NVM_QUEUE.tail]
+		mov 	ax, word [esi + NVM_QUEUE_ENTRY.tail]
 		cmp 	ax, NVM_ASQS
 		jl 		@f
 		xor 	ax, ax
@@ -723,7 +750,7 @@ proc write_admin_cmd stdcall, pci:dword
 		mov 	esi, dword [esi + pcidev.io_addr]
 		inc 	ax
 		mov 	word [esi + 0x1000], ax
-		mov 	word [esi + NVM_QUEUE.tail], ax
+		mov 	word [esi + NVM_QUEUE_ENTRY.tail], ax
 		pop 	esi
 		ret
 
@@ -773,7 +800,7 @@ proc irq_handler
 
 @@:
 		mov 	dword [esi + NVME_MMIO.INTMC], 0x1
-		stdcall cqyhdbl_write, [p_nvme_devices], 0
+		stdcall cqyhdbl_write, [p_nvme_devices], 0x0, 0x1
 
 .exit:
 		; Interrupt handled by driver, return 1

drivers/nvme/nvme.inc

@@ -16,6 +16,7 @@ VS121 = 0x00010201 ; (v1.2.1)
 VS130 = 0x00010300 ; (v1.3.0)
 VS140 = 0x00010400 ; (v1.4.0)
 
+NVM_CMDS = 64       ; Number of Commands
 NVM_MPS = 0         ; Memory Page Size (2 ^ (12 + MPS))
 NVM_ASQS = 2        ; Admin Submission Queue Size
 NVM_ACQS = NVM_ASQS ; Admin Completion Queue Size
@@ -301,7 +302,7 @@ struct pcidev
 	io_addr 		dd ?
 	sq_ptr 			dd ?
 	cq_ptr 			dd ?
-	queue_ptr 		dd ?
+	queue_entries 	dd ?
 	pc 	            db ?
 	dstrd 	        db ?
 				    rb 2 ; align
@@ -309,9 +310,16 @@ ends
 TOTAL_PCIDEVS = 4
 TOTAL_PCIDEVS_MALLOC_SZ = TOTAL_PCIDEVS * sizeof.pcidev
 
-struct NVM_QUEUE
+struct DPTR
+	prp1 			dd ?
+	prp2 			dd ?
+ends
+
+struct NVM_QUEUE_ENTRY
 	tail 			dw ?
 	head 			dw ?
+	dptr 			dd ?
+	;cid_slots 		dq ?
 ends
 
 ; Identify Controller Data Structure