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mirror of https://git.missingno.dev/kolibrios-nvme-driver/ synced 2024-09-19 18:11:03 +02:00

add verbose debug logs

This commit is contained in:
Abdur-Rahman Mansoor 2024-08-09 13:51:52 -04:00
parent aa0a75e715
commit efc5b95250

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@ -429,7 +429,7 @@ proc nvme_readwrite stdcall, ns:dword, buf:dword, start_sector:qword, numsectors
mov eax, [numsectors_ptr]
mov eax, dword [eax]
;DEBUGF DBG_INFO, "buf: %x, start_sector: %u:%u, numsectors: %u\n", [buf], [start_sector + 4], [start_sector], eax
DEBUGF DBG_INFO, "buf: %x, start_sector: %u:%u, numsectors: %u\n", [buf], [start_sector + 4], [start_sector], eax
mov dword [ebx + 4], 0 ; PRP2 entry (0 by default)
mov dword [ebx + 8], edx ; command type (read or write)
mov dword [ebx + 12], eax ; save original numsectors value
@ -445,7 +445,7 @@ proc nvme_readwrite stdcall, ns:dword, buf:dword, start_sector:qword, numsectors
test eax, eax
jz .fail
;DEBUGF DBG_INFO, "PRP1: %x, PRP2: %x\n", [ebx], [ebx + 4]
DEBUGF DBG_INFO, "PRP1: %x, PRP2: %x\n", [ebx], [ebx + 4]
mov eax, dword [start_sector]
; According to the NVMe specification, the NLB field in the I/O read and write
@ -672,9 +672,9 @@ proc nvme_init stdcall, pci:dword
; check maximum queue entries supported
mov eax, dword [edi + NVME_MMIO.CAP]
DEBUGF DBG_INFO, "nvme%u: Maximum queue entries available is %u (required: %u)\n", [esi + pcidev.num], ax, SQ_ENTRIES
cmp ax, SQ_ENTRIES
jb .exit_fail
DEBUGF DBG_INFO, "nvme%u: OK... maximum queue entries is %u\n", [esi + pcidev.num], ax
if __DEBUG__
test eax, CAP_CQR
@ -684,11 +684,13 @@ proc nvme_init stdcall, pci:dword
; Check if NVM command set is supported
mov eax, dword [edi + NVME_MMIO.CAP + 4]
DEBUGF DBG_INFO, "nvme%u: Checking if NVM command set is supported...\n", [esi + pcidev.num]
test eax, CAP_CSS_NVM_CMDSET
jz .exit_fail
DEBUGF DBG_INFO, "nvme%u: OK... NVM command set supported\n", [esi + pcidev.num]
stdcall nvme_disable_ctrl, esi
DEBUGF DBG_INFO, "nvme%u: Checking if memory page size is supported...\n", [esi + pcidev.num]
mov eax, dword [edi + NVME_MMIO.CAP + 4]
mov edx, eax
and edx, CAP_MPSMIN
@ -710,6 +712,7 @@ proc nvme_init stdcall, pci:dword
xor eax, eax
or eax, (4 shl 20) or (6 shl 16)
mov dword [edi + NVME_MMIO.CC], eax
DEBUGF DBG_INFO, "nvme%u: OK... controller is configured to appropriate settings\n", [esi + pcidev.num]
; Configure Admin Queue Attributes
xor eax, eax
@ -718,6 +721,7 @@ proc nvme_init stdcall, pci:dword
DEBUGF DBG_INFO, "nvme%u: Admin queue attributes: 0x%x\n", [esi + pcidev.num], eax
; Allocate list of queues
DEBUGF DBG_INFO, "nvme%u: Allocating Administrator and I/O queues...\n",, [esi + pcidev.num]
invoke KernelAlloc, sizeof.NVM_QUEUE_ENTRY * (LAST_QUEUE_ID + 1)
test eax, eax
jz .exit_fail
@ -1000,6 +1004,7 @@ proc get_new_cid stdcall, pci:dword, y:dword
mov ecx, [y]
shl ecx, SIZEOF_NVM_QUEUE_ENTRY
movzx eax, word [eax + ecx + NVM_QUEUE_ENTRY.head]
DEBUGF DBG_INFO, "get_new_cid: %u\n", eax
ret
endp
@ -1093,7 +1098,7 @@ proc cqyhdbl_write stdcall, pci:dword, y:dword, cqh:dword
mov edi, dword [esi + pcidev.queue_entries]
lea edi, dword [edi + ecx]
mov eax, [cqh]
;DEBUGF DBG_INFO, "nvme%u: Writing to CQ%u doorbell register 0x%x: %u\n", [esi + pcidev.num], [y], dx, ax
DEBUGF DBG_INFO, "nvme%u: Writing to CQ%u doorbell register 0x%x: %u\n", [esi + pcidev.num], [y], dx, ax
mov esi, dword [esi + pcidev.io_addr]
mov word [esi + edx], ax ; Write to CQyHDBL
mov word [edi + NVM_QUEUE_ENTRY.head], ax
@ -1150,7 +1155,7 @@ proc sqytdbl_write stdcall, pci:dword, y:word, cmd:dword
shl edx, cl
imul edx, ebx
add edx, 0x1000
;DEBUGF DBG_INFO, "nvme%u: Writing to SQ%u doorbell register 0x%x: %u\n", [esi + pcidev.num], [y], dx, ax
DEBUGF DBG_INFO, "nvme%u: Writing to SQ%u doorbell register 0x%x: %u\n", [esi + pcidev.num], [y], dx, ax
mov word [edi + NVM_QUEUE_ENTRY.tail], ax
mov esi, dword [esi + pcidev.io_addr]
mov word [esi + edx], ax