418 lines
19 KiB
C
418 lines
19 KiB
C
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/*====================================================================/*
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opcodes_ed.c -> This file executes the ED opcodes.
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Another prefix that "creates" new instructions. This prefix also
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introduces some undocumented opcodes that we've tried to include
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here. Maybe their implementation it's wrong: if you can find any
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mistake about how we have implemented/interpreted them, please
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let us know.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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Copyright (c) 2000 Santiago Romero Iglesias.
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Email: sromero@escomposlinux.org
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=====================================================================*/
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/* 8 clock cycles minimum = ED opcode = 4 + 4 */
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opcode = Z80ReadMem( r_PC );
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r_PC++;
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switch(opcode)
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{
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case LD_BC_xNNe : LOAD_rr_nn(r_BC); AddCycles( 4+4+12 ); break;
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case LD_DE_xNNe : LOAD_rr_nn(r_DE); AddCycles( 4+4+12 ); break;
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case LD_HL_xNNe : LOAD_rr_nn(r_HL); AddCycles( 4+4+12 ); break;
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case LD_SP_xNNe : LOAD_rr_nn(r_SP); AddCycles( 4+4+12 ); break;
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case LD_xNNe_BC : STORE_nn_rr(r_BC); AddCycles( 4+4+12 ); break;
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case LD_xNNe_DE : STORE_nn_rr(r_DE); AddCycles( 4+4+12 ); break;
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case LD_xNNe_HL : STORE_nn_rr(r_HL); AddCycles( 4+4+12 ); break;
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case LD_xNNe_SP : STORE_nn_rr(r_SP); AddCycles( 4+4+12 ); break;
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case NEG :
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case ED_5C :
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case ED_74 :
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case ED_7C :
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case ED_6C :
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case ED_54 :
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case ED_4C :
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case ED_64 : NEG_A(); AddCycles( 4+4 ); break;
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case RETI :
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case RETN :
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case ED_65 :
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case ED_6D :
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case ED_75 :
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case ED_7D :
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case ED_5D :
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case ED_55 :
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r_IFF1 = r_IFF2;
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RET_nn();
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AddCycles( 4+4+6 ); break;
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case IM_0 :
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case ED_4E : /* * IM 0/1 */
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case ED_6E :
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case ED_66 : regs->IM = 0;
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AddCycles( 4+4 ); break; /* * IM 0 */
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case IM_1 :
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case ED_76 : regs->IM = 1;
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AddCycles( 4+4 ); break;
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case IM_2 :
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case ED_7E : regs->IM = 2;
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AddCycles( 4+4 ); break;
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case ED_77 :
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case ED_7F : AddCycles( 4+4 ); break; /* * NOP */
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case OUT_xC_B : Z80OutPort(regs,r_BC, r_B); AddCycles( 4+4+4 ); break;
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case OUT_xC_C : Z80OutPort(regs,r_BC, r_C); AddCycles( 4+4+4 ); break;
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case OUT_xC_D : Z80OutPort(regs,r_BC, r_D); AddCycles( 4+4+4 ); break;
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case OUT_xC_E : Z80OutPort(regs,r_BC, r_E); AddCycles( 4+4+4 ); break;
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case OUT_xC_H : Z80OutPort(regs,r_BC, r_H); AddCycles( 4+4+4 ); break;
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case OUT_xC_L : Z80OutPort(regs,r_BC, r_L); AddCycles( 4+4+4 ); break;
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case OUT_xC_A : Z80OutPort(regs,r_BC, r_A); AddCycles( 4+4+4 ); break;
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/* * OUT (C), 0 */
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case ED_71 : Z80OutPort(regs,r_BC, 0); AddCycles( 4+4+4 ); break;
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case IN_B_xC : IN(r_B, r_BC); AddCycles( 4+4+4 ); break;
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case IN_C_xC : IN(r_C, r_BC); AddCycles( 4+4+4 ); break;
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case IN_D_xC : IN(r_D, r_BC); AddCycles( 4+4+4 ); break;
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case IN_E_xC : IN(r_E, r_BC); AddCycles( 4+4+4 ); break;
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case IN_L_xC : IN(r_L, r_BC); AddCycles( 4+4+4 ); break;
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case IN_H_xC : IN(r_H, r_BC); AddCycles( 4+4+4 ); break;
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case IN_A_xC : IN(r_A, r_BC); AddCycles( 4+4+4 ); break;
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case IN_F_xC : IN(r_meml, r_BC); AddCycles( 4+4+4 ); break;
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case LD_A_I : r_A = regs->I;
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r_F = ( r_F & FLAG_C )|sz53_table[r_A]|
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( regs->IFF2 ? FLAG_V:0 );
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AddCycles( 4+4+1 ); break;
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case LD_I_A : regs->I = r_A; AddCycles( 4+4+1 ); break;
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case LD_A_R : r_A = ( regs->R.W & 0x7f ) | (regs->R.W & 0x80);
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r_F = (r_F&FLAG_C)|sz53_table[r_A] | (regs->IFF2?FLAG_V:0);
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AddCycles( 4+4+1 ); break;
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case LD_R_A : regs->R.W = r_A;
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AddCycles( 4+4+1 ); break;
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case ADC_HL_BC : ADC_WORD(r_BC); AddCycles( 4+4+4+1+2 ); break;
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case ADC_HL_DE : ADC_WORD(r_DE); AddCycles( 4+4+4+1+2 ); break;
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case ADC_HL_HL : ADC_WORD(r_HL); AddCycles( 4+4+4+1+2 ); break;
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case ADC_HL_SP : ADC_WORD(r_SP); AddCycles( 4+4+4+1+2 ); break;
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case SBC_HL_BC : SBC_WORD(r_BC); AddCycles( 4+4+4+1+2 ); break;
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case SBC_HL_DE : SBC_WORD(r_DE); AddCycles( 4+4+4+1+2 ); break;
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case SBC_HL_HL : SBC_WORD(r_HL); AddCycles( 4+4+4+1+2 ); break;
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case SBC_HL_SP : SBC_WORD(r_SP); AddCycles( 4+4+4+1+2 ); break;
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case RRD : r_meml = Z80ReadMem(r_HL);
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Z80WriteMem(r_HL, ( r_A << 4 ) | ( r_meml >> 4 ), regs );
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r_A = ( r_A & 0xf0 ) | ( r_meml & 0x0f );
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r_F = ( r_F & FLAG_C ) | sz53p_table[r_A];
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AddCycles( 4+4+10 ); break;
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case RLD : r_meml = Z80ReadMem(r_HL);
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Z80WriteMem(r_HL, (r_meml << 4 ) | ( r_A & 0x0f ), regs );
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r_A = ( r_A & 0xf0 ) | ( r_meml >> 4 );
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r_F = ( r_F & FLAG_C ) | sz53p_table[r_A];
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AddCycles( 4+4+10 ); break;
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case LDI : r_meml = Z80ReadMem(r_HL); r_HL++;
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Z80WriteMem( r_DE, r_meml, regs ); r_DE++;
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r_BC--; r_meml += r_A;
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r_F = ( r_F & ( FLAG_C|FLAG_Z|FLAG_S ) ) |
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( r_BC ? FLAG_V:0 ) | ( r_meml & FLAG_3 ) |
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((r_meml & 0x02) ? FLAG_5 : 0 );
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AddCycles( 4+4+4+4 ); break;
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case LDIR : r_meml = Z80ReadMem(r_HL); r_HL++;
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Z80WriteMem( r_DE, r_meml, regs ); r_DE++;
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r_BC--; r_meml += r_A;
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r_F = ( r_F & ( FLAG_C|FLAG_Z|FLAG_S ) ) |
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( r_BC ? FLAG_V:0 ) | ( r_meml & FLAG_3 ) |
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((r_meml & 0x02) ? FLAG_5 : 0 );
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AddCycles( 4+4+4+4 );
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if( r_BC ) { r_PC-=2; AddCycles(5); }
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break;
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case LDD : r_meml = Z80ReadMem(r_HL); r_HL--;
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Z80WriteMem( r_DE, r_meml, regs ); r_DE--;
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r_BC--; r_meml += r_A;
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r_F = ( r_F & ( FLAG_C | FLAG_Z | FLAG_S ) ) |
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(r_BC ? FLAG_V : 0 ) | ( r_meml & FLAG_3 ) |
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((r_meml & 0x02) ? FLAG_5 : 0 );
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AddCycles( 4+4+4+4 ); break;
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case LDDR : r_meml = Z80ReadMem(r_HL);
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Z80WriteMem( r_DE, r_meml, regs );
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r_HL--; r_DE--; r_BC--; r_meml += r_A;
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r_F = ( r_F & ( FLAG_C | FLAG_Z | FLAG_S ) ) |
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(r_BC ? FLAG_V : 0 ) | ( r_meml & FLAG_3 ) |
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((r_meml & 0x02) ? FLAG_5 : 0 );
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AddCycles( 4+4+4+4+1 );
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if( r_BC ) { r_PC-=2; AddCycles(4); }
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break;
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// I had lots of problems with CPI, INI, CPD, IND, OUTI, OUTD and so...
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// Thanks a lot to Philip Kendall for letting me to take a look to his
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// fuse emulator and allowing me to use their flag routines :-)
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case CPI : r_meml = Z80ReadMem(r_HL);
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r_memh = r_A - r_meml;
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r_opl = ( (r_A & 0x08) >> 3 ) |
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( ( (r_meml) & 0x08 ) >> 2 ) |
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( (r_meml & 0x08) >> 1 );
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r_HL++; r_BC--;
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r_F = ( r_F & FLAG_C ) |
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( r_BC ? ( FLAG_V | FLAG_N ) : FLAG_N ) |
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halfcarry_sub_table[r_opl] |
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( r_memh ? 0 : FLAG_Z ) |
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( r_memh & FLAG_S );
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if( r_F & FLAG_H) r_memh--;
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r_F |= ( r_memh & FLAG_3 ) |
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( (r_memh&0x02) ? FLAG_5 : 0 );
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AddCycles( 4+4+4+4); break;
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case CPIR : r_meml = Z80ReadMem(r_HL);
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r_memh = r_A - r_meml;
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r_opl = ( (r_A & 0x08) >> 3 ) |
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( ( (r_meml) & 0x08 ) >> 2 ) |
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( (r_meml & 0x08) >> 1 );
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r_HL++; r_BC--;
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r_F = ( r_F & FLAG_C ) |
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( r_BC ? ( FLAG_V | FLAG_N ) : FLAG_N ) |
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halfcarry_sub_table[r_opl] |
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( r_memh ? 0 : FLAG_Z ) |
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( r_memh & FLAG_S );
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if( r_F & FLAG_H) r_memh--;
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r_F |= ( r_memh & FLAG_3 ) |
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( (r_memh&0x02) ? FLAG_5 : 0 );
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if( ( r_F & ( FLAG_V | FLAG_Z ) ) == FLAG_V )
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{ AddCycles(5); r_PC-=2; }
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AddCycles( 4+4+4+4); break;
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case CPD : r_meml = Z80ReadMem(r_HL);
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r_memh = r_A-r_meml;
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r_opl = ( (r_A & 0x08) >> 3 ) |
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( ( (r_meml) & 0x08 ) >> 2 ) |
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( (r_memh & 0x08) >> 1 );
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r_HL--; r_BC--;
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r_F = ( r_F & FLAG_C ) |
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( r_BC ? ( FLAG_V | FLAG_N ) : FLAG_N ) |
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halfcarry_sub_table[r_opl] |
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( r_memh ? 0 : FLAG_Z ) |
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( r_memh & FLAG_S );
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if(r_F & FLAG_H) r_memh--;
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r_F |= ( r_memh & FLAG_3 ) |
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( (r_memh&0x02) ? FLAG_5 : 0 );
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AddCycles( 4+4+4+4); break;
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case CPDR : r_meml = Z80ReadMem(r_HL);
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r_memh = r_A-r_meml;
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r_opl = ( (r_A & 0x08) >> 3 ) |
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( ( (r_meml) & 0x08 ) >> 2 ) |
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( (r_memh & 0x08) >> 1 );
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r_HL--; r_BC--;
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r_F = ( r_F & FLAG_C ) |
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( r_BC ? ( FLAG_V | FLAG_N ) : FLAG_N ) |
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halfcarry_sub_table[r_opl] |
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( r_memh ? 0 : FLAG_Z ) |
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( r_memh & FLAG_S );
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if(r_F & FLAG_H) r_memh--;
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r_F |= ( r_memh & FLAG_3 ) |
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( (r_memh&0x02) ? FLAG_5 : 0 );
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if( ( r_F & ( FLAG_V | FLAG_Z ) ) == FLAG_V )
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{ AddCycles(5); r_PC-=2; }
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AddCycles( 4+4+4+4 ); break;
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/*
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// OUTI contributed by Alvaro Alea
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case OUTI : Z80OutPort( regs, r_BC, Z80ReadMem( r_HL )) ;
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r_HL++ ; r_B-- ;
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if (r_B==0)
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r_F |= FLAG_Z;
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else
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r_F &= !FLAG_Z;
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r_F |= FLAG_N;
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AddCycles( 4+4+4+4 ); break;
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*/
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// I/O block instructions by Metalbrain - 14-5-2001
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case IND : r_meml = Z80InPort((r_BC)); r_memh=0;
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r_F = ( r_F & FLAG_C ) | ( (r_B)&0x0f ? 0 : FLAG_H ) | FLAG_N; \
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(r_B)--;
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r_F |= ( (r_B)==0x7f ? FLAG_V : 0 ) | sz53_table[(r_B)];
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r_F &= 0xE8;
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Z80WriteMem( r_HL, r_meml, regs );
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r_F |= ( (r_meml & 0x80 ) >> 6);
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r_opl = r_C; r_oph = 0;
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r_opl--;
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r_op += r_mem;
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r_oph += (r_oph << 4);
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r_F |= r_oph;
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r_opl = (r_meml & 7) + ( (r_C & 7) << 3 );
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r_F |= ( ioblock_2_table[(r_B)] ^ ioblock_dec1_table[(r_opl)] );
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r_HL--;
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AddCycles( 4+4+4+4); break;
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case INDR : r_meml = Z80InPort((r_BC)); r_memh=0;
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r_F = ( r_F & FLAG_C ) | ( (r_B)&0x0f ? 0 : FLAG_H ) | FLAG_N; \
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(r_B)--;
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r_F |= ( (r_B)==0x7f ? FLAG_V : 0 ) | sz53_table[(r_B)];
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r_F &= 0xE8;
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Z80WriteMem( r_HL, r_meml, regs );
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r_F |= ( (r_meml & 0x80 ) >> 6);
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r_opl = r_C; r_oph = 0;
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r_opl--;
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r_op += r_mem;
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r_oph += (r_oph << 4);
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r_F |= r_oph;
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r_opl = (r_meml & 7) + ( (r_C & 7) << 3 );
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r_F |= ( ioblock_2_table[(r_B)] ^ ioblock_dec1_table[(r_opl)] );
|
||
|
|
r_HL--;
|
||
|
|
if( r_B ) { r_PC-=2; AddCycles(5); }
|
||
|
|
AddCycles( 4+4+4+4); break;
|
||
|
|
|
||
|
|
case INI : r_meml = Z80InPort((r_BC)); r_memh=0;
|
||
|
|
r_F = ( r_F & FLAG_C ) | ( (r_B)&0x0f ? 0 : FLAG_H ) | FLAG_N; \
|
||
|
|
(r_B)--;
|
||
|
|
r_F |= ( (r_B)==0x7f ? FLAG_V : 0 ) | sz53_table[(r_B)];
|
||
|
|
r_F &= 0xE8;
|
||
|
|
Z80WriteMem( r_HL, r_meml, regs );
|
||
|
|
r_F |= ( (r_meml & 0x80 ) >> 6);
|
||
|
|
r_opl = r_C; r_oph = 0;
|
||
|
|
r_opl++;
|
||
|
|
r_op += r_mem;
|
||
|
|
r_oph += (r_oph << 4);
|
||
|
|
r_F |= r_oph;
|
||
|
|
r_opl = (r_meml & 7) + ( (r_C & 7) << 3 );
|
||
|
|
r_F |= ( ioblock_2_table[(r_B)] ^ ioblock_inc1_table[(r_opl)] );
|
||
|
|
r_HL++;
|
||
|
|
AddCycles( 4+4+4+4); break;
|
||
|
|
|
||
|
|
|
||
|
|
case INIR : r_meml = Z80InPort((r_BC)); r_memh=0;
|
||
|
|
r_F = ( r_F & FLAG_C ) | ( (r_B)&0x0f ? 0 : FLAG_H ) | FLAG_N; \
|
||
|
|
(r_B)--;
|
||
|
|
r_F |= ( (r_B)==0x7f ? FLAG_V : 0 ) | sz53_table[(r_B)];
|
||
|
|
r_F &= 0xE8;
|
||
|
|
Z80WriteMem( r_HL, r_meml, regs );
|
||
|
|
r_F |= ( (r_meml & 0x80 ) >> 6);
|
||
|
|
r_opl = r_C; r_oph = 0;
|
||
|
|
r_opl++;
|
||
|
|
r_op += r_mem;
|
||
|
|
r_oph += (r_oph << 4);
|
||
|
|
r_F |= r_oph;
|
||
|
|
r_opl = (r_meml & 7) + ( (r_C & 7) << 3 );
|
||
|
|
r_F |= ( ioblock_2_table[(r_B)] ^ ioblock_inc1_table[(r_opl)] );
|
||
|
|
r_HL++;
|
||
|
|
if( r_B ) { r_PC-=2; AddCycles(5); }
|
||
|
|
AddCycles( 4+4+4+4); break;
|
||
|
|
|
||
|
|
case OUTI : r_meml = Z80ReadMem(r_HL); r_memh = 0;
|
||
|
|
r_F = ( r_F & FLAG_C ) | ( (r_B)&0x0f ? 0 : FLAG_H ) | FLAG_N; \
|
||
|
|
(r_B)--;
|
||
|
|
r_F |= ( (r_B)==0x7f ? FLAG_V : 0 ) | sz53_table[(r_B)];
|
||
|
|
r_F &= 0xE8;
|
||
|
|
Z80OutPort( regs, r_BC, r_meml);
|
||
|
|
r_F |= ((r_meml & 0x80 ) >> 6);
|
||
|
|
r_opl = r_C; r_oph=0;
|
||
|
|
r_opl++;
|
||
|
|
r_op += r_mem;
|
||
|
|
r_oph += (r_oph<<4);
|
||
|
|
r_F |= r_oph;
|
||
|
|
r_opl = (r_meml & 7) + ( (r_C & 7) << 3 );
|
||
|
|
r_F |= ( ioblock_2_table[(r_B)] ^ ioblock_inc1_table[(r_opl)] );
|
||
|
|
r_HL++;
|
||
|
|
AddCycles( 4+4+4+4); break;
|
||
|
|
|
||
|
|
case OTIR : r_meml = Z80ReadMem(r_HL); r_memh = 0;
|
||
|
|
r_F = ( r_F & FLAG_C ) | ( (r_B)&0x0f ? 0 : FLAG_H ) | FLAG_N; \
|
||
|
|
(r_B)--;
|
||
|
|
r_F |= ( (r_B)==0x7f ? FLAG_V : 0 ) | sz53_table[(r_B)];
|
||
|
|
r_F &= 0xE8;
|
||
|
|
Z80OutPort( regs, r_BC, r_meml);
|
||
|
|
r_F |= ((r_meml & 0x80 ) >> 6);
|
||
|
|
r_opl = r_C; r_oph=0;
|
||
|
|
r_opl++;
|
||
|
|
r_op += r_mem;
|
||
|
|
r_oph += (r_oph<<4);
|
||
|
|
r_F |= r_oph;
|
||
|
|
r_opl = (r_meml & 7) + ( (r_C & 7) << 3 );
|
||
|
|
r_F |= ( ioblock_2_table[(r_B)] ^ ioblock_inc1_table[(r_opl)] );
|
||
|
|
r_HL++;
|
||
|
|
if( r_B ) { r_PC-=2; AddCycles(5); }
|
||
|
|
AddCycles( 4+4+4+4); break;
|
||
|
|
|
||
|
|
|
||
|
|
case OUTD : r_meml = Z80ReadMem(r_HL); r_memh = 0;
|
||
|
|
r_F = ( r_F & FLAG_C ) | ( (r_B)&0x0f ? 0 : FLAG_H ) | FLAG_N; \
|
||
|
|
(r_B)--;
|
||
|
|
r_F |= ( (r_B)==0x7f ? FLAG_V : 0 ) | sz53_table[(r_B)];
|
||
|
|
r_F &= 0xE8;
|
||
|
|
Z80OutPort( regs, r_BC, r_meml);
|
||
|
|
r_F |= ((r_meml & 0x80 ) >> 6);
|
||
|
|
r_opl = r_C; r_oph=0;
|
||
|
|
r_opl--;
|
||
|
|
r_op += r_mem;
|
||
|
|
r_oph += (r_oph<<4);
|
||
|
|
r_F |= r_oph;
|
||
|
|
r_opl = (r_meml & 7) + ( (r_C & 7) << 3 );
|
||
|
|
r_F |= ( ioblock_2_table[(r_B)] ^ ioblock_dec1_table[(r_opl)] );
|
||
|
|
r_HL--;
|
||
|
|
AddCycles( 4+4+4+4); break;
|
||
|
|
|
||
|
|
case OTDR : r_meml = Z80ReadMem(r_HL); r_memh = 0;
|
||
|
|
r_F = ( r_F & FLAG_C ) | ( (r_B)&0x0f ? 0 : FLAG_H ) | FLAG_N; \
|
||
|
|
(r_B)--;
|
||
|
|
r_F |= ( (r_B)==0x7f ? FLAG_V : 0 ) | sz53_table[(r_B)];
|
||
|
|
r_F &= 0xE8;
|
||
|
|
Z80OutPort( regs, r_BC, r_meml);
|
||
|
|
r_F |= ((r_meml & 0x80 ) >> 6);
|
||
|
|
r_opl = r_C; r_oph=0;
|
||
|
|
r_opl--;
|
||
|
|
r_op += r_mem;
|
||
|
|
r_oph += (r_oph<<4);
|
||
|
|
r_F |= r_oph;
|
||
|
|
r_opl = (r_meml & 7) + ( (r_C & 7) << 3 );
|
||
|
|
r_F |= ( ioblock_2_table[(r_B)] ^ ioblock_dec1_table[(r_opl)] );
|
||
|
|
r_HL--;
|
||
|
|
if( r_B ) { r_PC-=2; AddCycles(5); }
|
||
|
|
AddCycles( 4+4+4+4); break;
|
||
|
|
|
||
|
|
// End of Metalbrain's contribution
|
||
|
|
|
||
|
|
case PREFIX_ED: AddCycles( 4 ); /* ED ED xx = 12 cycles min = 4+8 */
|
||
|
|
r_PC-- ;
|
||
|
|
break;
|
||
|
|
|
||
|
|
default:
|
||
|
|
// exit(1);
|
||
|
|
AddCycles( 4+4 ); /* Just a NOP */
|
||
|
|
///!!! if(regs->DecodingErrors)
|
||
|
|
///!!! printf( "z80 core: Unknown instruction: ED %02Xh at PC=%04Xh.\n",
|
||
|
|
///!!! Z80ReadMem(r_PC-1),r_PC-2 );
|
||
|
|
break;
|
||
|
|
}
|