351 lines
14 KiB
C
351 lines
14 KiB
C
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/*
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* RadeonHD R6xx, R7xx DRI driver
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*
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* Copyright (C) 2008-2009 Alexander Deucher
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* Copyright (C) 2008-2009 Matthias Hopf
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* BRIAN PAUL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
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* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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/*
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* Shader macros
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*/
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#ifndef __SHADER_H__
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#define __SHADER_H__
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//#include "radeon.h"
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/* Restrictions of ALU instructions
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* order of scalar ops is always x,y,z,w,t(rans), last to be indicated by last==1.
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* max of 3 different src GPRs per instr.
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* max of 4 different cfile constant components per instr.
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* max of 2 (different) constants (any type) for t.
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* bank swizzle (see below).
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* GPR write stalls read of same register. Auto-replaced by PV/PS, NOP needed if registers are relative to
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* different indices (gpr,loop,nothing).
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* may use constant registers or constant cache, but not both.
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*/
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/* Bank_swizzle: (pp. 297ff)
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* Only one of each x,y,z,w GPR component can be loaded per cycle (3 cycles per instr, called 0-2).
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* per scalar instruction bank_swizzle can select which cycle each operand comes from. e.g.:
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* SRC0 SRC1 SRC2 SWIZZLE cycle0 cycle1 cycle2
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* 1.x 2.x 012 1.x 2.x -
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* 3.x 1.y 201 1.y - 3.x
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* 2.x 1.y 102 (1.y) (2.x) -
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* If data is read in a cycle, multiple scalar instructions can reference it.
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* Special case: square() - i.e. same component in src0+src1 doesn't need read port -> ignores swizzle for src1.
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* No restrictions for constants or PV/PS.
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* t can load multiple components in a single cycle slot, but has to share cycles with xyzw.
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* t with single constant may not load GPRs or PV/PS in cycle 0 (carefull with ALU_TRANS_210).
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* t with two constants may only load GPRs or PV/PS in cycle 2.
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*/
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/* Oder of instructions: All CF, All ALU, All Tex/Vtx fetches */
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// CF insts
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// addr
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#define ADDR(x) (x)
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// pc
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#define POP_COUNT(x) (x)
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// const
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#define CF_CONST(x) (x)
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// cond
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#define COND(x) (x) // SQ_COND_*
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// count
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#define I_COUNT(x) ((x) ? ((x) - 1) : 0)
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//r7xx
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#define COUNT_3(x) (x)
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// call count
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#define CALL_COUNT(x) (x)
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// eop
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#define END_OF_PROGRAM(x) (x)
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// vpm
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#define VALID_PIXEL_MODE(x) (x)
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// cf inst
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#define CF_INST(x) (x) // SQ_CF_INST_*
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// wqm
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#define WHOLE_QUAD_MODE(x) (x)
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// barrier
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#define BARRIER(x) (x)
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//kb0
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#define KCACHE_BANK0(x) (x)
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//kb1
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#define KCACHE_BANK1(x) (x)
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// km0/1
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#define KCACHE_MODE0(x) (x)
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#define KCACHE_MODE1(x) (x) // SQ_CF_KCACHE_*
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//
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#define KCACHE_ADDR0(x) (x)
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#define KCACHE_ADDR1(x) (x)
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// uw
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#define USES_WATERFALL(x) (x)
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#define ARRAY_BASE(x) (x)
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// export pixel
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#define CF_PIXEL_MRT0 0
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#define CF_PIXEL_MRT1 1
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#define CF_PIXEL_MRT2 2
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#define CF_PIXEL_MRT3 3
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#define CF_PIXEL_MRT4 4
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#define CF_PIXEL_MRT5 5
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#define CF_PIXEL_MRT6 6
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#define CF_PIXEL_MRT7 7
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// *_FOG: r6xx only
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#define CF_PIXEL_MRT0_FOG 16
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#define CF_PIXEL_MRT1_FOG 17
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#define CF_PIXEL_MRT2_FOG 18
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#define CF_PIXEL_MRT3_FOG 19
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#define CF_PIXEL_MRT4_FOG 20
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#define CF_PIXEL_MRT5_FOG 21
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#define CF_PIXEL_MRT6_FOG 22
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#define CF_PIXEL_MRT7_FOG 23
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#define CF_PIXEL_Z 61
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// export pos
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#define CF_POS0 60
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#define CF_POS1 61
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#define CF_POS2 62
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#define CF_POS3 63
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// export param
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// 0...31
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#define TYPE(x) (x) // SQ_EXPORT_*
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#if 0
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// type export
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#define SQ_EXPORT_PIXEL 0
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#define SQ_EXPORT_POS 1
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#define SQ_EXPORT_PARAM 2
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// reserved 3
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// type mem
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#define SQ_EXPORT_WRITE 0
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#define SQ_EXPORT_WRITE_IND 1
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#define SQ_EXPORT_WRITE_ACK 2
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#define SQ_EXPORT_WRITE_IND_ACK 3
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#endif
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#define RW_GPR(x) (x)
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#define RW_REL(x) (x)
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#define ABSOLUTE 0
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#define RELATIVE 1
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#define INDEX_GPR(x) (x)
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#define ELEM_SIZE(x) (x ? (x - 1) : 0)
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#define COMP_MASK(x) (x)
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#define R6xx_ELEM_LOOP(x) (x)
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#define BURST_COUNT(x) (x ? (x - 1) : 0)
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// swiz
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#define SRC_SEL_X(x) (x) // SQ_SEL_* each
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#define SRC_SEL_Y(x) (x)
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#define SRC_SEL_Z(x) (x)
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#define SRC_SEL_W(x) (x)
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#define CF_DWORD0(addr) cpu_to_le32((addr))
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// R7xx has another entry (COUNT3), but that is only used for adding a bit to count.
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// We allow one more bit for count in the argument of the macro on R7xx instead.
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// R6xx: [0,7] R7xx: [1,16]
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#define CF_DWORD1(pc, cf_const, cond, count, call_count, eop, vpm, cf_inst, wqm, b) \
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cpu_to_le32((((pc) << 0) | ((cf_const) << 3) | ((cond) << 8) | (((count) & 7) << 10) | (((count) >> 3) << 19) | \
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((call_count) << 13) | ((eop) << 21) | ((vpm) << 22) | ((cf_inst) << 23) | ((wqm) << 30) | ((b) << 31)))
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#define CF_ALU_DWORD0(addr, kb0, kb1, km0) cpu_to_le32((((addr) << 0) | ((kb0) << 22) | ((kb1) << 26) | ((km0) << 30)))
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#define CF_ALU_DWORD1(km1, kcache_addr0, kcache_addr1, count, uw, cf_inst, wqm, b) \
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cpu_to_le32((((km1) << 0) | ((kcache_addr0) << 2) | ((kcache_addr1) << 10) | \
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((count) << 18) | ((uw) << 25) | ((cf_inst) << 26) | ((wqm) << 30) | ((b) << 31)))
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#define CF_ALLOC_IMP_EXP_DWORD0(array_base, type, rw_gpr, rr, index_gpr, es) \
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cpu_to_le32((((array_base) << 0) | ((type) << 13) | ((rw_gpr) << 15) | ((rr) << 22) | ((index_gpr) << 23) | \
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((es) << 30)))
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// R7xx apparently doesn't have the ELEM_LOOP entry any more
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// We still expose it, but ELEM_LOOP is explicitely R6xx now.
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// TODO: is this just forgotten in the docs, or really not available any more?
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#define CF_ALLOC_IMP_EXP_DWORD1_BUF(array_size, comp_mask, el, bc, eop, vpm, cf_inst, wqm, b) \
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cpu_to_le32((((array_size) << 0) | ((comp_mask) << 12) | ((el) << 16) | ((bc) << 17) | \
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((eop) << 21) | ((vpm) << 22) | ((cf_inst) << 23) | ((wqm) << 30) | ((b) << 31)))
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#define CF_ALLOC_IMP_EXP_DWORD1_SWIZ(sel_x, sel_y, sel_z, sel_w, el, bc, eop, vpm, cf_inst, wqm, b) \
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cpu_to_le32((((sel_x) << 0) | ((sel_y) << 3) | ((sel_z) << 6) | ((sel_w) << 9) | ((el) << 16) | \
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((bc) << 17) | ((eop) << 21) | ((vpm) << 22) | ((cf_inst) << 23) | \
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((wqm) << 30) | ((b) << 31)))
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// ALU clause insts
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#define SRC0_SEL(x) (x)
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#define SRC1_SEL(x) (x)
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#define SRC2_SEL(x) (x)
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// src[0-2]_sel
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// 0-127 GPR
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// 128-159 kcache constants bank 0
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// 160-191 kcache constants bank 1
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// 248-255 special SQ_ALU_SRC_* (0, 1, etc.)
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#define ALU_SRC_GPR_BASE 0
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#define ALU_SRC_KCACHE0_BASE 128
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#define ALU_SRC_KCACHE1_BASE 160
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#define ALU_SRC_CFILE_BASE 256
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#define SRC0_REL(x) (x)
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#define SRC1_REL(x) (x)
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#define SRC2_REL(x) (x)
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// elem
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#define SRC0_ELEM(x) (x)
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#define SRC1_ELEM(x) (x)
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#define SRC2_ELEM(x) (x)
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#define ELEM_X 0
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#define ELEM_Y 1
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#define ELEM_Z 2
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#define ELEM_W 3
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// neg
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#define SRC0_NEG(x) (x)
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#define SRC1_NEG(x) (x)
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#define SRC2_NEG(x) (x)
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// im
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#define INDEX_MODE(x) (x) // SQ_INDEX_*
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// ps
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#define PRED_SEL(x) (x) // SQ_PRED_SEL_*
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// last
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#define LAST(x) (x)
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// abs
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#define SRC0_ABS(x) (x)
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#define SRC1_ABS(x) (x)
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// uem
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#define UPDATE_EXECUTE_MASK(x) (x)
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// up
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#define UPDATE_PRED(x) (x)
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// wm
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#define WRITE_MASK(x) (x)
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// fm
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#define FOG_MERGE(x) (x)
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// omod
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#define OMOD(x) (x) // SQ_ALU_OMOD_*
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// alu inst
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#define ALU_INST(x) (x) // SQ_ALU_INST_*
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//bs
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#define BANK_SWIZZLE(x) (x) // SQ_ALU_VEC_*
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#define DST_GPR(x) (x)
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#define DST_REL(x) (x)
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#define DST_ELEM(x) (x)
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#define CLAMP(x) (x)
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#define ALU_DWORD0(src0_sel, s0r, s0e, s0n, src1_sel, s1r, s1e, s1n, im, ps, last) \
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cpu_to_le32((((src0_sel) << 0) | ((s0r) << 9) | ((s0e) << 10) | ((s0n) << 12) | \
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((src1_sel) << 13) | ((s1r) << 22) | ((s1e) << 23) | ((s1n) << 25) | \
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((im) << 26) | ((ps) << 29) | ((last) << 31)))
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// R7xx has alu_inst at a different slot, and no fog merge any more (no fix function fog any more)
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#define R6xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, fm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) \
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cpu_to_le32((((s0a) << 0) | ((s1a) << 1) | ((uem) << 2) | ((up) << 3) | ((wm) << 4) | \
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((fm) << 5) | ((omod) << 6) | ((alu_inst) << 8) | ((bs) << 18) | ((dst_gpr) << 21) | \
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((dr) << 28) | ((de) << 29) | ((clamp) << 31)))
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#define R7xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) \
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cpu_to_le32((((s0a) << 0) | ((s1a) << 1) | ((uem) << 2) | ((up) << 3) | ((wm) << 4) | \
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((omod) << 5) | ((alu_inst) << 7) | ((bs) << 18) | ((dst_gpr) << 21) | \
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((dr) << 28) | ((de) << 29) | ((clamp) << 31)))
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// This is a general chipset macro, but due to selection by chipid typically not usable in static arrays
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// Fog is NOT USED on R7xx, even if specified.
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#define ALU_DWORD1_OP2(chipfamily, s0a, s1a, uem, up, wm, fm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) \
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((chipfamily) < CHIP_FAMILY_RV770 ? \
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R6xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, fm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) : \
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R7xx_ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, omod, alu_inst, bs, dst_gpr, dr, de, clamp))
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#define ALU_DWORD1_OP3(src2_sel, s2r, s2e, s2n, alu_inst, bs, dst_gpr, dr, de, clamp) \
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cpu_to_le32((((src2_sel) << 0) | ((s2r) << 9) | ((s2e) << 10) | ((s2n) << 12) | \
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((alu_inst) << 13) | ((bs) << 18) | ((dst_gpr) << 21) | ((dr) << 28) | \
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((de) << 29) | ((clamp) << 31)))
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// VTX clause insts
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// vxt insts
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#define VTX_INST(x) (x) // SQ_VTX_INST_*
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// fetch type
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#define FETCH_TYPE(x) (x) // SQ_VTX_FETCH_*
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#define FETCH_WHOLE_QUAD(x) (x)
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#define BUFFER_ID(x) (x)
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#define SRC_GPR(x) (x)
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#define SRC_REL(x) (x)
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#define MEGA_FETCH_COUNT(x) ((x) ? ((x) - 1) : 0)
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#define SEMANTIC_ID(x) (x)
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#define DST_SEL_X(x) (x)
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#define DST_SEL_Y(x) (x)
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#define DST_SEL_Z(x) (x)
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#define DST_SEL_W(x) (x)
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#define USE_CONST_FIELDS(x) (x)
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#define DATA_FORMAT(x) (x)
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// num format
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#define NUM_FORMAT_ALL(x) (x) // SQ_NUM_FORMAT_*
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// format comp
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#define FORMAT_COMP_ALL(x) (x) // SQ_FORMAT_COMP_*
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// sma
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#define SRF_MODE_ALL(x) (x)
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#define SRF_MODE_ZERO_CLAMP_MINUS_ONE 0
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#define SRF_MODE_NO_ZERO 1
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#define OFFSET(x) (x)
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// endian swap
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#define ENDIAN_SWAP(x) (x) // SQ_ENDIAN_*
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#define CONST_BUF_NO_STRIDE(x) (x)
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// mf
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#define MEGA_FETCH(x) (x)
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#define VTX_DWORD0(vtx_inst, ft, fwq, buffer_id, src_gpr, sr, ssx, mfc) \
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cpu_to_le32((((vtx_inst) << 0) | ((ft) << 5) | ((fwq) << 7) | ((buffer_id) << 8) | \
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((src_gpr) << 16) | ((sr) << 23) | ((ssx) << 24) | ((mfc) << 26)))
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#define VTX_DWORD1_SEM(semantic_id, dsx, dsy, dsz, dsw, ucf, data_format, nfa, fca, sma) \
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cpu_to_le32((((semantic_id) << 0) | ((dsx) << 9) | ((dsy) << 12) | ((dsz) << 15) | ((dsw) << 18) | \
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((ucf) << 21) | ((data_format) << 22) | ((nfa) << 28) | ((fca) << 30) | ((sma) << 31)))
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#define VTX_DWORD1_GPR(dst_gpr, dr, dsx, dsy, dsz, dsw, ucf, data_format, nfa, fca, sma) \
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cpu_to_le32((((dst_gpr) << 0) | ((dr) << 7) | ((dsx) << 9) | ((dsy) << 12) | ((dsz) << 15) | ((dsw) << 18) | \
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||
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((ucf) << 21) | ((data_format) << 22) | ((nfa) << 28) | ((fca) << 30) | ((sma) << 31)))
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||
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#define VTX_DWORD2(offset, es, cbns, mf) \
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cpu_to_le32((((offset) << 0) | ((es) << 16) | ((cbns) << 18) | ((mf) << 19)))
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#define VTX_DWORD_PAD cpu_to_le32(0x00000000)
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// TEX clause insts
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// tex insts
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#define TEX_INST(x) (x) // SQ_TEX_INST_*
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||
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#define BC_FRAC_MODE(x) (x)
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||
|
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#define FETCH_WHOLE_QUAD(x) (x)
|
||
|
|
#define RESOURCE_ID(x) (x)
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||
|
|
#define R7xx_ALT_CONST(x) (x)
|
||
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|
||
|
|
#define LOD_BIAS(x) (x)
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||
|
|
//ct
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||
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|
#define COORD_TYPE_X(x) (x)
|
||
|
|
#define COORD_TYPE_Y(x) (x)
|
||
|
|
#define COORD_TYPE_Z(x) (x)
|
||
|
|
#define COORD_TYPE_W(x) (x)
|
||
|
|
#define TEX_UNNORMALIZED 0
|
||
|
|
#define TEX_NORMALIZED 1
|
||
|
|
#define OFFSET_X(x) (((int)(x) * 2) & 0x1f) /* 4:1-bits 2's-complement fixed-point: [-8.0..7.5] */
|
||
|
|
#define OFFSET_Y(x) (((int)(x) * 2) & 0x1f)
|
||
|
|
#define OFFSET_Z(x) (((int)(x) * 2) & 0x1f)
|
||
|
|
#define SAMPLER_ID(x) (x)
|
||
|
|
|
||
|
|
// R7xx has an additional parameter ALT_CONST. We always expose it, but ALT_CONST is R7xx only
|
||
|
|
#define TEX_DWORD0(tex_inst, bfm, fwq, resource_id, src_gpr, sr, ac) \
|
||
|
|
cpu_to_le32((((tex_inst) << 0) | ((bfm) << 5) | ((fwq) << 7) | ((resource_id) << 8) | \
|
||
|
|
((src_gpr) << 16) | ((sr) << 23) | ((ac) << 24)))
|
||
|
|
#define TEX_DWORD1(dst_gpr, dr, dsx, dsy, dsz, dsw, lod_bias, ctx, cty, ctz, ctw) \
|
||
|
|
cpu_to_le32((((dst_gpr) << 0) | ((dr) << 7) | ((dsx) << 9) | ((dsy) << 12) | ((dsz) << 15) | ((dsw) << 18) | \
|
||
|
|
((lod_bias) << 21) | ((ctx) << 28) | ((cty) << 29) | ((ctz) << 30) | ((ctw) << 31)))
|
||
|
|
#define TEX_DWORD2(offset_x, offset_y, offset_z, sampler_id, ssx, ssy, ssz, ssw) \
|
||
|
|
cpu_to_le32((((offset_x) << 0) | ((offset_y) << 5) | ((offset_z) << 10) | ((sampler_id) << 15) | \
|
||
|
|
((ssx) << 20) | ((ssy) << 23) | ((ssz) << 26) | ((ssw) << 29)))
|
||
|
|
#define TEX_DWORD_PAD cpu_to_le32(0x00000000)
|
||
|
|
|
||
|
|
#endif
|