390 lines
12 KiB
C
390 lines
12 KiB
C
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/*
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* Copyright 2007, 2008 Luc Verhaegen <lverhaegen@novell.com>
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* Copyright 2007, 2008 Matthias Hopf <mhopf@novell.com>
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* Copyright 2007, 2008 Egbert Eich <eich@novell.com>
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* Copyright 2007, 2008 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "xf86.h"
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/* for usleep */
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#if HAVE_XF86_ANSIC_H
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# include "xf86_ansic.h"
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#else
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# include <unistd.h>
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#endif
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#include "rhd.h"
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#include "rhd_crtc.h"
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#include "rhd_connector.h"
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#include "rhd_output.h"
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#include "rhd_regs.h"
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#ifdef ATOM_BIOS
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#include "rhd_atombios.h"
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#endif
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struct DDIAPrivate
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{
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Bool RunDualLink;
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CARD32 PcieCfgReg7;
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CARD32 CapabilityFlag;
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Bool Stored;
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CARD32 DdiaPathControl;
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CARD32 DdiaCntl;
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CARD32 DdiaDcbalancerControl;
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CARD32 DdiaPcieLinkControl2;
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CARD32 DdiaBitDepthControl;
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};
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/*
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*
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*/
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static ModeStatus
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DDIAModeValid(struct rhdOutput *Output, DisplayModePtr Mode)
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{
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RHDFUNC(Output);
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if (Mode->Flags & V_INTERLACE)
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return MODE_NO_INTERLACE;
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if (Mode->Clock < 25000)
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return MODE_CLOCK_LOW;
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if (Output->Connector->Type == RHD_CONNECTOR_DVI_SINGLE) {
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if (Mode->Clock > 165000)
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return MODE_CLOCK_HIGH;
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} else if (Output->Connector->Type == RHD_CONNECTOR_DVI) {
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if (Mode->Clock > 330000) /* could go higher still */
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return MODE_CLOCK_HIGH;
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}
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return MODE_OK;
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}
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/*
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*
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*/
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static void
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DDIAMode(struct rhdOutput *Output, DisplayModePtr Mode)
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{
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struct DDIAPrivate *Private = (struct DDIAPrivate *)Output->Private;
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CARD32 mux0, mux1, mux2, mux3;
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Bool LaneReversal;
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RHDPtr rhdPtr = RHDPTRI(Output);
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RHDFUNC(Output);
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if (Mode->SynthClock >= 165000)
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Private->RunDualLink = TRUE;
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else
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Private->RunDualLink = FALSE;
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/* reset on - will be enabled at POWER_ON */
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RHDRegMask(Output, RS69_DDIA_PATH_CONTROL, RS69_DDIA_PIXVLD_RESET, RS69_DDIA_PIXVLD_RESET);
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/* RGB 4:4:4 */
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RHDRegMask(Output, RS69_DDIA_CNTL, 0, RS69_DDIA_PIXEL_ENCODING);
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/* TMDS_AC */
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RHDRegMask(Output, RS69_DDIA_PATH_CONTROL,
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2 << RS69_DDIA_PATH_SELECT_SHIFT,
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0x3 << RS69_DDIA_PATH_SELECT_SHIFT);
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/* dual link */
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RHDRegMask(Output, RS69_DDIA_CNTL, Private->RunDualLink ?
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RS69_DDIA_DUAL_LINK_ENABLE : 0, RS69_DDIA_DUAL_LINK_ENABLE);
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RHDRegMask(Output, RS69_DDIA_DCBALANCER_CONTROL,
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RS69_DDIA_DCBALANCER_EN,
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RS69_DDIA_SYNC_DCBAL_EN_MASK | RS69_DDIA_DCBALANCER_EN);
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RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL2, 0x0, 0x80);
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RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL2, 0x0, 0x100);
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mux0 = Private->PcieCfgReg7 & 0x3;
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mux1 = (Private->PcieCfgReg7 >> 2) & 0x3;
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mux2 = (Private->PcieCfgReg7 >> 4) & 0x3;
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mux3 = (Private->PcieCfgReg7 >> 6) & 0x3;
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RHDRegMask(Output, RS69_DDIA_PCIE_LINK_CONTROL2,
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(mux0 << RS69_DDIA_PCIE_OUTPUT_MUX_SEL0)
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| (mux1 << RS69_DDIA_PCIE_OUTPUT_MUX_SEL1)
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| (mux2 << RS69_DDIA_PCIE_OUTPUT_MUX_SEL2)
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| (mux3 << RS69_DDIA_PCIE_OUTPUT_MUX_SEL3),
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(3 << RS69_DDIA_PCIE_OUTPUT_MUX_SEL0)
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| (3 << RS69_DDIA_PCIE_OUTPUT_MUX_SEL1)
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| (3 << RS69_DDIA_PCIE_OUTPUT_MUX_SEL2)
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| (3 << RS69_DDIA_PCIE_OUTPUT_MUX_SEL3)
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);
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LaneReversal = Private->PcieCfgReg7 & (0x1 << 10);
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RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL2, 0x0, 0x3);
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RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL2, 0x2, 0x2);
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RHDRegMask(Output, RS69_DDIA_PCIE_LINK_CONTROL3,
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LaneReversal ? RS69_DDIA_PCIE_MIRROR_EN : 0,
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RS69_DDIA_PCIE_MIRROR_EN);
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RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL2, 0x70, 0x70);
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RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0, 0x10);
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RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0, 0x60);
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RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0, 0x4000000);
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switch (rhdPtr->PciDeviceID) {
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case 0x791E:
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if (Mode->SynthClock <= 25000) {
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RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x2780, 0x3f80);
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RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x0, 0xc000);
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RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x039f0000, 0x03000000 | 0x039f0000);
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} else if (Mode->SynthClock <= 60000) {
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RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x2780, 0x3f80);
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RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x0, 0xc000);
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RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x024f0000, 0x03000000 | 0x024f0000);
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} else {
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RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x0980, 0x3f80);
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RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x0, 0xc000);
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RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x01270000, 0x03000000 | 0x01270000);
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}
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break;
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case 0x791F:
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RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x0980, 0x3f80);
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RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x4000, 0xc000);
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RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x00ac0000, 0x03000000 | 0x00ac0000);
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if (Private->CapabilityFlag & 0x10) {
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RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x0, 0xc000);
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if (Mode->SynthClock <= 6500)
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RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x01ac0000, 0x03ff0000);
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else
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RHDRegMaskD(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x01110000, 0x03ff0000);
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}
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break;
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}
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usleep (1);
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RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x04000000, 0x04000000);
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RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x60, 0x60);
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usleep(30);
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RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x01, 0x01);
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usleep(1);
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RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x02, 0x02);
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usleep(1);
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RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x04, 0x04);
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usleep(1);
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RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x08, 0x08);
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usleep(1);
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RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x10, 0x10);
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RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL1, 0x0, 0xf);
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RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL2, 0x0180, 0x0180);
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RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL2, 0x600, 0x600);
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usleep(5);
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RHDRegMask(Output, RS69_DDIA_PCIE_PHY_CONTROL2, 0x0, 0x600);
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/* hw reset will be turned off at POWER_ON */
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/* select crtc source, sync_a, no stereosync */
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RHDRegMask(Output, RS69_DDIA_SOURCE_SELECT, Output->Crtc->Id,
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RS69_DDIA_SOURCE_SELECT_BIT
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| RS69_DDIA_SYNC_SELECT
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| RS69_DDIA_STEREOSYNC_SELECT);
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}
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/*
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*
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*/
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static void
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DDIAPower(struct rhdOutput *Output, int Power)
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{
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RHDDebug(Output->scrnIndex, "%s(%s,%s)\n",__func__,Output->Name,
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rhdPowerString[Power]);
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switch (Power) {
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case RHD_POWER_ON:
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RHDRegMask(Output, RS69_DDIA_PATH_CONTROL, RS69_DDIA_PIXVLD_RESET,
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RS69_DDIA_PIXVLD_RESET);
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RHDRegWrite(Output, RS69_DDIA_BIT_DEPTH_CONTROL, 0);
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RHDRegMask(Output, RS69_DDIA_BIT_DEPTH_CONTROL,
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RS69_DDIA_TEMPORAL_DITHER_RESET, RS69_DDIA_TEMPORAL_DITHER_RESET);
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RHDRegMask(Output, RS69_DDIA_BIT_DEPTH_CONTROL,
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0, RS69_DDIA_TEMPORAL_DITHER_RESET);
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RHDRegMask(Output, RS69_DDIA_CNTL, RS69_DDIA_ENABLE, RS69_DDIA_ENABLE);
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RHDRegMask(Output, RS69_DDIA_PATH_CONTROL, 0, RS69_DDIA_PIXVLD_RESET);
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return;
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case RHD_POWER_RESET:
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RHDRegMask(Output, RS69_DDIA_CNTL, 0, RS69_DDIA_ENABLE);
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return;
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case RHD_POWER_SHUTDOWN:
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RHDRegMask(Output, RS69_DDIA_BIT_DEPTH_CONTROL,
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RS69_DDIA_TEMPORAL_DITHER_RESET, RS69_DDIA_TEMPORAL_DITHER_RESET);
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RHDRegMask(Output, RS69_DDIA_BIT_DEPTH_CONTROL,
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0, RS69_DDIA_TEMPORAL_DITHER_RESET);
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RHDRegMask(Output, RS69_DDIA_BIT_DEPTH_CONTROL,
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0,
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RS69_DDIA_TRUNCATE_EN
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| RS69_DDIA_TRUNCATE_DEPTH
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| RS69_DDIA_SPATIAL_DITHER_EN
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| RS69_DDIA_SPATIAL_DITHER_DEPTH);
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RHDRegMask(Output, RS69_DDIA_BIT_DEPTH_CONTROL,
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0,
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RS69_DDIA_TEMPORAL_DITHER_EN
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| RS69_DDIA_TEMPORAL_DITHER_EN
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| RS69_DDIA_TEMPORAL_DITHER_DEPTH
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| RS69_DDIA_TEMPORAL_LEVEL);
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RHDRegMask(Output, RS69_DDIA_CNTL, 0, RS69_DDIA_ENABLE);
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return;
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default:
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return;
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}
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}
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/*
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*
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*/
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static void
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DDIASave(struct rhdOutput *Output)
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{
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struct DDIAPrivate *Private = (struct DDIAPrivate *)Output->Private;
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RHDFUNC(Output);
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Private->DdiaPathControl = RHDRegRead(Output, RS69_DDIA_PATH_CONTROL);
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Private->DdiaCntl = RHDRegRead(Output, RS69_DDIA_CNTL);
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Private->DdiaDcbalancerControl = RHDRegRead(Output, RS69_DDIA_DCBALANCER_CONTROL);
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Private->DdiaPcieLinkControl2 = RHDRegRead(Output, RS69_DDIA_PCIE_LINK_CONTROL2);
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Private->DdiaBitDepthControl = RHDRegRead(Output, RS69_DDIA_BIT_DEPTH_CONTROL);
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Private->Stored = TRUE;
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}
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/*
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*
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*/
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static void
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DDIARestore(struct rhdOutput *Output)
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{
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struct DDIAPrivate *Private = (struct DDIAPrivate *)Output->Private;
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RHDFUNC(Output);
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if (!Private->Stored)
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return;
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/* disalbe */
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RHDRegMask(Output, RS69_DDIA_CNTL, 0, RS69_DDIA_ENABLE);
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/* reset on */
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RHDRegMask(Output, RS69_DDIA_PATH_CONTROL, RS69_DDIA_PIXVLD_RESET, RS69_DDIA_PIXVLD_RESET);
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RHDRegWrite(Output, RS69_DDIA_PATH_CONTROL, Private->DdiaPathControl | RS69_DDIA_PIXVLD_RESET);
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RHDRegWrite(Output, RS69_DDIA_BIT_DEPTH_CONTROL, Private->DdiaBitDepthControl);
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/* temporal dither reset on */
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RHDRegWrite(Output, RS69_DDIA_BIT_DEPTH_CONTROL, Private->DdiaBitDepthControl
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| RS69_DDIA_TEMPORAL_DITHER_RESET);
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/* temporal dither reset off */
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RHDRegWrite(Output, RS69_DDIA_BIT_DEPTH_CONTROL, Private->DdiaBitDepthControl);
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RHDRegWrite(Output, RS69_DDIA_DCBALANCER_CONTROL, Private->DdiaDcbalancerControl);
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RHDRegWrite(Output, RS69_DDIA_PCIE_LINK_CONTROL2, Private->DdiaPcieLinkControl2);
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/* enable if enabled at startup */
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RHDRegWrite(Output, RS69_DDIA_CNTL, Private->DdiaCntl);
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/* reset off */
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RHDRegWrite(Output, RS69_DDIA_PATH_CONTROL, Private->DdiaPathControl);
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}
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/*
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*
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*/
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|
|
static void
|
||
|
|
DDIADestroy(struct rhdOutput *Output)
|
||
|
|
{
|
||
|
|
struct DDIAPrivate *Private = (struct DDIAPrivate *)Output->Private;
|
||
|
|
|
||
|
|
RHDFUNC(Output);
|
||
|
|
|
||
|
|
xfree(Private);
|
||
|
|
Output->Private = NULL;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
struct rhdOutput *
|
||
|
|
RHDDDIAInit(RHDPtr rhdPtr)
|
||
|
|
{
|
||
|
|
#ifdef ATOM_BIOS
|
||
|
|
struct rhdOutput *Output;
|
||
|
|
struct DDIAPrivate *Private;
|
||
|
|
AtomBiosArgRec data;
|
||
|
|
|
||
|
|
RHDFUNC(rhdPtr);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* This needs to be handled separately
|
||
|
|
* for now we only deal with it here.
|
||
|
|
*/
|
||
|
|
if (rhdPtr->ChipSet < RHD_RS600 || rhdPtr->ChipSet >= RHD_RS740)
|
||
|
|
return FALSE;
|
||
|
|
|
||
|
|
Output = xnfcalloc(sizeof(struct rhdOutput), 1);
|
||
|
|
|
||
|
|
Output->Name = "DDIA";
|
||
|
|
|
||
|
|
Output->scrnIndex = rhdPtr->scrnIndex;
|
||
|
|
Output->Id = RHD_OUTPUT_DVO;
|
||
|
|
|
||
|
|
Output->Sense = NULL;
|
||
|
|
Output->ModeValid = DDIAModeValid;
|
||
|
|
Output->Mode = DDIAMode;
|
||
|
|
Output->Power = DDIAPower;
|
||
|
|
Output->Save = DDIASave;
|
||
|
|
Output->Restore = DDIARestore;
|
||
|
|
Output->Destroy = DDIADestroy;
|
||
|
|
|
||
|
|
Private = xnfcalloc(1, sizeof(struct DDIAPrivate));
|
||
|
|
Output->Private = Private;
|
||
|
|
Private->Stored = FALSE;
|
||
|
|
|
||
|
|
if (RHDAtomBiosFunc(rhdPtr, rhdPtr->atomBIOS,
|
||
|
|
ATOM_GET_PCIENB_CFG_REG7, &data) == ATOM_SUCCESS) {
|
||
|
|
Private->PcieCfgReg7 = data.val;
|
||
|
|
} else {
|
||
|
|
xf86DrvMsg(Output->scrnIndex, X_ERROR, "Retrieval of PCIE MUX values failed. "
|
||
|
|
"no DDIA block support available\n");
|
||
|
|
goto error;
|
||
|
|
}
|
||
|
|
if (RHDAtomBiosFunc(rhdPtr, rhdPtr->atomBIOS,
|
||
|
|
ATOM_GET_CAPABILITY_FLAG, &data) == ATOM_SUCCESS) {
|
||
|
|
Private->CapabilityFlag = data.val;
|
||
|
|
} else {
|
||
|
|
xf86DrvMsg(Output->scrnIndex, X_ERROR, "Retrieval of Capability flag failed. "
|
||
|
|
"no DDIA block support available\n");
|
||
|
|
goto error;
|
||
|
|
}
|
||
|
|
|
||
|
|
return Output;
|
||
|
|
error:
|
||
|
|
xfree(Private);
|
||
|
|
return NULL;
|
||
|
|
|
||
|
|
#else
|
||
|
|
return NULL;
|
||
|
|
#endif
|
||
|
|
}
|