301 lines
8.0 KiB
C
301 lines
8.0 KiB
C
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/*
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* Copyright © 2013 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Shobhit Kumar <shobhit.kumar@intel.com>
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* Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com>
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*/
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#include <linux/kernel.h>
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#include "intel_drv.h"
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#include "i915_drv.h"
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#include "intel_dsi.h"
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#define DSI_HSS_PACKET_SIZE 4
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#define DSI_HSE_PACKET_SIZE 4
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#define DSI_HSA_PACKET_EXTRA_SIZE 6
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#define DSI_HBP_PACKET_EXTRA_SIZE 6
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#define DSI_HACTIVE_PACKET_EXTRA_SIZE 6
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#define DSI_HFP_PACKET_EXTRA_SIZE 6
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#define DSI_EOTP_PACKET_SIZE 4
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struct dsi_mnp {
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u32 dsi_pll_ctrl;
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u32 dsi_pll_div;
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};
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static const u32 lfsr_converts[] = {
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426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */
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461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */
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106, 53, 282, 397, 354, 227, 113, 56, 284, 142, /* 81 - 90 */
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71, 35 /* 91 - 92 */
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};
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#ifdef DSI_CLK_FROM_RR
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static u32 dsi_rr_formula(const struct drm_display_mode *mode,
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int pixel_format, int video_mode_format,
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int lane_count, bool eotp)
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{
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u32 bpp;
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u32 hactive, vactive, hfp, hsync, hbp, vfp, vsync, vbp;
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u32 hsync_bytes, hbp_bytes, hactive_bytes, hfp_bytes;
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u32 bytes_per_line, bytes_per_frame;
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u32 num_frames;
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u32 bytes_per_x_frames, bytes_per_x_frames_x_lanes;
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u32 dsi_bit_clock_hz;
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u32 dsi_clk;
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switch (pixel_format) {
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default:
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case VID_MODE_FORMAT_RGB888:
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case VID_MODE_FORMAT_RGB666_LOOSE:
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bpp = 24;
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break;
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case VID_MODE_FORMAT_RGB666:
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bpp = 18;
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break;
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case VID_MODE_FORMAT_RGB565:
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bpp = 16;
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break;
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}
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hactive = mode->hdisplay;
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vactive = mode->vdisplay;
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hfp = mode->hsync_start - mode->hdisplay;
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hsync = mode->hsync_end - mode->hsync_start;
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hbp = mode->htotal - mode->hsync_end;
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vfp = mode->vsync_start - mode->vdisplay;
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vsync = mode->vsync_end - mode->vsync_start;
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vbp = mode->vtotal - mode->vsync_end;
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hsync_bytes = DIV_ROUND_UP(hsync * bpp, 8);
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hbp_bytes = DIV_ROUND_UP(hbp * bpp, 8);
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hactive_bytes = DIV_ROUND_UP(hactive * bpp, 8);
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hfp_bytes = DIV_ROUND_UP(hfp * bpp, 8);
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bytes_per_line = DSI_HSS_PACKET_SIZE + hsync_bytes +
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DSI_HSA_PACKET_EXTRA_SIZE + DSI_HSE_PACKET_SIZE +
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hbp_bytes + DSI_HBP_PACKET_EXTRA_SIZE +
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hactive_bytes + DSI_HACTIVE_PACKET_EXTRA_SIZE +
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hfp_bytes + DSI_HFP_PACKET_EXTRA_SIZE;
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/*
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* XXX: Need to accurately calculate LP to HS transition timeout and add
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* it to bytes_per_line/bytes_per_frame.
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*/
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if (eotp && video_mode_format == VIDEO_MODE_BURST)
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bytes_per_line += DSI_EOTP_PACKET_SIZE;
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bytes_per_frame = vsync * bytes_per_line + vbp * bytes_per_line +
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vactive * bytes_per_line + vfp * bytes_per_line;
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if (eotp &&
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(video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE ||
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video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS))
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bytes_per_frame += DSI_EOTP_PACKET_SIZE;
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num_frames = drm_mode_vrefresh(mode);
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bytes_per_x_frames = num_frames * bytes_per_frame;
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bytes_per_x_frames_x_lanes = bytes_per_x_frames / lane_count;
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/* the dsi clock is divided by 2 in the hardware to get dsi ddr clock */
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dsi_bit_clock_hz = bytes_per_x_frames_x_lanes * 8;
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dsi_clk = dsi_bit_clock_hz / 1000;
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if (eotp && video_mode_format == VIDEO_MODE_BURST)
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dsi_clk *= 2;
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return dsi_clk;
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}
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#else
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/* Get DSI clock from pixel clock */
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static u32 dsi_clk_from_pclk(const struct drm_display_mode *mode,
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int pixel_format, int lane_count)
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{
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u32 dsi_clk_khz;
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u32 bpp;
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switch (pixel_format) {
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default:
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case VID_MODE_FORMAT_RGB888:
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case VID_MODE_FORMAT_RGB666_LOOSE:
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bpp = 24;
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break;
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case VID_MODE_FORMAT_RGB666:
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bpp = 18;
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break;
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case VID_MODE_FORMAT_RGB565:
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bpp = 16;
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break;
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}
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/* DSI data rate = pixel clock * bits per pixel / lane count
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pixel clock is converted from KHz to Hz */
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dsi_clk_khz = DIV_ROUND_CLOSEST(mode->clock * bpp, lane_count);
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return dsi_clk_khz;
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}
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#endif
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static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp)
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{
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u32 m, n, p;
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u32 ref_clk;
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u32 error;
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u32 tmp_error;
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int target_dsi_clk;
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int calc_dsi_clk;
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u32 calc_m;
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u32 calc_p;
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u32 m_seed;
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/* dsi_clk is expected in KHZ */
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if (dsi_clk < 300000 || dsi_clk > 1150000) {
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DRM_ERROR("DSI CLK Out of Range\n");
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return -ECHRNG;
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}
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ref_clk = 25000;
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target_dsi_clk = dsi_clk;
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error = 0xFFFFFFFF;
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tmp_error = 0xFFFFFFFF;
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calc_m = 0;
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calc_p = 0;
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for (m = 62; m <= 92; m++) {
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for (p = 2; p <= 6; p++) {
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/* Find the optimal m and p divisors
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with minimal error +/- the required clock */
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calc_dsi_clk = (m * ref_clk) / p;
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if (calc_dsi_clk == target_dsi_clk) {
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calc_m = m;
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calc_p = p;
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error = 0;
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break;
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} else
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tmp_error = abs(target_dsi_clk - calc_dsi_clk);
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if (tmp_error < error) {
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error = tmp_error;
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calc_m = m;
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calc_p = p;
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}
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}
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if (error == 0)
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break;
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}
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m_seed = lfsr_converts[calc_m - 62];
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n = 1;
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dsi_mnp->dsi_pll_ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2);
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dsi_mnp->dsi_pll_div = (n - 1) << DSI_PLL_N1_DIV_SHIFT |
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m_seed << DSI_PLL_M1_DIV_SHIFT;
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return 0;
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}
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/*
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* XXX: The muxing and gating is hard coded for now. Need to add support for
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* sharing PLLs with two DSI outputs.
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*/
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static void vlv_configure_dsi_pll(struct intel_encoder *encoder)
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{
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struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
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const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
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struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
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int ret;
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struct dsi_mnp dsi_mnp;
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u32 dsi_clk;
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dsi_clk = dsi_clk_from_pclk(mode, intel_dsi->pixel_format,
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intel_dsi->lane_count);
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ret = dsi_calc_mnp(dsi_clk, &dsi_mnp);
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if (ret) {
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DRM_DEBUG_KMS("dsi_calc_mnp failed\n");
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return;
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}
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dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
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DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n",
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dsi_mnp.dsi_pll_div, dsi_mnp.dsi_pll_ctrl);
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vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0);
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vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, dsi_mnp.dsi_pll_div);
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vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, dsi_mnp.dsi_pll_ctrl);
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}
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void vlv_enable_dsi_pll(struct intel_encoder *encoder)
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{
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struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
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u32 tmp;
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DRM_DEBUG_KMS("\n");
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mutex_lock(&dev_priv->dpio_lock);
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vlv_configure_dsi_pll(encoder);
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/* wait at least 0.5 us after ungating before enabling VCO */
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usleep_range(1, 10);
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tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
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tmp |= DSI_PLL_VCO_EN;
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vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp);
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mutex_unlock(&dev_priv->dpio_lock);
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if (wait_for(I915_READ(PIPECONF(PIPE_A)) & PIPECONF_DSI_PLL_LOCKED, 20)) {
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DRM_ERROR("DSI PLL lock failed\n");
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return;
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}
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DRM_DEBUG_KMS("DSI PLL locked\n");
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}
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void vlv_disable_dsi_pll(struct intel_encoder *encoder)
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{
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struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
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u32 tmp;
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DRM_DEBUG_KMS("\n");
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mutex_lock(&dev_priv->dpio_lock);
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tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
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tmp &= ~DSI_PLL_VCO_EN;
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tmp |= DSI_PLL_LDO_GATE;
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vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp);
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mutex_unlock(&dev_priv->dpio_lock);
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}
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