182 lines
6.2 KiB
C
182 lines
6.2 KiB
C
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/*
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* Copyright 2006-2007 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/*++
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Module Name:
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CD_OPCODEs.h
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Abstract:
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Defines Command Decoder OPCODEs
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Revision History:
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NEG:24.09.2002 Initiated.
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--*/
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#ifndef _CD_OPCODES_H_
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#define _CD_OPCODES_H_
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typedef enum _OPCODE {
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Reserved_00= 0, // 0 = 0x00
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// MOVE_ group
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MOVE_REG_OPCODE, // 1 = 0x01
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FirstValidCommand=MOVE_REG_OPCODE,
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MOVE_PS_OPCODE, // 2 = 0x02
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MOVE_WS_OPCODE, // 3 = 0x03
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MOVE_FB_OPCODE, // 4 = 0x04
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MOVE_PLL_OPCODE, // 5 = 0x05
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MOVE_MC_OPCODE, // 6 = 0x06
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// Logic group
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AND_REG_OPCODE, // 7 = 0x07
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AND_PS_OPCODE, // 8 = 0x08
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AND_WS_OPCODE, // 9 = 0x09
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AND_FB_OPCODE, // 10 = 0x0A
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AND_PLL_OPCODE, // 11 = 0x0B
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AND_MC_OPCODE, // 12 = 0x0C
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OR_REG_OPCODE, // 13 = 0x0D
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OR_PS_OPCODE, // 14 = 0x0E
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OR_WS_OPCODE, // 15 = 0x0F
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OR_FB_OPCODE, // 16 = 0x10
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OR_PLL_OPCODE, // 17 = 0x11
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OR_MC_OPCODE, // 18 = 0x12
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SHIFT_LEFT_REG_OPCODE, // 19 = 0x13
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SHIFT_LEFT_PS_OPCODE, // 20 = 0x14
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SHIFT_LEFT_WS_OPCODE, // 21 = 0x15
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SHIFT_LEFT_FB_OPCODE, // 22 = 0x16
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SHIFT_LEFT_PLL_OPCODE, // 23 = 0x17
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SHIFT_LEFT_MC_OPCODE, // 24 = 0x18
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SHIFT_RIGHT_REG_OPCODE, // 25 = 0x19
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SHIFT_RIGHT_PS_OPCODE, // 26 = 0x1A
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SHIFT_RIGHT_WS_OPCODE, // 27 = 0x1B
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SHIFT_RIGHT_FB_OPCODE, // 28 = 0x1C
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SHIFT_RIGHT_PLL_OPCODE, // 29 = 0x1D
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SHIFT_RIGHT_MC_OPCODE, // 30 = 0x1E
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// Arithmetic group
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MUL_REG_OPCODE, // 31 = 0x1F
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MUL_PS_OPCODE, // 32 = 0x20
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MUL_WS_OPCODE, // 33 = 0x21
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MUL_FB_OPCODE, // 34 = 0x22
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MUL_PLL_OPCODE, // 35 = 0x23
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MUL_MC_OPCODE, // 36 = 0x24
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DIV_REG_OPCODE, // 37 = 0x25
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DIV_PS_OPCODE, // 38 = 0x26
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DIV_WS_OPCODE, // 39 = 0x27
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DIV_FB_OPCODE, // 40 = 0x28
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DIV_PLL_OPCODE, // 41 = 0x29
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DIV_MC_OPCODE, // 42 = 0x2A
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ADD_REG_OPCODE, // 43 = 0x2B
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ADD_PS_OPCODE, // 44 = 0x2C
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ADD_WS_OPCODE, // 45 = 0x2D
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ADD_FB_OPCODE, // 46 = 0x2E
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ADD_PLL_OPCODE, // 47 = 0x2F
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ADD_MC_OPCODE, // 48 = 0x30
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SUB_REG_OPCODE, // 49 = 0x31
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SUB_PS_OPCODE, // 50 = 0x32
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SUB_WS_OPCODE, // 51 = 0x33
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SUB_FB_OPCODE, // 52 = 0x34
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SUB_PLL_OPCODE, // 53 = 0x35
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SUB_MC_OPCODE, // 54 = 0x36
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// Control grouop
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SET_ATI_PORT_OPCODE, // 55 = 0x37
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SET_PCI_PORT_OPCODE, // 56 = 0x38
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SET_SYS_IO_PORT_OPCODE, // 57 = 0x39
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SET_REG_BLOCK_OPCODE, // 58 = 0x3A
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SET_FB_BASE_OPCODE, // 59 = 0x3B
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COMPARE_REG_OPCODE, // 60 = 0x3C
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COMPARE_PS_OPCODE, // 61 = 0x3D
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COMPARE_WS_OPCODE, // 62 = 0x3E
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COMPARE_FB_OPCODE, // 63 = 0x3F
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COMPARE_PLL_OPCODE, // 64 = 0x40
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COMPARE_MC_OPCODE, // 65 = 0x41
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SWITCH_OPCODE, // 66 = 0x42
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JUMP__OPCODE, // 67 = 0x43
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JUMP_EQUAL_OPCODE, // 68 = 0x44
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JUMP_BELOW_OPCODE, // 69 = 0x45
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JUMP_ABOVE_OPCODE, // 70 = 0x46
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JUMP_BELOW_OR_EQUAL_OPCODE, // 71 = 0x47
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JUMP_ABOVE_OR_EQUAL_OPCODE, // 72 = 0x48
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JUMP_NOT_EQUAL_OPCODE, // 73 = 0x49
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TEST_REG_OPCODE, // 74 = 0x4A
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TEST_PS_OPCODE, // 75 = 0x4B
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TEST_WS_OPCODE, // 76 = 0x4C
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TEST_FB_OPCODE, // 77 = 0x4D
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TEST_PLL_OPCODE, // 78 = 0x4E
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TEST_MC_OPCODE, // 79 = 0x4F
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DELAY_MILLISEC_OPCODE, // 80 = 0x50
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DELAY_MICROSEC_OPCODE, // 81 = 0x51
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CALL_TABLE_OPCODE, // 82 = 0x52
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REPEAT_OPCODE, // 83 = 0x53
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// Miscellaneous group
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CLEAR_REG_OPCODE, // 84 = 0x54
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CLEAR_PS_OPCODE, // 85 = 0x55
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CLEAR_WS_OPCODE, // 86 = 0x56
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CLEAR_FB_OPCODE, // 87 = 0x57
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CLEAR_PLL_OPCODE, // 88 = 0x58
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CLEAR_MC_OPCODE, // 89 = 0x59
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NOP_OPCODE, // 90 = 0x5A
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EOT_OPCODE, // 91 = 0x5B
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MASK_REG_OPCODE, // 92 = 0x5C
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MASK_PS_OPCODE, // 93 = 0x5D
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MASK_WS_OPCODE, // 94 = 0x5E
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MASK_FB_OPCODE, // 95 = 0x5F
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MASK_PLL_OPCODE, // 96 = 0x60
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MASK_MC_OPCODE, // 97 = 0x61
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// BIOS dedicated group
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POST_CARD_OPCODE, // 98 = 0x62
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BEEP_OPCODE, // 99 = 0x63
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SAVE_REG_OPCODE, // 100 = 0x64
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RESTORE_REG_OPCODE, // 101 = 0x65
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SET_DATA_BLOCK_OPCODE, // 102 = 0x66
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XOR_REG_OPCODE, // 103 = 0x67
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XOR_PS_OPCODE, // 104 = 0x68
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XOR_WS_OPCODE, // 105 = 0x69
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XOR_FB_OPCODE, // 106 = 0x6a
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XOR_PLL_OPCODE, // 107 = 0x6b
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XOR_MC_OPCODE, // 108 = 0x6c
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SHL_REG_OPCODE, // 109 = 0x6d
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SHL_PS_OPCODE, // 110 = 0x6e
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SHL_WS_OPCODE, // 111 = 0x6f
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SHL_FB_OPCODE, // 112 = 0x70
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SHL_PLL_OPCODE, // 113 = 0x71
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SHL_MC_OPCODE, // 114 = 0x72
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SHR_REG_OPCODE, // 115 = 0x73
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SHR_PS_OPCODE, // 116 = 0x74
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SHR_WS_OPCODE, // 117 = 0x75
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SHR_FB_OPCODE, // 118 = 0x76
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SHR_PLL_OPCODE, // 119 = 0x77
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SHR_MC_OPCODE, // 120 = 0x78
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DEBUG_OPCODE, // 121 = 0x79
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CTB_DS_OPCODE, // 122 = 0x7A
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LastValidCommand = CTB_DS_OPCODE,
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// Extension specificaTOR
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Extension = 0x80, // 128 = 0x80 // Next byte is an OPCODE as well
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Reserved_FF = 255 // 255 = 0xFF
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}OPCODE;
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#endif // _CD_OPCODES_H_
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