Add chip type detection. Only QCA816x/7x supported so far.
git-svn-id: svn://kolibrios.org@7827 a494cfbc-eb01-0410-851d-a64ba20cac60
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hidnplayr
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@ -7,7 +7,10 @@
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;; ;;
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;; ;;
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;; based on alx driver from TI-OpenLink ;;
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;; based on alx driver from TI-OpenLink ;;
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;; ;;
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;; ;;
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;; Written by hidnplayr (hidnplayr@gmail.com) ;;
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;; Written by hidnplayr (hidnplayr@gmail.com) ;;
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;; ;;
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;; Thanks to: floppy121 for kindly providing me with the hardware ;;
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;; that made the development of this driver possible. ;;
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;; ;;
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;; ;;
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;; GNU GENERAL PUBLIC LICENSE ;;
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;; GNU GENERAL PUBLIC LICENSE ;;
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;; Version 2, June 1991 ;;
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;; Version 2, June 1991 ;;
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@ -77,6 +80,8 @@ struct device ETH_DEVICE
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io_addr dd ?
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io_addr dd ?
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pci_bus dd ?
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pci_bus dd ?
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pci_dev dd ?
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pci_dev dd ?
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pci_vid dw ? ; Vendor ID
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pci_did dw ? ; Device ID
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irq_line dd ?
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irq_line dd ?
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pci_rev dd ?
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pci_rev dd ?
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chip_rev dd ?
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chip_rev dd ?
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@ -311,6 +316,25 @@ probe:
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and ax, not(PCI_CMD_INTX_DISABLE)
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and ax, not(PCI_CMD_INTX_DISABLE)
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invoke PciWrite16, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.command, eax
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invoke PciWrite16, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.command, eax
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; get device id
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invoke PciRead16, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.device_id
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mov [ebx + device.pci_did], ax
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mov esi, chiplist
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.loop:
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cmp word[esi+2], ax
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je .got_it
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add esi, 8
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cmp esi, chiplist + 6*8
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jbe .loop
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DEBUGF 2, "Unknown chip: 0x%x, continuing anyway\n", ax
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jmp .done
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.got_it:
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mov eax, dword[esi+4]
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mov [ebx + device.name], eax
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DEBUGF 1, "Chip type = %s\n", eax
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.done:
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; get revision id.
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; get revision id.
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invoke PciRead8, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.revision_id
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invoke PciRead8, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.revision_id
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and eax, 0xff
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and eax, 0xff
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@ -318,7 +342,7 @@ probe:
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shr al, ALX_PCI_REVID_SHIFT
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shr al, ALX_PCI_REVID_SHIFT
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mov [ebx + device.chip_rev], eax
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mov [ebx + device.chip_rev], eax
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DEBUGF 1,"revision: %u\n", al
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DEBUGF 1,"Revision: %u\n", al
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;;; call alx_reset_pcie
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;;; call alx_reset_pcie
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@ -545,6 +569,8 @@ alx_identify_hw:
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ret
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ret
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.einval:
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.einval:
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DEBUGF 1, "Invalid revision 0x%x\n", [ebx + device.chip_rev]
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xor eax, eax
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xor eax, eax
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dec eax
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dec eax
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ret
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ret
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@ -923,6 +949,7 @@ alx_read_macaddr:
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ret
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ret
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.invalid:
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.invalid:
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DEBUGF 1, "Invalid MAC!\n"
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xor eax, eax
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xor eax, eax
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inc eax
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inc eax
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ret
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ret
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@ -1406,7 +1433,7 @@ alx_configure_basic:
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or (ALX_RXQ0_IDT_TBL_SIZE_DEF shl ALX_RXQ0_IDT_TBL_SIZE_SHIFT) \
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or (ALX_RXQ0_IDT_TBL_SIZE_DEF shl ALX_RXQ0_IDT_TBL_SIZE_SHIFT) \
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or ALX_RXQ0_RSS_HSTYP_ALL or ALX_RXQ0_RSS_HASH_EN or ALX_RXQ0_IPV6_PARSE_EN
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or ALX_RXQ0_RSS_HSTYP_ALL or ALX_RXQ0_RSS_HASH_EN or ALX_RXQ0_IPV6_PARSE_EN
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test [ebx + device.pci_dev], 1 ;;; FIXME: is gigabit device?
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test [ebx + device.pci_did], 1 ;;; FIXME: is gigabit device?
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jz @f
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jz @f
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or eax, ALX_RXQ0_ASPM_THRESH_100M shl ALX_RXQ0_ASPM_THRESH_SHIFT
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or eax, ALX_RXQ0_ASPM_THRESH_100M shl ALX_RXQ0_ASPM_THRESH_SHIFT
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@@:
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@@:
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@ -1746,6 +1773,27 @@ include '../peimport.inc'
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my_service db 'AR81XX',0 ; max 16 chars include zero
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my_service db 'AR81XX',0 ; max 16 chars include zero
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chiplist:
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dd (ALX_DEV_ID_AR8131 shl 16) or ALX_VEN_ID, ar8131_sz
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dd (ALX_DEV_ID_AR8161 shl 16) or ALX_VEN_ID, ar8161_sz
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dd (ALX_DEV_ID_AR8162 shl 16) or ALX_VEN_ID, ar8162_sz
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dd (ALX_DEV_ID_AR8171 shl 16) or ALX_VEN_ID, ar8171_sz
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dd (ALX_DEV_ID_AR8172 shl 16) or ALX_VEN_ID, ar8172_sz
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dd (ALX_DEV_ID_E2200 shl 16) or ALX_VEN_ID, e2200_sz
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dd (ALX_DEV_ID_E2400 shl 16) or ALX_VEN_ID, e2400_sz
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dd (ALX_DEV_ID_E2500 shl 16) or ALX_VEN_ID, e2500_sz
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dd 0
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ar8131_sz db "AR8131", 0
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ar8161_sz db "AR8161", 0
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ar8162_sz db "AR8162", 0
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ar8171_sz db "QCA8171", 0
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ar8172_sz db "QCA8172", 0
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e2200_sz db "Killer E2200", 0
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e2400_sz db "Killer E2400", 0
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e2500_sz db "Killer E2500", 0
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include_debug_strings
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include_debug_strings
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align 4
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align 4
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@ -1,3 +1,6 @@
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ALX_VEN_ID = 0x1969
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ALX_DEV_ID_AR8131 = 0x1063
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ALX_DEV_ID_AR8161 = 0x1091
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ALX_DEV_ID_AR8161 = 0x1091
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ALX_DEV_ID_E2200 = 0xe091
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ALX_DEV_ID_E2200 = 0xe091
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ALX_DEV_ID_E2400 = 0xe0a1
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ALX_DEV_ID_E2400 = 0xe0a1
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