A sys func. 62 have call without cross registers.
git-svn-id: svn://kolibrios.org@1587 a494cfbc-eb01-0410-851d-a64ba20cac60
This commit is contained in:
Alexey Teplov (
parent
f261636169
commit
0b08e1d642
@ -1,6 +1,6 @@
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; ;;
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;; Copyright (C) KolibriOS team 2004-2007. All rights reserved. ;;
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;; Copyright (C) KolibriOS team 2004-2010. All rights reserved. ;;
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;; Distributed under terms of the GNU General Public License ;;
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;; ;;
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;; ;;
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@ -8,13 +8,11 @@
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;; ;;
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;; 32 bit PCI driver code ;;
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;; ;;
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;; Version 0.4 February 2nd, 2010 ;;
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;; Version 0.3 April 9, 2007 ;;
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;; Version 0.2 December 21st, 2002 ;;
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;; ;;
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;; Author: Victor Prodan, victorprodan@yahoo.com ;;
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;; Mihailov Ilia, ghost.nsk@gmail.com ;;
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;; Artem Jerdev, kolibri@jerdev.co.uk ;;
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;; Credits: ;;
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;; Ralf Brown ;;
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;; Mike Hibbett, mikeh@oceanfree.net ;;
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@ -32,64 +30,116 @@ $Revision$
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; Description
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; entry point for system PCI calls
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;***************************************************************************
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mmio_pci_addr dw 0x400 ; default PCI device bdf-address
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mmio_pci_addr equ 0x400 ; set actual PCI address here to activate user-MMIO
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iglobal
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align 4
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f62call:
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dd pci_api.0
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dd pci_api.1
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dd pci_api.2
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dd pci_api.not_support ;3
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dd pci_read_reg ;4 byte
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dd pci_read_reg ;5 word
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dd pci_read_reg ;6 dword
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dd pci_api.not_support ;7
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dd pci_write_reg ;8 byte
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dd pci_write_reg ;9 word
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dd pci_write_reg ;10 dword
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if defined mmio_pci_addr
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dd pci_mmio_init ;11
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dd pci_mmio_map ;12
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dd pci_mmio_unmap ;13
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end if
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f62_rcall:
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dd pci_read_reg.0 ;4 byte
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dd pci_read_reg.1 ;5 word
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dd pci_read_reg.2 ;6 dword
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f62_rcall2:
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dd pci_read_reg_2.0 ;4 byte
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dd pci_read_reg_2.1 ;5 word
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dd pci_read_reg_2.2 ;6 dword
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f62_wcall:
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dd pci_write_reg.0 ;4 byte
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dd pci_write_reg.1 ;5 word
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dd pci_write_reg.2 ;6 dword
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f62_wcall2:
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dd pci_write_reg_2.0 ;4 byte
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dd pci_write_reg_2.1 ;5 word
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dd pci_write_reg_2.2 ;6 dword
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endg
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align 4
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pci_api:
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movzx eax,bl
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cmp [pci_access_enabled],1
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jne no_pci_access_for_applications
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jne .no_pci_access_for_applications
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or al,al
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jnz pci_fn_1
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if defined mmio_pci_addr
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cmp eax, 13
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jb .not_support
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else
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cmp eax, 10
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jb .not_support
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end if
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call dword [f62call+eax*4]
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mov dword [esp+32],eax
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ret
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; or al,al
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; jnz pci_fn_1
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; PCI function 0: get pci version (AH.AL)
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movzx eax,word [BOOT_VAR+0x9022]
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.0:
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movzx eax, word [BOOT_VAR+0x9022]
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ret
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pci_fn_1:
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cmp al,1
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jnz pci_fn_2
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;pci_fn_1:
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; cmp al,1
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; jnz pci_fn_2
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; PCI function 1: get last bus in AL
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mov al,[BOOT_VAR+0x9021]
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.1:
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movzx eax, byte [BOOT_VAR+0x9021]
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ret
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pci_fn_2:
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cmp al,2
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jne pci_fn_3
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;pci_fn_2:
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; cmp al,2
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; jne pci_fn_3
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; PCI function 2: get pci access mechanism
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mov al,[BOOT_VAR+0x9020]
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.2:
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movzx eax, byte [BOOT_VAR+0x9020]
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ret
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pci_fn_3:
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;pci_fn_3:
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cmp al,4
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jz pci_read_reg ;byte
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cmp al,5
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jz pci_read_reg ;word
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cmp al,6
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jz pci_read_reg ;dword
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; cmp al,4
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; jz pci_read_reg ;byte
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; cmp al,5
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; jz pci_read_reg ;word
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; cmp al,6
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; jz pci_read_reg ;dword
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cmp al,8
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jz pci_write_reg ;byte
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cmp al,9
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jz pci_write_reg ;word
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cmp al,10
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jz pci_write_reg ;dword
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; cmp al,8
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; jz pci_write_reg ;byte
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; cmp al,9
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; jz pci_write_reg ;word
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; cmp al,10
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; jz pci_write_reg ;dword
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cmp al,11 ; user-level MMIO functions
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jz pci_mmio_init
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cmp al,12
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jz pci_mmio_map
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cmp al,13
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jz pci_mmio_unmap
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no_pci_access_for_applications:
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or eax,-1
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;if defined mmio_pci_addr
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; cmp al,11 ; user-level MMIO functions
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; jz pci_mmio_init
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; cmp al,12
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; jz pci_mmio_map
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; cmp al,13
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; jz pci_mmio_unmap
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;end if
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.not_support:
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.no_pci_access_for_applications:
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or eax,-1
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ret
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;***************************************************************************
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@ -98,20 +148,20 @@ pci_fn_3:
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;
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; Description
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; creates a command dword for use with the PCI bus
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; bus # in ah
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; device+func in bh (dddddfff)
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; register in bl
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; bus # in bh;ah
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; device+func in ch;bh (dddddfff)
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; register in cl;bl
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;
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; command dword returned in eax ( 10000000 bbbbbbbb dddddfff rrrrrr00 )
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; command dword returned in ebx;eax ( 10000000 bbbbbbbb dddddfff rrrrrr00 )
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;***************************************************************************
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align 4
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pci_make_config_cmd:
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shl eax,8 ; move bus to bits 16-23
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mov ax,bx ; combine all
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and eax,0xffffff
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or eax,0x80000000
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shl ebx,8;eax,8 ; move bus to bits 16-23
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mov bx,cx;ax,bx ; combine all
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and ebx,0xffffff;eax,0xffffff
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or ebx,0x80000000;eax,0x80000000
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ret
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;***************************************************************************
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@ -128,12 +178,16 @@ pci_make_config_cmd:
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align 4
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pci_read_reg:
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push esi ; save register size into ESI
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mov esi,eax
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cmp byte [BOOT_VAR+0x9020],2 ;what mechanism will we use?
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je pci_read_reg_2
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; mechanism 1
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; push esi ; save register size into ESI
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mov esi,ebx;eax
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and esi,3
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call pci_make_config_cmd
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mov ebx,eax
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mov eax,ebx;ebx,eax
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; get current state
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mov dx,0xcf8
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in eax, dx
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@ -147,37 +201,100 @@ pci_read_reg:
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and bl,3
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or dl,bl ; add to port address first 2 bits of register address
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or esi,esi
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jz pci_read_byte1
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cmp esi,1
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jz pci_read_word1
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cmp esi,2
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jz pci_read_dword1
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jmp pci_fin_read1
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; or esi,esi
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; jz pci_read_byte1
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; cmp esi,1
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; jz pci_read_word1
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; cmp esi,2
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; jz pci_read_dword1
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; jmp pci_fin_read1
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jmp dword [f62_rcall+esi*4]
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pci_read_byte1:
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.0:
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in al,dx
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jmp pci_fin_read1
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pci_read_word1:
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jmp .pci_fin_read1
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.1:
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in ax,dx
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jmp pci_fin_read1
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pci_read_dword1:
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jmp .pci_fin_read1
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.2:
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in eax,dx
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jmp pci_fin_read1
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pci_fin_read1:
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; jmp pci_fin_read1
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.pci_fin_read1:
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; restore configuration control
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xchg eax,[esp]
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mov dx,0xcf8
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out dx,eax
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pop eax
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pop esi
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;pop esi
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ret
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pci_read_reg_2:
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test ch,128;bh,128 ;mech#2 only supports 16 devices per bus
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jnz pci_api.not_support
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; push esi ; save register size into ESI
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mov esi,ebx;eax
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and esi,3
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push ebx;eax
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mov eax,ebx
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;store current state of config space
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mov dx,0xcf8
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in al,dx
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mov ah,al
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mov dl,0xfa
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in al,dx
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xchg eax,[esp]
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; out 0xcfa,bus
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mov al,ah
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out dx,al
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; out 0xcf8,0x80
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mov dl,0xf8
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mov al,0x80
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out dx,al
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; compute addr
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shr ch,3;bh,3 ; func is ignored in mechanism 2
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or ch,0xc0;bh,0xc0
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mov dx,cx;bx
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; or esi,esi
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; jz pci_read_byte2
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; cmp esi,1
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; jz pci_read_word2
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; cmp esi,2
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; jz pci_read_dword2
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; jmp pci_fin_read2
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jmp dword [f62_rcall2+esi*4]
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.0:
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in al,dx
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jmp .pci_fin_read2
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.1:
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in ax,dx
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jmp .pci_fin_read2
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.2:
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in eax,dx
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; jmp pci_fin_read2
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.pci_fin_read2:
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; restore configuration space
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xchg eax,[esp]
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mov dx,0xcfa
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out dx,al
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mov dl,0xf8
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mov al,ah
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out dx,al
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pop eax
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; pop esi
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ret
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pci_read_reg_err:
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xor eax,eax
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dec eax
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ret
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;pci_read_reg_err:
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; or dword [esp+32],-1
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; ret
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;***************************************************************************
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@ -195,12 +312,17 @@ pci_read_reg_err:
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align 4
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pci_write_reg:
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push esi ; save register size into ESI
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mov esi,eax
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and esi,3
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cmp byte [BOOT_VAR+0x9020],2 ;what mechanism will we use?
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je pci_write_reg_2
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; mechanism 1
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; push esi ; save register size into ESI
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mov esi,ebx;eax
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and esi,3 ;not need
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call pci_make_config_cmd
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mov ebx,eax
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mov eax,ebx;ebx,eax
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mov ecx,edx ;cross registers
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; get current state into ecx
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mov dx,0xcf8
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in eax, dx
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@ -215,56 +337,121 @@ pci_write_reg:
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or dl,bl
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mov eax,ecx
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or esi,esi
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jz pci_write_byte1
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cmp esi,1
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jz pci_write_word1
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cmp esi,2
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jz pci_write_dword1
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jmp pci_fin_write1
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pci_write_byte1:
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; or esi,esi
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; jz pci_write_byte1
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; cmp esi,1
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; jz pci_write_word1
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; cmp esi,2
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; jz pci_write_dword1
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; jmp pci_fin_write1
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jmp dword [f62_wcall+esi*4]
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.0:
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out dx,al
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jmp pci_fin_write1
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pci_write_word1:
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jmp .pci_fin_write1
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.1:
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out dx,ax
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jmp pci_fin_write1
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pci_write_dword1:
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jmp .pci_fin_write1
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.2:
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out dx,eax
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jmp pci_fin_write1
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pci_fin_write1:
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.pci_fin_write1:
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; restore configuration control
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pop eax
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mov dl,0xf8
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out dx,eax
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xor eax,eax
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pop esi
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;pop esi
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ret
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pci_write_reg_2:
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test ch,128;bh,128 ;mech#2 only supports 16 devices per bus
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jnz pci_api.not_support
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; push esi ; save register size into ESI
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mov esi,eax
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and esi,3 ;not need
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push eax
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mov ecx,edx ;cross registers
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;store current state of config space
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mov dx,0xcf8
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in al,dx
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mov ah,al
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mov dl,0xfa
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in al,dx
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xchg eax,[esp]
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; out 0xcfa,bus
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mov al,ah
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out dx,al
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; out 0xcf8,0x80
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mov dl,0xf8
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mov al,0x80
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out dx,al
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; compute addr
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shr bh,3 ; func is ignored in mechanism 2
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or bh,0xc0
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mov dx,bx
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; write register
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mov eax,ecx
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; or esi,esi
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; jz pci_write_byte2
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; cmp esi,1
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; jz pci_write_word2
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; cmp esi,2
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; jz pci_write_dword2
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; jmp pci_fin_write2
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jmp dword [f62_wcall2+esi*4]
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.0:
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out dx,al
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jmp .pci_fin_write2
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.1:
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out dx,ax
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jmp .pci_fin_write2
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.2:
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out dx,eax
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.pci_fin_write2:
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; restore configuration space
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pop eax
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mov dx,0xcfa
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out dx,al
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mov dl,0xf8
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mov al,ah
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out dx,al
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pci_write_reg_err:
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xor eax,eax
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dec eax
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;pop esi
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ret
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;pci_write_reg_err:
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; xor eax,eax
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; dec eax
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; ret
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if defined mmio_pci_addr ; must be set above
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;***************************************************************************
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; Function
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; pci_mmio_init
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;
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; Description
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; IN: bx = device's PCI bus address (bbbbbbbbdddddfff)
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; Returns eax = phys. address of user-accessible DMA block
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; IN: cx = device's PCI bus address (bbbbbbbbdddddfff)
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; Returns eax = user heap space available (bytes)
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; Error codes
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; eax = -1 : PCI user access blocked,
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; eax = -2 : device not registered for uMMIO service
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; eax = -3 : user heap initialization failure
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;***************************************************************************
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pci_mmio_init:
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mov [mmio_pci_addr],bx
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cmp cx, mmio_pci_addr
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jz @f
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mov eax,-2
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ret
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@@:
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call init_heap ; (if not initialized yet)
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or eax,eax
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jz @f
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mov eax, [UserDMAaddr]
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ret
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@@:
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mov eax,-3
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@ -278,9 +465,10 @@ pci_mmio_init:
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; Description
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; maps a block of PCI memory to user-accessible linear address
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;
|
||||
; WARNING! This VERY EXPERIMENTAL service is for one chosen PCI device only!
|
||||
; The target device address should be set in kernel var mmio_pci_addr
|
||||
;
|
||||
; IN: ah = BAR#; or
|
||||
; IN: ah = 0xDA for DMA-mapping requests;
|
||||
; IN: ah = BAR#;
|
||||
; IN: ebx = block size (bytes);
|
||||
; IN: ecx = offset in MMIO block (in 4K-pages, to avoid misaligned pages);
|
||||
;
|
||||
@ -296,21 +484,17 @@ pci_mmio_init:
|
||||
;***************************************************************************
|
||||
|
||||
pci_mmio_map:
|
||||
;cross
|
||||
mov eax,ebx
|
||||
mov ebx,ecx
|
||||
mov ecx,edx
|
||||
;;;;;;;;;;;;;;;;;;;
|
||||
and edx,0x0ffff
|
||||
cmp ah, 0xDA
|
||||
jz .dma_map
|
||||
cmp ah,6
|
||||
jc .bar_0_5
|
||||
jz .bar_rom
|
||||
jc .bar_0_5
|
||||
jz .bar_rom
|
||||
mov eax,-2
|
||||
ret
|
||||
|
||||
.dma_map:
|
||||
push ecx
|
||||
mov ecx,ebx
|
||||
mov eax,[UserDMAaddr]
|
||||
jmp .allocate_block
|
||||
|
||||
.bar_rom:
|
||||
mov ah, 8 ; bar6 = Expansion ROM base address
|
||||
.bar_0_5:
|
||||
@ -322,7 +506,7 @@ pci_mmio_map:
|
||||
shl bl, 1
|
||||
shl bl, 1
|
||||
add bl, 0x10 ; now bl = BAR offset in PCI config. space
|
||||
mov ax, [mmio_pci_addr]
|
||||
mov ax, mmio_pci_addr
|
||||
mov bh, al ; bh = dddddfff
|
||||
mov al, 2 ; al : DW to read
|
||||
call pci_read_reg
|
||||
@ -339,9 +523,7 @@ pci_mmio_map:
|
||||
pop ecx ; ecx = block size, bytes (expanded to whole page)
|
||||
mov ebx, ecx ; user_alloc destroys eax, ecx, edx, but saves ebx
|
||||
and eax, 0xFFFFFFF0
|
||||
|
||||
.allocate_block:
|
||||
push eax ; store MMIO physical address + keep the stack 2x4b deep
|
||||
push eax ; store MMIO physical address + keep 2DWords in the stack
|
||||
stdcall user_alloc, ecx
|
||||
or eax, eax
|
||||
jnz mmio_map_over
|
||||
@ -360,7 +542,9 @@ mmio_map_over:
|
||||
pop edx ; edx = MMIO shift (pages)
|
||||
shl edx, 12 ; edx = MMIO shift (bytes)
|
||||
add eax, edx ; eax = uMMIO physical address
|
||||
or eax, (PG_SHARED+PG_UW+PG_NOCACHE)
|
||||
or eax, PG_SHARED
|
||||
or eax, PG_UW
|
||||
or eax, PG_NOCACHE
|
||||
mov edi, ebx
|
||||
call commit_pages
|
||||
mov eax, edi
|
||||
@ -382,9 +566,11 @@ mmio_map_over:
|
||||
;***************************************************************************
|
||||
|
||||
pci_mmio_unmap:
|
||||
stdcall user_free, ebx
|
||||
stdcall user_free, ecx;ebx
|
||||
ret
|
||||
|
||||
end if
|
||||
|
||||
;-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
|
||||
uglobal
|
||||
align 4
|
||||
|
||||
@ -99,7 +99,7 @@ iglobal
|
||||
dd 0
|
||||
dd 0
|
||||
dd 0
|
||||
dd sys_pci ; 62-PCI functions
|
||||
dd 0;sys_pci ; 62-PCI functions
|
||||
dd sys_msg_board ; 63-System message board
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
@ -170,7 +170,7 @@ iglobal
|
||||
dd undefined_syscall ; 59-reserved
|
||||
dd sys_IPC ; 60-Inter Process Communication
|
||||
dd sys_gs ; 61-Direct graphics access
|
||||
dd cross_order ; 62-PCI functions
|
||||
dd pci_api;cross_order ; 62-PCI functions
|
||||
dd cross_order ; 63-System message board
|
||||
dd sys_resize_app_memory ; 64-Resize application memory usage
|
||||
dd sys_putimage_palette ; 65-PutImagePalette
|
||||
|
||||
@ -4251,13 +4251,13 @@ sys_gs: ; direct screen access
|
||||
ret
|
||||
|
||||
|
||||
align 4 ; PCI functions
|
||||
|
||||
sys_pci:
|
||||
|
||||
call pci_api
|
||||
mov [esp+36],eax
|
||||
ret
|
||||
;align 4 ; PCI functions
|
||||
;
|
||||
;sys_pci:
|
||||
;
|
||||
; call pci_api
|
||||
; mov [esp+36],eax
|
||||
; ret
|
||||
|
||||
|
||||
align 4 ; system functions
|
||||
|
||||
Loading…
Reference in New Issue
Block a user