initialize framebuffer
git-svn-id: svn://kolibrios.org@2335 a494cfbc-eb01-0410-851d-a64ba20cac60
This commit is contained in:
Sergey Semyonov (Serge)
parent
4151b7bbc2
commit
14a185a759
@ -1314,26 +1314,134 @@ i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
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return 0;
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}
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#if 0
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int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
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enum i915_cache_level cache_level)
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{
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int ret;
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if (obj->cache_level == cache_level)
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return 0;
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if (obj->pin_count) {
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DRM_DEBUG("can not change the cache level of pinned objects\n");
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return -EBUSY;
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}
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if (obj->gtt_space) {
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ret = i915_gem_object_finish_gpu(obj);
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if (ret)
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return ret;
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i915_gem_object_finish_gtt(obj);
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/* Before SandyBridge, you could not use tiling or fence
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* registers with snooped memory, so relinquish any fences
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* currently pointing to our region in the aperture.
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*/
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if (INTEL_INFO(obj->base.dev)->gen < 6) {
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ret = i915_gem_object_put_fence(obj);
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if (ret)
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return ret;
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}
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i915_gem_gtt_rebind_object(obj, cache_level);
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}
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if (cache_level == I915_CACHE_NONE) {
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u32 old_read_domains, old_write_domain;
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/* If we're coming from LLC cached, then we haven't
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* actually been tracking whether the data is in the
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* CPU cache or not, since we only allow one bit set
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* in obj->write_domain and have been skipping the clflushes.
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* Just set it to the CPU cache for now.
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*/
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WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
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WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
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old_read_domains = obj->base.read_domains;
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old_write_domain = obj->base.write_domain;
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obj->base.read_domains = I915_GEM_DOMAIN_CPU;
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obj->base.write_domain = I915_GEM_DOMAIN_CPU;
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trace_i915_gem_object_change_domain(obj,
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old_read_domains,
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old_write_domain);
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}
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obj->cache_level = cache_level;
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return 0;
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}
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#endif
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/*
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* Prepare buffer for display plane (scanout, cursors, etc).
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* Can be called from an uninterruptible phase (modesetting) and allows
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* any flushes to be pipelined (for pageflips).
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*
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* For the display plane, we want to be in the GTT but out of any write
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* domains. So in many ways this looks like set_to_gtt_domain() apart from the
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* ability to pipeline the waits, pinning and any additional subtleties
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* that may differentiate the display plane from ordinary buffers.
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*/
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int
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i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
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u32 alignment,
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struct intel_ring_buffer *pipelined)
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{
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u32 old_read_domains, old_write_domain;
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int ret;
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ret = i915_gem_object_flush_gpu_write_domain(obj);
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if (ret)
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return ret;
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if (pipelined != obj->ring) {
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ret = i915_gem_object_wait_rendering(obj);
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if (ret == -ERESTARTSYS)
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return ret;
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}
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/* The display engine is not coherent with the LLC cache on gen6. As
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* a result, we make sure that the pinning that is about to occur is
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* done with uncached PTEs. This is lowest common denominator for all
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* chipsets.
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*
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* However for gen6+, we could do better by using the GFDT bit instead
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* of uncaching, which would allow us to flush all the LLC-cached data
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* with that bit in the PTE to main memory with just one PIPE_CONTROL.
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*/
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// ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
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// if (ret)
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// return ret;
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/* As the user may map the buffer once pinned in the display plane
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* (e.g. libkms for the bootup splash), we have to ensure that we
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* always use map_and_fenceable for all scanout buffers.
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*/
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ret = i915_gem_object_pin(obj, alignment, true);
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if (ret)
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return ret;
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i915_gem_object_flush_cpu_write_domain(obj);
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old_write_domain = obj->base.write_domain;
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old_read_domains = obj->base.read_domains;
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/* It should now be out of any other write domains, and we can update
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* the domain values for our changes.
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*/
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BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
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obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
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// trace_i915_gem_object_change_domain(obj,
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// old_read_domains,
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// old_write_domain);
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return 0;
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}
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@ -1920,13 +1920,61 @@ out_disable:
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}
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}
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int
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intel_pin_and_fence_fb_obj(struct drm_device *dev,
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struct drm_i915_gem_object *obj,
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struct intel_ring_buffer *pipelined)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 alignment;
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int ret;
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switch (obj->tiling_mode) {
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case I915_TILING_NONE:
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if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
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alignment = 128 * 1024;
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else if (INTEL_INFO(dev)->gen >= 4)
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alignment = 4 * 1024;
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else
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alignment = 64 * 1024;
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break;
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case I915_TILING_X:
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/* pin() will align the object as required by fence */
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alignment = 0;
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break;
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case I915_TILING_Y:
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/* FIXME: Is this true? */
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DRM_ERROR("Y tiled not allowed for scan out buffers\n");
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return -EINVAL;
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default:
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BUG();
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}
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dev_priv->mm.interruptible = false;
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ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
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if (ret)
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goto err_interruptible;
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/* Install a fence for tiled scan-out. Pre-i965 always needs a
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* fence, whereas 965+ only requires a fence if using
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* framebuffer compression. For simplicity, we always install
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* a fence as the cost is not that onerous.
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*/
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// if (obj->tiling_mode != I915_TILING_NONE) {
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// ret = i915_gem_object_get_fence(obj, pipelined);
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// if (ret)
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// goto err_unpin;
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// }
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dev_priv->mm.interruptible = true;
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return 0;
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err_unpin:
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// i915_gem_object_unpin(obj);
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err_interruptible:
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dev_priv->mm.interruptible = true;
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return ret;
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}
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static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
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int x, int y)
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@ -6508,13 +6556,49 @@ static const struct drm_mode_config_funcs intel_mode_funcs = {
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static const struct drm_framebuffer_funcs intel_fb_funcs = {
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// .destroy = intel_user_framebuffer_destroy,
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// .create_handle = intel_user_framebuffer_create_handle,
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};
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int intel_framebuffer_init(struct drm_device *dev,
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struct intel_framebuffer *intel_fb,
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struct drm_mode_fb_cmd *mode_cmd,
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struct drm_i915_gem_object *obj)
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{
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int ret;
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if (obj->tiling_mode == I915_TILING_Y)
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return -EINVAL;
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if (mode_cmd->pitch & 63)
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return -EINVAL;
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switch (mode_cmd->bpp) {
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case 8:
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case 16:
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/* Only pre-ILK can handle 5:5:5 */
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if (mode_cmd->depth == 15 && !HAS_PCH_SPLIT(dev))
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return -EINVAL;
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break;
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case 24:
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case 32:
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break;
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default:
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return -EINVAL;
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}
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ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
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if (ret) {
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DRM_ERROR("framebuffer init failed %d\n", ret);
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return ret;
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}
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drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
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intel_fb->obj = obj;
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return 0;
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}
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@ -7528,7 +7612,6 @@ void intel_modeset_init(struct drm_device *dev)
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dev->mode_config.max_width = 8192;
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dev->mode_config.max_height = 8192;
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}
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dev->mode_config.fb_base = get_bus_addr();
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DRM_DEBUG_KMS("%d display pipe%s available.\n",
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@ -45,10 +45,167 @@
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#include "i915_drv.h"
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struct fb_info *framebuffer_alloc(size_t size, struct device *dev)
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{
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#define BYTES_PER_LONG (BITS_PER_LONG/8)
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#define PADDING (BYTES_PER_LONG - (sizeof(struct fb_info) % BYTES_PER_LONG))
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int fb_info_size = sizeof(struct fb_info);
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struct fb_info *info;
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char *p;
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if (size)
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fb_info_size += PADDING;
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p = kzalloc(fb_info_size + size, GFP_KERNEL);
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if (!p)
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return NULL;
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info = (struct fb_info *) p;
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if (size)
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info->par = p + fb_info_size;
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return info;
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#undef PADDING
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#undef BYTES_PER_LONG
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}
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static struct fb_ops intelfb_ops = {
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// .owner = THIS_MODULE,
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.fb_check_var = drm_fb_helper_check_var,
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.fb_set_par = drm_fb_helper_set_par,
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// .fb_fillrect = cfb_fillrect,
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// .fb_copyarea = cfb_copyarea,
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// .fb_imageblit = cfb_imageblit,
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// .fb_pan_display = drm_fb_helper_pan_display,
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.fb_blank = drm_fb_helper_blank,
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// .fb_setcmap = drm_fb_helper_setcmap,
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// .fb_debug_enter = drm_fb_helper_debug_enter,
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// .fb_debug_leave = drm_fb_helper_debug_leave,
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};
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static int intelfb_create(struct intel_fbdev *ifbdev,
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struct drm_fb_helper_surface_size *sizes)
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{
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struct drm_device *dev = ifbdev->helper.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct fb_info *info;
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struct drm_framebuffer *fb;
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struct drm_mode_fb_cmd mode_cmd;
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struct drm_i915_gem_object *obj;
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struct device *device = &dev->pdev->dev;
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int size, ret;
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/* we don't do packed 24bpp */
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if (sizes->surface_bpp == 24)
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sizes->surface_bpp = 32;
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mode_cmd.width = sizes->surface_width;
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mode_cmd.height = sizes->surface_height;
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mode_cmd.bpp = sizes->surface_bpp;
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mode_cmd.pitch = ALIGN(mode_cmd.width * ((mode_cmd.bpp + 7) / 8), 64);
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mode_cmd.depth = sizes->surface_depth;
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size = mode_cmd.pitch * mode_cmd.height;
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size = ALIGN(size, PAGE_SIZE);
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obj = i915_gem_alloc_object(dev, size);
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if (!obj) {
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DRM_ERROR("failed to allocate framebuffer\n");
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ret = -ENOMEM;
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goto out;
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}
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mutex_lock(&dev->struct_mutex);
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/* Flush everything out, we'll be doing GTT only from now on */
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ret = intel_pin_and_fence_fb_obj(dev, obj, false);
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if (ret) {
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DRM_ERROR("failed to pin fb: %d\n", ret);
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goto out_unref;
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}
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info = framebuffer_alloc(0, device);
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if (!info) {
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ret = -ENOMEM;
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goto out_unpin;
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}
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info->par = ifbdev;
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ret = intel_framebuffer_init(dev, &ifbdev->ifb, &mode_cmd, obj);
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if (ret)
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goto out_unpin;
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fb = &ifbdev->ifb.base;
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ifbdev->helper.fb = fb;
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ifbdev->helper.fbdev = info;
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strcpy(info->fix.id, "inteldrmfb");
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info->flags = FBINFO_DEFAULT | FBINFO_CAN_FORCE_OUTPUT;
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info->fbops = &intelfb_ops;
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/* setup aperture base/size for vesafb takeover */
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info->apertures = alloc_apertures(1);
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if (!info->apertures) {
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ret = -ENOMEM;
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goto out_unpin;
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}
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info->apertures->ranges[0].base = dev->mode_config.fb_base;
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info->apertures->ranges[0].size =
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dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
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info->fix.smem_start = dev->mode_config.fb_base + obj->gtt_offset;
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info->fix.smem_len = size;
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info->screen_size = size;
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// memset(info->screen_base, 0, size);
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drm_fb_helper_fill_fix(info, fb->pitch, fb->depth);
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drm_fb_helper_fill_var(info, &ifbdev->helper, sizes->fb_width, sizes->fb_height);
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DRM_DEBUG_KMS("allocated %dx%d fb: 0x%08x, bo %p\n",
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fb->width, fb->height,
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obj->gtt_offset, obj);
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mutex_unlock(&dev->struct_mutex);
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// vga_switcheroo_client_fb_set(dev->pdev, info);
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return 0;
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out_unpin:
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// i915_gem_object_unpin(obj);
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out_unref:
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// drm_gem_object_unreference(&obj->base);
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mutex_unlock(&dev->struct_mutex);
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out:
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return ret;
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}
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static int intel_fb_find_or_create_single(struct drm_fb_helper *helper,
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struct drm_fb_helper_surface_size *sizes)
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{
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struct intel_fbdev *ifbdev = (struct intel_fbdev *)helper;
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int new_fb = 0;
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int ret;
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if (!helper->fb) {
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ret = intelfb_create(ifbdev, sizes);
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if (ret)
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return ret;
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new_fb = 1;
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}
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return new_fb;
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}
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static struct drm_fb_helper_funcs intel_fb_helper_funcs = {
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.gamma_set = intel_crtc_fb_gamma_set,
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.gamma_get = intel_crtc_fb_gamma_get,
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// .fb_probe = intel_fb_find_or_create_single,
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.fb_probe = intel_fb_find_or_create_single,
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};
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@ -1242,7 +1242,7 @@ static int blt_ring_init(struct intel_ring_buffer *ring)
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ptr = ioremap(obj->pages[0], 4096);
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*ptr++ = MI_BATCH_BUFFER_END;
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*ptr++ = MI_NOOP;
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iounmap(obj->pages[0]);
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// iounmap(obj->pages[0]);
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ret = i915_gem_object_set_to_gtt_domain(obj, false);
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if (ret) {
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