update ddk includes
git-svn-id: svn://kolibrios.org@2967 a494cfbc-eb01-0410-851d-a64ba20cac60
This commit is contained in:
Sergey Semyonov (Serge)
parent
96aa59bb73
commit
5b7d788e49
@ -10,7 +10,7 @@
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#define OS_BASE 0x80000000
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#define PG_SW 0x003
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#define PG_NOCACHE 0x018
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#define PG_NOCACHE 0x010
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#define MANUAL_DESTROY 0x80000000
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@ -702,6 +702,9 @@ struct drm_get_cap {
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#define DRM_IOCTL_MODE_CREATE_DUMB DRM_IOWR(0xB2, struct drm_mode_create_dumb)
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#define DRM_IOCTL_MODE_MAP_DUMB DRM_IOWR(0xB3, struct drm_mode_map_dumb)
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#define DRM_IOCTL_MODE_DESTROY_DUMB DRM_IOWR(0xB4, struct drm_mode_destroy_dumb)
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#define DRM_IOCTL_MODE_GETPLANERESOURCES DRM_IOWR(0xB5, struct drm_mode_get_plane_res)
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#define DRM_IOCTL_MODE_GETPLANE DRM_IOWR(0xB6, struct drm_mode_get_plane)
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#define DRM_IOCTL_MODE_SETPLANE DRM_IOWR(0xB7, struct drm_mode_set_plane)
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*/
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@ -36,17 +36,15 @@
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#define _DRM_P_H_
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#ifdef __KERNEL__
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#ifdef __alpha__
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/* add include of current.h so that "current" is defined
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* before static inline funcs in wait.h. Doing this so we
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* can build the DRM (part of PI DRI). 4/21/2000 S + B */
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#include <asm/current.h>
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#endif /* __alpha__ */
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#include <syscall.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <errno-base.h>
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#include <linux/errno.h>
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#include <linux/kref.h>
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#include <linux/spinlock.h>
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#include <linux/wait.h>
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//#include <linux/miscdevice.h>
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//#include <linux/fs.h>
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@ -54,7 +52,7 @@
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//#include <linux/init.h>
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//#include <linux/file.h>
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#include <linux/pci.h>
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//#include <linux/jiffies.h>
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#include <linux/jiffies.h>
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//#include <linux/smp_lock.h> /* For (un)lock_kernel */
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//#include <linux/dma-mapping.h>
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//#include <linux/mm.h>
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@ -122,16 +120,15 @@ extern void drm_ut_debug_printk(unsigned int request_level,
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printk("[" DRM_NAME ":%s] " fmt , __func__ , ##args); \
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} while(0)
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#define dev_err(dev, format, arg...) \
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printk("Error %s " format, __func__ , ## arg)
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#define dev_warn(dev, format, arg...) \
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printk("Warning %s " format, __func__ , ## arg)
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#define dev_info(dev, format, arg...) \
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printk("Info %s " format , __func__, ## arg)
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#define DRM_DEBUG_DRIVER(fmt, args...) \
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do { \
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printk("[" DRM_NAME ":%s] " fmt , __func__ , ##args); \
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} while (0)
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#define DRM_LOG_KMS(fmt, args...) \
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do { \
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printk("[" DRM_NAME "]" fmt, ##args); \
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} while (0)
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static inline int drm_sysfs_connector_add(struct drm_connector *connector)
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{ return 0; };
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@ -160,7 +157,10 @@ static inline void drm_sysfs_connector_remove(struct drm_connector *connector)
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#define DRIVER_IRQ_VBL2 0x800
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#define DRIVER_GEM 0x1000
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#define DRIVER_MODESET 0x2000
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#define DRIVER_USE_PLATFORM_DEVICE 0x4000
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#define DRIVER_BUS_PCI 0x1
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#define DRIVER_BUS_PLATFORM 0x2
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#define DRIVER_BUS_USB 0x3
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/***********************************************************************/
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/** \name Begin the DRM... */
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@ -396,6 +396,7 @@ struct drm_freelist {
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atomic_t wfh; /**< If waiting for high mark */
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spinlock_t lock;
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};
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#endif
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typedef struct drm_dma_handle {
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dma_addr_t busaddr;
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@ -403,6 +404,7 @@ typedef struct drm_dma_handle {
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size_t size;
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} drm_dma_handle_t;
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#if 0
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/**
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* Buffer entry. There is one of this for each buffer size order.
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*/
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@ -554,6 +556,8 @@ struct drm_sigdata {
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struct drm_hw_lock *lock;
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};
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#endif
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/**
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* Kernel side of a mapping
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@ -570,6 +574,7 @@ struct drm_local_map {
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typedef struct drm_local_map drm_local_map_t;
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#if 0
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/**
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* Mappings list
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*/
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@ -638,7 +643,6 @@ struct drm_gem_object {
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struct file *filp;
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/* Mapping info for this object */
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// struct drm_map_list map_list;
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/**
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* Size of the object, in bytes. Immutable over the object's
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@ -673,8 +677,6 @@ struct drm_gem_object {
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void *driver_private;
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};
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#if 0
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#include "drm_crtc.h"
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/* per-master structure */
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@ -693,15 +695,17 @@ struct drm_master {
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/** \name Authentication */
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/*@{ */
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struct drm_open_hash magiclist;
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struct list_head magicfree;
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// struct drm_open_hash magiclist;
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// struct list_head magicfree;
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/*@} */
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struct drm_lock_data lock; /**< Information on hardware lock */
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// struct drm_lock_data lock; /**< Information on hardware lock */
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void *driver_priv; /**< Private structure for driver to use */
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};
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#if 0
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/* Size of ringbuffer for vblank timestamps. Just double-buffer
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* in initial implementation.
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*/
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@ -841,7 +845,7 @@ struct drm_driver {
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* Specifically, the timestamp in @vblank_time should correspond as
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* closely as possible to the time when the first video scanline of
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* the video frame after the end of VBLANK will start scanning out,
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* the time immmediately after end of the VBLANK interval. If the
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* the time immediately after end of the VBLANK interval. If the
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* @crtc is currently inside VBLANK, this will be a time in the future.
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* If the @crtc is currently scanning out a frame, this will be the
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* past start time of the current scanout. This is meant to adhere
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@ -908,10 +912,23 @@ struct drm_driver {
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*/
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int (*gem_init_object) (struct drm_gem_object *obj);
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void (*gem_free_object) (struct drm_gem_object *obj);
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int (*gem_open_object) (struct drm_gem_object *, struct drm_file *);
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void (*gem_close_object) (struct drm_gem_object *, struct drm_file *);
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/* vga arb irq handler */
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void (*vgaarb_irq)(struct drm_device *dev, bool state);
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/* dumb alloc support */
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int (*dumb_create)(struct drm_file *file_priv,
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struct drm_device *dev,
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struct drm_mode_create_dumb *args);
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int (*dumb_map_offset)(struct drm_file *file_priv,
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struct drm_device *dev, uint32_t handle,
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uint64_t *offset);
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int (*dumb_destroy)(struct drm_file *file_priv,
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struct drm_device *dev,
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uint32_t handle);
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/* Driver private ops for this object */
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struct vm_operations_struct *gem_vm_ops;
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@ -926,12 +943,20 @@ struct drm_driver {
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int dev_priv_size;
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struct drm_ioctl_desc *ioctls;
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int num_ioctls;
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struct file_operations fops;
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struct pci_driver pci_driver;
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const struct file_operations *fops;
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union {
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struct pci_driver *pci;
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struct platform_device *platform_device;
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struct usb_driver *usb;
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} kdriver;
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struct drm_bus *bus;
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/* List of devices hanging off this driver */
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struct list_head device_list;
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};
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#endif
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#define DRM_MINOR_UNASSIGNED 0
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#define DRM_MINOR_LEGACY 1
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#define DRM_MINOR_CONTROL 2
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@ -944,7 +969,7 @@ struct drm_driver {
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*/
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struct drm_debugfs_list {
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const char *name; /** file name */
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int (*show)(struct seq_file*, void*); /** show callback */
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// int (*show)(struct seq_file*, void*); /** show callback */
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u32 driver_features; /**< Required driver features for this entry */
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};
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@ -964,7 +989,7 @@ struct drm_debugfs_node {
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*/
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struct drm_info_list {
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const char *name; /** file name */
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int (*show)(struct seq_file*, void*); /** show callback */
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// int (*show)(struct seq_file*, void*); /** show callback */
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u32 driver_features; /**< Required driver features for this entry */
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void *data;
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};
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@ -985,22 +1010,20 @@ struct drm_info_node {
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struct drm_minor {
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int index; /**< Minor device number */
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int type; /**< Control or render */
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dev_t device; /**< Device number for mknod */
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struct device kdev; /**< Linux device */
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// dev_t device; /**< Device number for mknod */
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// struct device kdev; /**< Linux device */
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struct drm_device *dev;
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struct proc_dir_entry *proc_root; /**< proc directory entry */
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struct drm_info_node proc_nodes;
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struct dentry *debugfs_root;
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struct drm_info_node debugfs_nodes;
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// struct proc_dir_entry *proc_root; /**< proc directory entry */
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// struct drm_info_node proc_nodes;
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// struct dentry *debugfs_root;
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// struct drm_info_node debugfs_nodes;
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struct drm_master *master; /* currently active master for this node */
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struct list_head master_list;
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struct drm_mode_group mode_group;
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struct drm_master *master; /* currently active master for this node */
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// struct list_head master_list;
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// struct drm_mode_group mode_group;
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};
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#endif
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/* mode specified on the command line */
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struct drm_cmdline_mode {
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bool specified;
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@ -1149,7 +1172,7 @@ struct drm_device {
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// struct drm_local_map *agp_buffer_map;
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// unsigned int agp_buffer_token;
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// struct drm_minor *control; /**< Control node for card */
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// struct drm_minor *primary; /**< render type primary screen head */
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struct drm_minor *primary; /**< render type primary screen head */
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struct drm_mode_config mode_config; /**< Current mode config */
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@ -1166,37 +1189,12 @@ struct drm_device {
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#define DRM_SWITCH_POWER_CHANGING 2
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static __inline__ int drm_device_is_agp(struct drm_device *dev)
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{
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return pci_find_capability(dev->pdev, PCI_CAP_ID_AGP);
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}
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static __inline__ int drm_device_is_pcie(struct drm_device *dev)
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{
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return pci_find_capability(dev->pdev, PCI_CAP_ID_EXP);
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}
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#if 0
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static inline int drm_dev_to_irq(struct drm_device *dev)
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{
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return dev->pdev->irq;
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}
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static __inline__ int drm_core_check_feature(struct drm_device *dev,
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int feature)
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{
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return ((dev->driver->driver_features & feature) ? 1 : 0);
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}
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#if 0
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#ifdef __alpha__
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#define drm_get_pci_domain(dev) dev->hose->index
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@ -1344,6 +1342,7 @@ extern int drm_getmagic(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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extern int drm_authmagic(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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extern int drm_remove_magic(struct drm_master *master, drm_magic_t magic);
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/* Cache management (drm_cache.c) */
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void drm_clflush_pages(struct page *pages[], unsigned long num_pages);
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@ -1555,6 +1554,8 @@ static inline int drm_sysfs_connector_add(struct drm_connector *connector)
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static inline void drm_sysfs_connector_remove(struct drm_connector *connector)
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{ };
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#endif
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/* Graphics Execution Manager library functions (drm_gem.c) */
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int drm_gem_init(struct drm_device *dev);
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void drm_gem_destroy(struct drm_device *dev);
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@ -1564,11 +1565,14 @@ struct drm_gem_object *drm_gem_object_alloc(struct drm_device *dev,
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size_t size);
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int drm_gem_object_init(struct drm_device *dev,
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struct drm_gem_object *obj, size_t size);
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int drm_gem_private_object_init(struct drm_device *dev,
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struct drm_gem_object *obj, size_t size);
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void drm_gem_object_handle_free(struct drm_gem_object *obj);
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void drm_gem_vm_open(struct vm_area_struct *vma);
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void drm_gem_vm_close(struct vm_area_struct *vma);
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int drm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
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static inline void
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drm_gem_object_reference(struct drm_gem_object *obj)
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{
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@ -1578,10 +1582,20 @@ drm_gem_object_reference(struct drm_gem_object *obj)
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static inline void
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drm_gem_object_unreference(struct drm_gem_object *obj)
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{
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if (obj == NULL)
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return;
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if (obj != NULL)
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kref_put(&obj->refcount, drm_gem_object_free);
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}
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#if 0
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static inline void
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drm_gem_object_unreference_unlocked(struct drm_gem_object *obj)
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{
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if (obj != NULL) {
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struct drm_device *dev = obj->dev;
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mutex_lock(&dev->struct_mutex);
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kref_put(&obj->refcount, drm_gem_object_free);
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mutex_unlock(&dev->struct_mutex);
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}
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}
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int drm_gem_handle_create(struct drm_file *file_priv,
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@ -1609,10 +1623,32 @@ drm_gem_object_handle_unreference(struct drm_gem_object *obj)
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* ref, in which case the object would disappear before we
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* checked for a name
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*/
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kref_put(&obj->handlecount, drm_gem_object_handle_free);
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if (atomic_dec_and_test(&obj->handle_count))
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drm_gem_object_handle_free(obj);
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drm_gem_object_unreference(obj);
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}
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static inline void
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drm_gem_object_handle_unreference_unlocked(struct drm_gem_object *obj)
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{
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if (obj == NULL)
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return;
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if (atomic_read(&obj->handle_count) == 0)
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return;
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/*
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* Must bump handle count first as this may be the last
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* ref, in which case the object would disappear before we
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* checked for a name
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*/
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if (atomic_dec_and_test(&obj->handle_count))
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drm_gem_object_handle_free(obj);
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drm_gem_object_unreference_unlocked(obj);
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}
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struct drm_gem_object *drm_gem_object_lookup(struct drm_device *dev,
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struct drm_file *filp,
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u32 handle);
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@ -1663,11 +1699,18 @@ static __inline void drm_free_large(void *ptr)
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vfree(ptr);
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}
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/*@}*/
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#endif
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static __inline__ int drm_device_is_agp(struct drm_device *dev)
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{
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return pci_find_capability(dev->pdev, PCI_CAP_ID_AGP);
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}
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static __inline__ int drm_device_is_pcie(struct drm_device *dev)
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{
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return pci_find_capability(dev->pdev, PCI_CAP_ID_EXP);
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}
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#endif /* __KERNEL__ */
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#endif
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1694
drivers/include/drm/drmP.hh
Normal file
1694
drivers/include/drm/drmP.hh
Normal file
File diff suppressed because it is too large
Load Diff
@ -29,9 +29,10 @@
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include <linux/idr.h>
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#include <linux/fb.h>
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#include <drm/drm_fourcc.h>
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struct drm_device;
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struct drm_mode_set;
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struct drm_framebuffer;
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@ -44,6 +45,7 @@ struct drm_framebuffer;
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#define DRM_MODE_OBJECT_PROPERTY 0xb0b0b0b0
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#define DRM_MODE_OBJECT_FB 0xfbfbfbfb
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#define DRM_MODE_OBJECT_BLOB 0xbbbbbbbb
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#define DRM_MODE_OBJECT_PLANE 0xeeeeeeee
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struct drm_mode_object {
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uint32_t id;
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@ -118,7 +120,6 @@ struct drm_display_mode {
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char name[DRM_DISPLAY_MODE_LEN];
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int connector_count;
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enum drm_mode_status status;
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int type;
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@ -238,13 +239,15 @@ struct drm_framebuffer {
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struct list_head head;
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struct drm_mode_object base;
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const struct drm_framebuffer_funcs *funcs;
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unsigned int pitch;
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unsigned int pitches[4];
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unsigned int offsets[4];
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unsigned int width;
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unsigned int height;
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/* depth can be 15 or 16 */
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unsigned int depth;
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int bits_per_pixel;
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int flags;
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uint32_t pixel_format; /* fourcc format */
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struct list_head filp_head;
|
||||
/* if you are using the helper */
|
||||
void *helper_private;
|
||||
@ -278,6 +281,7 @@ struct drm_crtc;
|
||||
struct drm_connector;
|
||||
struct drm_encoder;
|
||||
struct drm_pending_vblank_event;
|
||||
struct drm_plane;
|
||||
|
||||
/**
|
||||
* drm_crtc_funcs - control CRTCs for a given device
|
||||
@ -341,10 +345,21 @@ struct drm_crtc_funcs {
|
||||
|
||||
/**
|
||||
* drm_crtc - central CRTC control structure
|
||||
* @dev: parent DRM device
|
||||
* @head: list management
|
||||
* @base: base KMS object for ID tracking etc.
|
||||
* @enabled: is this CRTC enabled?
|
||||
* @mode: current mode timings
|
||||
* @hwmode: mode timings as programmed to hw regs
|
||||
* @x: x position on screen
|
||||
* @y: y position on screen
|
||||
* @funcs: CRTC control functions
|
||||
* @gamma_size: size of gamma ramp
|
||||
* @gamma_store: gamma ramp values
|
||||
* @framedur_ns: precise frame timing
|
||||
* @framedur_ns: precise line timing
|
||||
* @pixeldur_ns: precise pixel timing
|
||||
* @helper_private: mid-layer private data
|
||||
*
|
||||
* Each CRTC may have one or more connectors associated with it. This structure
|
||||
* allows the CRTC to be controlled.
|
||||
@ -423,6 +438,13 @@ struct drm_connector_funcs {
|
||||
void (*force)(struct drm_connector *connector);
|
||||
};
|
||||
|
||||
/**
|
||||
* drm_encoder_funcs - encoder controls
|
||||
* @reset: reset state (e.g. at init or resume time)
|
||||
* @destroy: cleanup and free associated data
|
||||
*
|
||||
* Encoders sit between CRTCs and connectors.
|
||||
*/
|
||||
struct drm_encoder_funcs {
|
||||
void (*reset)(struct drm_encoder *encoder);
|
||||
void (*destroy)(struct drm_encoder *encoder);
|
||||
@ -431,10 +453,22 @@ struct drm_encoder_funcs {
|
||||
#define DRM_CONNECTOR_MAX_UMODES 16
|
||||
#define DRM_CONNECTOR_MAX_PROPERTY 16
|
||||
#define DRM_CONNECTOR_LEN 32
|
||||
#define DRM_CONNECTOR_MAX_ENCODER 2
|
||||
#define DRM_CONNECTOR_MAX_ENCODER 3
|
||||
|
||||
/**
|
||||
* drm_encoder - central DRM encoder structure
|
||||
* @dev: parent DRM device
|
||||
* @head: list management
|
||||
* @base: base KMS object
|
||||
* @encoder_type: one of the %DRM_MODE_ENCODER_<foo> types in drm_mode.h
|
||||
* @possible_crtcs: bitmask of potential CRTC bindings
|
||||
* @possible_clones: bitmask of potential sibling encoders for cloning
|
||||
* @crtc: currently bound CRTC
|
||||
* @funcs: control functions
|
||||
* @helper_private: mid-layer private data
|
||||
*
|
||||
* CRTCs drive pixels to encoders, which convert them into signals
|
||||
* appropriate for a given connector or set of connectors.
|
||||
*/
|
||||
struct drm_encoder {
|
||||
struct drm_device *dev;
|
||||
@ -466,16 +500,41 @@ enum drm_connector_force {
|
||||
/* DACs should rarely do this without a lot of testing */
|
||||
#define DRM_CONNECTOR_POLL_DISCONNECT (1 << 2)
|
||||
|
||||
#define MAX_ELD_BYTES 128
|
||||
|
||||
/**
|
||||
* drm_connector - central DRM connector control structure
|
||||
* @crtc: CRTC this connector is currently connected to, NULL if none
|
||||
* @dev: parent DRM device
|
||||
* @kdev: kernel device for sysfs attributes
|
||||
* @attr: sysfs attributes
|
||||
* @head: list management
|
||||
* @base: base KMS object
|
||||
* @connector_type: one of the %DRM_MODE_CONNECTOR_<foo> types from drm_mode.h
|
||||
* @connector_type_id: index into connector type enum
|
||||
* @interlace_allowed: can this connector handle interlaced modes?
|
||||
* @doublescan_allowed: can this connector handle doublescan?
|
||||
* @available_modes: modes available on this connector (from get_modes() + user)
|
||||
* @initial_x: initial x position for this connector
|
||||
* @initial_y: initial y position for this connector
|
||||
* @status: connector connected?
|
||||
* @modes: modes available on this connector (from fill_modes() + user)
|
||||
* @status: one of the drm_connector_status enums (connected, not, or unknown)
|
||||
* @probed_modes: list of modes derived directly from the display
|
||||
* @display_info: information about attached display (e.g. from EDID)
|
||||
* @funcs: connector control functions
|
||||
* @user_modes: user added mode list
|
||||
* @edid_blob_ptr: DRM property containing EDID if present
|
||||
* @property_ids: property tracking for this connector
|
||||
* @property_values: value pointers or data for properties
|
||||
* @polled: a %DRM_CONNECTOR_POLL_<foo> value for core driven polling
|
||||
* @dpms: current dpms state
|
||||
* @helper_private: mid-layer private data
|
||||
* @force: a %DRM_FORCE_<foo> state for forced mode sets
|
||||
* @encoder_ids: valid encoders for this connector
|
||||
* @encoder: encoder driving this connector, if any
|
||||
* @eld: EDID-like data, if present
|
||||
* @dvi_dual: dual link DVI, if found
|
||||
* @max_tmds_clock: max clock rate, if found
|
||||
* @latency_present: AV delay info from ELD, if found
|
||||
* @video_latency: video latency info from ELD, if found
|
||||
* @audio_latency: audio latency info from ELD, if found
|
||||
* @null_edid_counter: track sinks that give us all zeros for the EDID
|
||||
*
|
||||
* Each connector may be connected to one or more CRTCs, or may be clonable by
|
||||
* another connector if they can share a CRTC. Each connector also has a specific
|
||||
@ -496,7 +555,6 @@ struct drm_connector {
|
||||
bool doublescan_allowed;
|
||||
struct list_head modes; /* list of modes on this connector */
|
||||
|
||||
int initial_x, initial_y;
|
||||
enum drm_connector_status status;
|
||||
|
||||
/* these are modes added by probing with DDC or the BIOS */
|
||||
@ -520,14 +578,84 @@ struct drm_connector {
|
||||
/* forced on connector */
|
||||
enum drm_connector_force force;
|
||||
uint32_t encoder_ids[DRM_CONNECTOR_MAX_ENCODER];
|
||||
uint32_t force_encoder_id;
|
||||
struct drm_encoder *encoder; /* currently active encoder */
|
||||
|
||||
/* EDID bits */
|
||||
uint8_t eld[MAX_ELD_BYTES];
|
||||
bool dvi_dual;
|
||||
int max_tmds_clock; /* in MHz */
|
||||
bool latency_present[2];
|
||||
int video_latency[2]; /* [0]: progressive, [1]: interlaced */
|
||||
int audio_latency[2];
|
||||
int null_edid_counter; /* needed to workaround some HW bugs where we get all 0s */
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_mode_set
|
||||
* drm_plane_funcs - driver plane control functions
|
||||
* @update_plane: update the plane configuration
|
||||
* @disable_plane: shut down the plane
|
||||
* @destroy: clean up plane resources
|
||||
*/
|
||||
struct drm_plane_funcs {
|
||||
int (*update_plane)(struct drm_plane *plane,
|
||||
struct drm_crtc *crtc, struct drm_framebuffer *fb,
|
||||
int crtc_x, int crtc_y,
|
||||
unsigned int crtc_w, unsigned int crtc_h,
|
||||
uint32_t src_x, uint32_t src_y,
|
||||
uint32_t src_w, uint32_t src_h);
|
||||
int (*disable_plane)(struct drm_plane *plane);
|
||||
void (*destroy)(struct drm_plane *plane);
|
||||
};
|
||||
|
||||
/**
|
||||
* drm_plane - central DRM plane control structure
|
||||
* @dev: DRM device this plane belongs to
|
||||
* @head: for list management
|
||||
* @base: base mode object
|
||||
* @possible_crtcs: pipes this plane can be bound to
|
||||
* @format_types: array of formats supported by this plane
|
||||
* @format_count: number of formats supported
|
||||
* @crtc: currently bound CRTC
|
||||
* @fb: currently bound fb
|
||||
* @gamma_size: size of gamma table
|
||||
* @gamma_store: gamma correction table
|
||||
* @enabled: enabled flag
|
||||
* @funcs: helper functions
|
||||
* @helper_private: storage for drver layer
|
||||
*/
|
||||
struct drm_plane {
|
||||
struct drm_device *dev;
|
||||
struct list_head head;
|
||||
|
||||
struct drm_mode_object base;
|
||||
|
||||
uint32_t possible_crtcs;
|
||||
uint32_t *format_types;
|
||||
uint32_t format_count;
|
||||
|
||||
struct drm_crtc *crtc;
|
||||
struct drm_framebuffer *fb;
|
||||
|
||||
/* CRTC gamma size for reporting to userspace */
|
||||
uint32_t gamma_size;
|
||||
uint16_t *gamma_store;
|
||||
|
||||
bool enabled;
|
||||
|
||||
const struct drm_plane_funcs *funcs;
|
||||
void *helper_private;
|
||||
};
|
||||
|
||||
/**
|
||||
* drm_mode_set - new values for a CRTC config change
|
||||
* @head: list management
|
||||
* @fb: framebuffer to use for new config
|
||||
* @crtc: CRTC whose configuration we're about to change
|
||||
* @mode: mode timings to use
|
||||
* @x: position of this CRTC relative to @fb
|
||||
* @y: position of this CRTC relative to @fb
|
||||
* @connectors: array of connectors to drive with this CRTC if possible
|
||||
* @num_connectors: size of @connectors array
|
||||
*
|
||||
* Represents a single crtc the connectors that it drives with what mode
|
||||
* and from which framebuffer it scans out from.
|
||||
@ -549,13 +677,33 @@ struct drm_mode_set {
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_mode_config_funcs - configure CRTCs for a given screen layout
|
||||
* struct drm_mode_config_funcs - basic driver provided mode setting functions
|
||||
* @fb_create: create a new framebuffer object
|
||||
* @output_poll_changed: function to handle output configuration changes
|
||||
*
|
||||
* Some global (i.e. not per-CRTC, connector, etc) mode setting functions that
|
||||
* involve drivers.
|
||||
*/
|
||||
struct drm_mode_config_funcs {
|
||||
struct drm_framebuffer *(*fb_create)(struct drm_device *dev, struct drm_file *file_priv, struct drm_mode_fb_cmd *mode_cmd);
|
||||
struct drm_framebuffer *(*fb_create)(struct drm_device *dev,
|
||||
struct drm_file *file_priv,
|
||||
struct drm_mode_fb_cmd2 *mode_cmd);
|
||||
void (*output_poll_changed)(struct drm_device *dev);
|
||||
};
|
||||
|
||||
/**
|
||||
* drm_mode_group - group of mode setting resources for potential sub-grouping
|
||||
* @num_crtcs: CRTC count
|
||||
* @num_encoders: encoder count
|
||||
* @num_connectors: connector count
|
||||
* @id_list: list of KMS object IDs in this group
|
||||
*
|
||||
* Currently this simply tracks the global mode setting state. But in the
|
||||
* future it could allow groups of objects to be set aside into independent
|
||||
* control groups for use by different user level processes (e.g. two X servers
|
||||
* running simultaneously on different heads, each with their own mode
|
||||
* configuration and freedom of mode setting).
|
||||
*/
|
||||
struct drm_mode_group {
|
||||
uint32_t num_crtcs;
|
||||
uint32_t num_encoders;
|
||||
@ -567,7 +715,30 @@ struct drm_mode_group {
|
||||
|
||||
/**
|
||||
* drm_mode_config - Mode configuration control structure
|
||||
* @mutex: mutex protecting KMS related lists and structures
|
||||
* @idr_mutex: mutex for KMS ID allocation and management
|
||||
* @crtc_idr: main KMS ID tracking object
|
||||
* @num_fb: number of fbs available
|
||||
* @fb_list: list of framebuffers available
|
||||
* @num_connector: number of connectors on this device
|
||||
* @connector_list: list of connector objects
|
||||
* @num_encoder: number of encoders on this device
|
||||
* @encoder_list: list of encoder objects
|
||||
* @num_crtc: number of CRTCs on this device
|
||||
* @crtc_list: list of CRTC objects
|
||||
* @min_width: minimum pixel width on this device
|
||||
* @min_height: minimum pixel height on this device
|
||||
* @max_width: maximum pixel width on this device
|
||||
* @max_height: maximum pixel height on this device
|
||||
* @funcs: core driver provided mode setting functions
|
||||
* @fb_base: base address of the framebuffer
|
||||
* @poll_enabled: track polling status for this device
|
||||
* @output_poll_work: delayed work for polling in process context
|
||||
* @*_property: core property tracking
|
||||
*
|
||||
* Core mode resource tracking structure. All CRTC, encoders, and connectors
|
||||
* enumerated by the driver are added here, as are global properties. Some
|
||||
* global restrictions are also here, e.g. dimension restrictions.
|
||||
*/
|
||||
struct drm_mode_config {
|
||||
struct mutex mutex; /* protects configuration (mode lists etc.) */
|
||||
@ -580,6 +751,8 @@ struct drm_mode_config {
|
||||
struct list_head connector_list;
|
||||
int num_encoder;
|
||||
struct list_head encoder_list;
|
||||
int num_plane;
|
||||
struct list_head plane_list;
|
||||
|
||||
int num_crtc;
|
||||
struct list_head crtc_list;
|
||||
@ -632,6 +805,7 @@ struct drm_mode_config {
|
||||
#define obj_to_fb(x) container_of(x, struct drm_framebuffer, base)
|
||||
#define obj_to_property(x) container_of(x, struct drm_property, base)
|
||||
#define obj_to_blob(x) container_of(x, struct drm_property_blob, base)
|
||||
#define obj_to_plane(x) container_of(x, struct drm_plane, base)
|
||||
|
||||
|
||||
extern void drm_crtc_init(struct drm_device *dev,
|
||||
@ -651,6 +825,14 @@ extern void drm_encoder_init(struct drm_device *dev,
|
||||
const struct drm_encoder_funcs *funcs,
|
||||
int encoder_type);
|
||||
|
||||
extern int drm_plane_init(struct drm_device *dev,
|
||||
struct drm_plane *plane,
|
||||
unsigned long possible_crtcs,
|
||||
const struct drm_plane_funcs *funcs,
|
||||
const uint32_t *formats, uint32_t format_count,
|
||||
bool priv);
|
||||
extern void drm_plane_cleanup(struct drm_plane *plane);
|
||||
|
||||
extern void drm_encoder_cleanup(struct drm_encoder *encoder);
|
||||
|
||||
extern char *drm_get_connector_name(struct drm_connector *connector);
|
||||
@ -744,17 +926,25 @@ extern struct drm_mode_object *drm_mode_object_find(struct drm_device *dev,
|
||||
/* IOCTLs */
|
||||
extern int drm_mode_getresources(struct drm_device *dev,
|
||||
void *data, struct drm_file *file_priv);
|
||||
|
||||
extern int drm_mode_getplane_res(struct drm_device *dev, void *data,
|
||||
struct drm_file *file_priv);
|
||||
extern int drm_mode_getcrtc(struct drm_device *dev,
|
||||
void *data, struct drm_file *file_priv);
|
||||
extern int drm_mode_getconnector(struct drm_device *dev,
|
||||
void *data, struct drm_file *file_priv);
|
||||
extern int drm_mode_setcrtc(struct drm_device *dev,
|
||||
void *data, struct drm_file *file_priv);
|
||||
extern int drm_mode_getplane(struct drm_device *dev,
|
||||
void *data, struct drm_file *file_priv);
|
||||
extern int drm_mode_setplane(struct drm_device *dev,
|
||||
void *data, struct drm_file *file_priv);
|
||||
extern int drm_mode_cursor_ioctl(struct drm_device *dev,
|
||||
void *data, struct drm_file *file_priv);
|
||||
extern int drm_mode_addfb(struct drm_device *dev,
|
||||
void *data, struct drm_file *file_priv);
|
||||
extern int drm_mode_addfb2(struct drm_device *dev,
|
||||
void *data, struct drm_file *file_priv);
|
||||
extern uint32_t drm_mode_legacy_fb_format(uint32_t bpp, uint32_t depth);
|
||||
extern int drm_mode_rmfb(struct drm_device *dev,
|
||||
void *data, struct drm_file *file_priv);
|
||||
extern int drm_mode_getfb(struct drm_device *dev,
|
||||
|
||||
@ -117,7 +117,7 @@ extern bool drm_helper_encoder_in_use(struct drm_encoder *encoder);
|
||||
extern void drm_helper_connector_dpms(struct drm_connector *connector, int mode);
|
||||
|
||||
extern int drm_helper_mode_fill_fb_struct(struct drm_framebuffer *fb,
|
||||
struct drm_mode_fb_cmd *mode_cmd);
|
||||
struct drm_mode_fb_cmd2 *mode_cmd);
|
||||
|
||||
static inline void drm_crtc_helper_add(struct drm_crtc *crtc,
|
||||
const struct drm_crtc_helper_funcs *funcs)
|
||||
@ -144,4 +144,7 @@ extern void drm_helper_hpd_irq_event(struct drm_device *dev);
|
||||
|
||||
extern void drm_kms_helper_poll_disable(struct drm_device *dev);
|
||||
extern void drm_kms_helper_poll_enable(struct drm_device *dev);
|
||||
|
||||
extern int drm_format_num_planes(uint32_t format);
|
||||
|
||||
#endif
|
||||
|
||||
@ -72,8 +72,23 @@
|
||||
|
||||
#define DP_MAIN_LINK_CHANNEL_CODING 0x006
|
||||
|
||||
#define DP_EDP_CONFIGURATION_CAP 0x00d
|
||||
#define DP_TRAINING_AUX_RD_INTERVAL 0x00e
|
||||
|
||||
#define DP_PSR_SUPPORT 0x070
|
||||
# define DP_PSR_IS_SUPPORTED 1
|
||||
#define DP_PSR_CAPS 0x071
|
||||
# define DP_PSR_NO_TRAIN_ON_EXIT 1
|
||||
# define DP_PSR_SETUP_TIME_330 (0 << 1)
|
||||
# define DP_PSR_SETUP_TIME_275 (1 << 1)
|
||||
# define DP_PSR_SETUP_TIME_220 (2 << 1)
|
||||
# define DP_PSR_SETUP_TIME_165 (3 << 1)
|
||||
# define DP_PSR_SETUP_TIME_110 (4 << 1)
|
||||
# define DP_PSR_SETUP_TIME_55 (5 << 1)
|
||||
# define DP_PSR_SETUP_TIME_0 (6 << 1)
|
||||
# define DP_PSR_SETUP_TIME_MASK (7 << 1)
|
||||
# define DP_PSR_SETUP_TIME_SHIFT 1
|
||||
|
||||
/* link configuration */
|
||||
#define DP_LINK_BW_SET 0x100
|
||||
# define DP_LINK_BW_1_62 0x06
|
||||
@ -133,6 +148,20 @@
|
||||
#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
|
||||
# define DP_SET_ANSI_8B10B (1 << 0)
|
||||
|
||||
#define DP_PSR_EN_CFG 0x170
|
||||
# define DP_PSR_ENABLE (1 << 0)
|
||||
# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1)
|
||||
# define DP_PSR_CRC_VERIFICATION (1 << 2)
|
||||
# define DP_PSR_FRAME_CAPTURE (1 << 3)
|
||||
|
||||
#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201
|
||||
# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0)
|
||||
# define DP_AUTOMATED_TEST_REQUEST (1 << 1)
|
||||
# define DP_CP_IRQ (1 << 2)
|
||||
# define DP_SINK_SPECIFIC_IRQ (1 << 6)
|
||||
|
||||
#define DP_EDP_CONFIGURATION_SET 0x10a
|
||||
|
||||
#define DP_LANE0_1_STATUS 0x202
|
||||
#define DP_LANE2_3_STATUS 0x203
|
||||
# define DP_LANE_CR_DONE (1 << 0)
|
||||
@ -165,10 +194,45 @@
|
||||
# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
|
||||
# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
|
||||
|
||||
#define DP_TEST_REQUEST 0x218
|
||||
# define DP_TEST_LINK_TRAINING (1 << 0)
|
||||
# define DP_TEST_LINK_PATTERN (1 << 1)
|
||||
# define DP_TEST_LINK_EDID_READ (1 << 2)
|
||||
# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */
|
||||
|
||||
#define DP_TEST_LINK_RATE 0x219
|
||||
# define DP_LINK_RATE_162 (0x6)
|
||||
# define DP_LINK_RATE_27 (0xa)
|
||||
|
||||
#define DP_TEST_LANE_COUNT 0x220
|
||||
|
||||
#define DP_TEST_PATTERN 0x221
|
||||
|
||||
#define DP_TEST_RESPONSE 0x260
|
||||
# define DP_TEST_ACK (1 << 0)
|
||||
# define DP_TEST_NAK (1 << 1)
|
||||
# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2)
|
||||
|
||||
#define DP_SET_POWER 0x600
|
||||
# define DP_SET_POWER_D0 0x1
|
||||
# define DP_SET_POWER_D3 0x2
|
||||
|
||||
#define DP_PSR_ERROR_STATUS 0x2006
|
||||
# define DP_PSR_LINK_CRC_ERROR (1 << 0)
|
||||
# define DP_PSR_RFB_STORAGE_ERROR (1 << 1)
|
||||
|
||||
#define DP_PSR_ESI 0x2007
|
||||
# define DP_PSR_CAPS_CHANGE (1 << 0)
|
||||
|
||||
#define DP_PSR_STATUS 0x2008
|
||||
# define DP_PSR_SINK_INACTIVE 0
|
||||
# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1
|
||||
# define DP_PSR_SINK_ACTIVE_RFB 2
|
||||
# define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3
|
||||
# define DP_PSR_SINK_ACTIVE_RESYNC 4
|
||||
# define DP_PSR_SINK_INTERNAL_ERROR 7
|
||||
# define DP_PSR_SINK_STATE_MASK 0x07
|
||||
|
||||
#define MODE_I2C_START 1
|
||||
#define MODE_I2C_WRITE 2
|
||||
#define MODE_I2C_READ 4
|
||||
|
||||
@ -230,4 +230,13 @@ struct edid {
|
||||
|
||||
#define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8))
|
||||
|
||||
struct drm_encoder;
|
||||
struct drm_connector;
|
||||
struct drm_display_mode;
|
||||
void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid);
|
||||
int drm_av_sync_delay(struct drm_connector *connector,
|
||||
struct drm_display_mode *mode);
|
||||
struct drm_connector *drm_select_eld(struct drm_encoder *encoder,
|
||||
struct drm_display_mode *mode);
|
||||
|
||||
#endif /* __DRM_EDID_H__ */
|
||||
|
||||
137
drivers/include/drm/drm_fourcc.h
Normal file
137
drivers/include/drm/drm_fourcc.h
Normal file
@ -0,0 +1,137 @@
|
||||
/*
|
||||
* Copyright 2011 Intel Corporation
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef DRM_FOURCC_H
|
||||
#define DRM_FOURCC_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
#define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
|
||||
((__u32)(c) << 16) | ((__u32)(d) << 24))
|
||||
|
||||
#define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of little endian */
|
||||
|
||||
/* color index */
|
||||
#define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
|
||||
|
||||
/* 8 bpp RGB */
|
||||
#define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
|
||||
#define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
|
||||
|
||||
/* 16 bpp RGB */
|
||||
#define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */
|
||||
#define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */
|
||||
#define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */
|
||||
#define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */
|
||||
|
||||
#define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */
|
||||
#define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */
|
||||
#define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */
|
||||
#define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */
|
||||
|
||||
#define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */
|
||||
#define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */
|
||||
#define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */
|
||||
#define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */
|
||||
|
||||
#define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */
|
||||
#define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */
|
||||
#define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */
|
||||
#define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */
|
||||
|
||||
#define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */
|
||||
#define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */
|
||||
|
||||
/* 24 bpp RGB */
|
||||
#define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */
|
||||
#define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */
|
||||
|
||||
/* 32 bpp RGB */
|
||||
#define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */
|
||||
#define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */
|
||||
#define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */
|
||||
#define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */
|
||||
|
||||
#define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */
|
||||
#define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */
|
||||
#define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */
|
||||
#define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */
|
||||
|
||||
#define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */
|
||||
#define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */
|
||||
#define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */
|
||||
#define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */
|
||||
|
||||
#define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */
|
||||
#define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */
|
||||
#define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
|
||||
#define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
|
||||
|
||||
/* packed YCbCr */
|
||||
#define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
|
||||
#define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
|
||||
#define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */
|
||||
#define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
|
||||
|
||||
#define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
|
||||
|
||||
/*
|
||||
* 2 plane YCbCr
|
||||
* index 0 = Y plane, [7:0] Y
|
||||
* index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian
|
||||
* or
|
||||
* index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian
|
||||
*/
|
||||
#define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */
|
||||
#define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */
|
||||
#define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */
|
||||
#define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
|
||||
|
||||
/* 2 non contiguous plane YCbCr */
|
||||
#define DRM_FORMAT_NV12M fourcc_code('N', 'M', '1', '2') /* 2x2 subsampled Cr:Cb plane */
|
||||
#define DRM_FORMAT_NV12MT fourcc_code('T', 'M', '1', '2') /* 2x2 subsampled Cr:Cb plane 64x32 macroblocks */
|
||||
|
||||
/*
|
||||
* 3 plane YCbCr
|
||||
* index 0: Y plane, [7:0] Y
|
||||
* index 1: Cb plane, [7:0] Cb
|
||||
* index 2: Cr plane, [7:0] Cr
|
||||
* or
|
||||
* index 1: Cr plane, [7:0] Cr
|
||||
* index 2: Cb plane, [7:0] Cb
|
||||
*/
|
||||
#define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */
|
||||
#define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */
|
||||
#define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */
|
||||
#define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */
|
||||
#define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */
|
||||
#define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */
|
||||
#define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */
|
||||
#define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */
|
||||
#define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */
|
||||
#define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */
|
||||
|
||||
/* 3 non contiguous plane YCbCr */
|
||||
#define DRM_FORMAT_YUV420M fourcc_code('Y', 'M', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */
|
||||
|
||||
#endif /* DRM_FOURCC_H */
|
||||
@ -120,11 +120,49 @@ struct drm_mode_crtc {
|
||||
struct drm_mode_modeinfo mode;
|
||||
};
|
||||
|
||||
#define DRM_MODE_PRESENT_TOP_FIELD (1<<0)
|
||||
#define DRM_MODE_PRESENT_BOTTOM_FIELD (1<<1)
|
||||
|
||||
/* Planes blend with or override other bits on the CRTC */
|
||||
struct drm_mode_set_plane {
|
||||
__u32 plane_id;
|
||||
__u32 crtc_id;
|
||||
__u32 fb_id; /* fb object contains surface format type */
|
||||
__u32 flags; /* see above flags */
|
||||
|
||||
/* Signed dest location allows it to be partially off screen */
|
||||
__s32 crtc_x, crtc_y;
|
||||
__u32 crtc_w, crtc_h;
|
||||
|
||||
/* Source values are 16.16 fixed point */
|
||||
__u32 src_x, src_y;
|
||||
__u32 src_h, src_w;
|
||||
};
|
||||
|
||||
struct drm_mode_get_plane {
|
||||
__u32 plane_id;
|
||||
|
||||
__u32 crtc_id;
|
||||
__u32 fb_id;
|
||||
|
||||
__u32 possible_crtcs;
|
||||
__u32 gamma_size;
|
||||
|
||||
__u32 count_format_types;
|
||||
__u64 format_type_ptr;
|
||||
};
|
||||
|
||||
struct drm_mode_get_plane_res {
|
||||
__u64 plane_id_ptr;
|
||||
__u32 count_planes;
|
||||
};
|
||||
|
||||
#define DRM_MODE_ENCODER_NONE 0
|
||||
#define DRM_MODE_ENCODER_DAC 1
|
||||
#define DRM_MODE_ENCODER_TMDS 2
|
||||
#define DRM_MODE_ENCODER_LVDS 3
|
||||
#define DRM_MODE_ENCODER_TVDAC 4
|
||||
#define DRM_MODE_ENCODER_VIRTUAL 5
|
||||
|
||||
struct drm_mode_get_encoder {
|
||||
__u32 encoder_id;
|
||||
@ -162,6 +200,7 @@ struct drm_mode_get_encoder {
|
||||
#define DRM_MODE_CONNECTOR_HDMIB 12
|
||||
#define DRM_MODE_CONNECTOR_TV 13
|
||||
#define DRM_MODE_CONNECTOR_eDP 14
|
||||
#define DRM_MODE_CONNECTOR_VIRTUAL 15
|
||||
|
||||
struct drm_mode_get_connector {
|
||||
|
||||
@ -229,10 +268,39 @@ struct drm_mode_fb_cmd {
|
||||
__u32 handle;
|
||||
};
|
||||
|
||||
#define DRM_MODE_FB_INTERLACED (1<<0) /* for interlaced framebuffers */
|
||||
|
||||
struct drm_mode_fb_cmd2 {
|
||||
__u32 fb_id;
|
||||
__u32 width, height;
|
||||
__u32 pixel_format; /* fourcc code from drm_fourcc.h */
|
||||
__u32 flags; /* see above flags */
|
||||
|
||||
/*
|
||||
* In case of planar formats, this ioctl allows up to 4
|
||||
* buffer objects with offets and pitches per plane.
|
||||
* The pitch and offset order is dictated by the fourcc,
|
||||
* e.g. NV12 (http://fourcc.org/yuv.php#NV12) is described as:
|
||||
*
|
||||
* YUV 4:2:0 image with a plane of 8 bit Y samples
|
||||
* followed by an interleaved U/V plane containing
|
||||
* 8 bit 2x2 subsampled colour difference samples.
|
||||
*
|
||||
* So it would consist of Y as offset[0] and UV as
|
||||
* offeset[1]. Note that offset[0] will generally
|
||||
* be 0.
|
||||
*/
|
||||
__u32 handles[4];
|
||||
__u32 pitches[4]; /* pitch for each plane */
|
||||
__u32 offsets[4]; /* offset of each plane */
|
||||
};
|
||||
|
||||
#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01
|
||||
#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02
|
||||
#define DRM_MODE_FB_DIRTY_FLAGS 0x03
|
||||
|
||||
#define DRM_MODE_FB_DIRTY_MAX_CLIPS 256
|
||||
|
||||
/*
|
||||
* Mark a region of a framebuffer as dirty.
|
||||
*
|
||||
|
||||
@ -4,6 +4,7 @@
|
||||
*/
|
||||
#define radeon_PCI_IDS \
|
||||
{0x1002, 0x3150, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \
|
||||
{0x1002, 0x3151, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x3152, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x3154, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x3155, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
||||
@ -55,6 +56,7 @@
|
||||
{0x1002, 0x4C64, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250|RADEON_IS_MOBILITY}, \
|
||||
{0x1002, 0x4C66, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250|RADEON_IS_MOBILITY}, \
|
||||
{0x1002, 0x4C67, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250|RADEON_IS_MOBILITY}, \
|
||||
{0x1002, 0x4C6E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280|RADEON_IS_MOBILITY}, \
|
||||
{0x1002, 0x4E44, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
|
||||
{0x1002, 0x4E45, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
|
||||
{0x1002, 0x4E46, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
|
||||
@ -180,8 +182,11 @@
|
||||
{0x1002, 0x6748, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6749, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6750, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6751, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6758, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6759, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x675B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x675D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x675F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6760, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAICOS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6761, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAICOS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
||||
@ -193,6 +198,7 @@
|
||||
{0x1002, 0x6767, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAICOS|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6768, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAICOS|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6770, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAICOS|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6772, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAICOS|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6778, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAICOS|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6779, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAICOS|RADEON_NEW_MEMMAP}, \
|
||||
{0x1002, 0x6880, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
|
||||
|
||||
43
drivers/include/drm/intel-gtt.h
Normal file
43
drivers/include/drm/intel-gtt.h
Normal file
@ -0,0 +1,43 @@
|
||||
/* Common header for intel-gtt.ko and i915.ko */
|
||||
|
||||
#ifndef _DRM_INTEL_GTT_H
|
||||
#define _DRM_INTEL_GTT_H
|
||||
|
||||
const struct intel_gtt {
|
||||
/* Size of memory reserved for graphics by the BIOS */
|
||||
unsigned int stolen_size;
|
||||
/* Total number of gtt entries. */
|
||||
unsigned int gtt_total_entries;
|
||||
/* Part of the gtt that is mappable by the cpu, for those chips where
|
||||
* this is not the full gtt. */
|
||||
unsigned int gtt_mappable_entries;
|
||||
/* Whether i915 needs to use the dmar apis or not. */
|
||||
unsigned int needs_dmar : 1;
|
||||
/* Whether we idle the gpu before mapping/unmapping */
|
||||
unsigned int do_idle_maps : 1;
|
||||
} *intel_gtt_get(void);
|
||||
|
||||
void intel_gtt_chipset_flush(void);
|
||||
void intel_gtt_unmap_memory(struct scatterlist *sg_list, int num_sg);
|
||||
void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries);
|
||||
int intel_gtt_map_memory(struct page **pages, unsigned int num_entries,
|
||||
struct scatterlist **sg_list, int *num_sg);
|
||||
void intel_gtt_insert_sg_entries(struct scatterlist *sg_list,
|
||||
unsigned int sg_len,
|
||||
unsigned int pg_start,
|
||||
unsigned int flags);
|
||||
void intel_gtt_insert_pages(unsigned int first_entry, unsigned int num_entries,
|
||||
struct page **pages, unsigned int flags);
|
||||
|
||||
/* Special gtt memory types */
|
||||
#define AGP_DCACHE_MEMORY 1
|
||||
#define AGP_PHYS_MEMORY 2
|
||||
|
||||
/* New caching attributes for gen6/sandybridge */
|
||||
#define AGP_USER_CACHED_MEMORY_LLC_MLC (AGP_USER_TYPES + 2)
|
||||
#define AGP_USER_UNCACHED_MEMORY (AGP_USER_TYPES + 4)
|
||||
|
||||
/* flag for GFDT type */
|
||||
#define AGP_USER_CACHED_MEMORY_GFDT (1 << 3)
|
||||
|
||||
#endif
|
||||
@ -550,6 +550,7 @@ typedef struct {
|
||||
#define DRM_IOCTL_RADEON_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling)
|
||||
#define DRM_IOCTL_RADEON_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling)
|
||||
#define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy)
|
||||
#define DRM_IOCTL_RADEON_GEM_VA DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_VA, struct drm_radeon_gem_va)
|
||||
|
||||
typedef struct drm_radeon_init {
|
||||
enum {
|
||||
@ -872,8 +873,39 @@ struct drm_radeon_gem_pwrite {
|
||||
uint64_t data_ptr;
|
||||
};
|
||||
|
||||
#define RADEON_VA_MAP 1
|
||||
#define RADEON_VA_UNMAP 2
|
||||
|
||||
#define RADEON_VA_RESULT_OK 0
|
||||
#define RADEON_VA_RESULT_ERROR 1
|
||||
#define RADEON_VA_RESULT_VA_EXIST 2
|
||||
|
||||
#define RADEON_VM_PAGE_VALID (1 << 0)
|
||||
#define RADEON_VM_PAGE_READABLE (1 << 1)
|
||||
#define RADEON_VM_PAGE_WRITEABLE (1 << 2)
|
||||
#define RADEON_VM_PAGE_SYSTEM (1 << 3)
|
||||
#define RADEON_VM_PAGE_SNOOPED (1 << 4)
|
||||
|
||||
struct drm_radeon_gem_va {
|
||||
uint32_t handle;
|
||||
uint32_t operation;
|
||||
uint32_t vm_id;
|
||||
uint32_t flags;
|
||||
uint64_t offset;
|
||||
};
|
||||
|
||||
#define RADEON_CHUNK_ID_RELOCS 0x01
|
||||
#define RADEON_CHUNK_ID_IB 0x02
|
||||
#define RADEON_CHUNK_ID_FLAGS 0x03
|
||||
|
||||
/* The first dword of RADEON_CHUNK_ID_FLAGS is a uint32 of these flags: */
|
||||
#define RADEON_CS_KEEP_TILING_FLAGS 0x01
|
||||
#define RADEON_CS_USE_VM 0x02
|
||||
/* The second dword of RADEON_CHUNK_ID_FLAGS is a uint32 that sets the ring type */
|
||||
#define RADEON_CS_RING_GFX 0
|
||||
#define RADEON_CS_RING_COMPUTE 1
|
||||
/* The third dword of RADEON_CHUNK_ID_FLAGS is a sint32 that sets the priority */
|
||||
/* 0 = normal, + = higher priority, - = lower priority */
|
||||
|
||||
struct drm_radeon_cs_chunk {
|
||||
uint32_t chunk_id;
|
||||
@ -881,6 +913,9 @@ struct drm_radeon_cs_chunk {
|
||||
uint64_t chunk_data;
|
||||
};
|
||||
|
||||
/* drm_radeon_cs_reloc.flags */
|
||||
#define RADEON_RELOC_DONT_SYNC 0x01
|
||||
|
||||
struct drm_radeon_cs_reloc {
|
||||
uint32_t handle;
|
||||
uint32_t read_domains;
|
||||
@ -912,6 +947,10 @@ struct drm_radeon_cs {
|
||||
#define RADEON_INFO_NUM_TILE_PIPES 0x0b /* tile pipes for r600+ */
|
||||
#define RADEON_INFO_FUSION_GART_WORKING 0x0c /* fusion writes to GTT were broken before this */
|
||||
#define RADEON_INFO_BACKEND_MAP 0x0d /* pipe to backend map, needed by mesa */
|
||||
/* virtual address start, va < start are reserved by the kernel */
|
||||
#define RADEON_INFO_VA_START 0x0e
|
||||
/* maximum size of ib using the virtual memory cs */
|
||||
#define RADEON_INFO_IB_VM_MAX_SIZE 0x0f
|
||||
|
||||
struct drm_radeon_info {
|
||||
uint32_t request;
|
||||
|
||||
@ -144,7 +144,9 @@ extern int bitmap_find_free_region(unsigned long *bitmap, int bits, int order);
|
||||
extern void bitmap_release_region(unsigned long *bitmap, int pos, int order);
|
||||
extern int bitmap_allocate_region(unsigned long *bitmap, int pos, int order);
|
||||
extern void bitmap_copy_le(void *dst, const unsigned long *src, int nbits);
|
||||
extern int bitmap_ord_to_pos(const unsigned long *bitmap, int n, int bits);
|
||||
|
||||
#define BITMAP_FIRST_WORD_MASK(start) (~0UL << ((start) % BITS_PER_LONG))
|
||||
#define BITMAP_LAST_WORD_MASK(nbits) \
|
||||
( \
|
||||
((nbits) % BITS_PER_LONG) ? \
|
||||
|
||||
@ -52,4 +52,13 @@ static inline unsigned char __toupper(unsigned char c)
|
||||
#define tolower(c) __tolower(c)
|
||||
#define toupper(c) __toupper(c)
|
||||
|
||||
/*
|
||||
* Fast implementation of tolower() for internal usage. Do not use in your
|
||||
* code.
|
||||
*/
|
||||
static inline char _tolower(const char c)
|
||||
{
|
||||
return c | 0x20;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
@ -111,4 +111,6 @@
|
||||
|
||||
#define ERFKILL 132 /* Operation not possible due to RF-kill */
|
||||
|
||||
#define ENOTSUPP 524 /* Operation is not supported */
|
||||
|
||||
#endif
|
||||
|
||||
@ -280,15 +280,13 @@ void i2c_unlock_adapter(struct i2c_adapter *);
|
||||
/* Internal numbers to terminate lists */
|
||||
#define I2C_CLIENT_END 0xfffeU
|
||||
|
||||
/* The numbers to use to set I2C bus address */
|
||||
#define ANY_I2C_BUS 0xffff
|
||||
|
||||
/* Construct an I2C_CLIENT_END-terminated array of i2c addresses */
|
||||
#define I2C_ADDRS(addr, addrs...) \
|
||||
((const unsigned short []){ addr, ## addrs, I2C_CLIENT_END })
|
||||
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
/**
|
||||
* struct i2c_msg - an I2C transaction segment beginning with START
|
||||
* @addr: Slave address, either seven or ten bits. When this is a ten
|
||||
|
||||
307
drivers/include/linux/jiffies.h
Normal file
307
drivers/include/linux/jiffies.h
Normal file
@ -0,0 +1,307 @@
|
||||
#ifndef _LINUX_JIFFIES_H
|
||||
#define _LINUX_JIFFIES_H
|
||||
|
||||
//#include <linux/math64.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/types.h>
|
||||
//#include <linux/time.h>
|
||||
//#include <linux/timex.h>
|
||||
//#include <asm/param.h> /* for HZ */
|
||||
|
||||
|
||||
#define HZ 100
|
||||
#define CLOCK_TICK_RATE 1193182ul
|
||||
|
||||
/*
|
||||
* The following defines establish the engineering parameters of the PLL
|
||||
* model. The HZ variable establishes the timer interrupt frequency, 100 Hz
|
||||
* for the SunOS kernel, 256 Hz for the Ultrix kernel and 1024 Hz for the
|
||||
* OSF/1 kernel. The SHIFT_HZ define expresses the same value as the
|
||||
* nearest power of two in order to avoid hardware multiply operations.
|
||||
*/
|
||||
#if HZ >= 12 && HZ < 24
|
||||
# define SHIFT_HZ 4
|
||||
#elif HZ >= 24 && HZ < 48
|
||||
# define SHIFT_HZ 5
|
||||
#elif HZ >= 48 && HZ < 96
|
||||
# define SHIFT_HZ 6
|
||||
#elif HZ >= 96 && HZ < 192
|
||||
# define SHIFT_HZ 7
|
||||
#elif HZ >= 192 && HZ < 384
|
||||
# define SHIFT_HZ 8
|
||||
#elif HZ >= 384 && HZ < 768
|
||||
# define SHIFT_HZ 9
|
||||
#elif HZ >= 768 && HZ < 1536
|
||||
# define SHIFT_HZ 10
|
||||
#elif HZ >= 1536 && HZ < 3072
|
||||
# define SHIFT_HZ 11
|
||||
#elif HZ >= 3072 && HZ < 6144
|
||||
# define SHIFT_HZ 12
|
||||
#elif HZ >= 6144 && HZ < 12288
|
||||
# define SHIFT_HZ 13
|
||||
#else
|
||||
# error Invalid value of HZ.
|
||||
#endif
|
||||
|
||||
/* LATCH is used in the interval timer and ftape setup. */
|
||||
#define LATCH ((CLOCK_TICK_RATE + HZ/2) / HZ) /* For divider */
|
||||
|
||||
/* Suppose we want to divide two numbers NOM and DEN: NOM/DEN, then we can
|
||||
* improve accuracy by shifting LSH bits, hence calculating:
|
||||
* (NOM << LSH) / DEN
|
||||
* This however means trouble for large NOM, because (NOM << LSH) may no
|
||||
* longer fit in 32 bits. The following way of calculating this gives us
|
||||
* some slack, under the following conditions:
|
||||
* - (NOM / DEN) fits in (32 - LSH) bits.
|
||||
* - (NOM % DEN) fits in (32 - LSH) bits.
|
||||
*/
|
||||
#define SH_DIV(NOM,DEN,LSH) ( (((NOM) / (DEN)) << (LSH)) \
|
||||
+ ((((NOM) % (DEN)) << (LSH)) + (DEN) / 2) / (DEN))
|
||||
|
||||
/* HZ is the requested value. ACTHZ is actual HZ ("<< 8" is for accuracy) */
|
||||
#define ACTHZ (SH_DIV (CLOCK_TICK_RATE, LATCH, 8))
|
||||
|
||||
/* TICK_NSEC is the time between ticks in nsec assuming real ACTHZ */
|
||||
#define TICK_NSEC (SH_DIV (1000000UL * 1000, ACTHZ, 8))
|
||||
|
||||
/* TICK_USEC is the time between ticks in usec assuming fake USER_HZ */
|
||||
#define TICK_USEC ((1000000UL + USER_HZ/2) / USER_HZ)
|
||||
|
||||
/* TICK_USEC_TO_NSEC is the time between ticks in nsec assuming real ACTHZ and */
|
||||
/* a value TUSEC for TICK_USEC (can be set bij adjtimex) */
|
||||
#define TICK_USEC_TO_NSEC(TUSEC) (SH_DIV (TUSEC * USER_HZ * 1000, ACTHZ, 8))
|
||||
|
||||
#define jiffies GetTimerTicks()
|
||||
|
||||
#if (BITS_PER_LONG < 64)
|
||||
u64 get_jiffies_64(void);
|
||||
#else
|
||||
static inline u64 get_jiffies_64(void)
|
||||
{
|
||||
return (u64)jiffies;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* These inlines deal with timer wrapping correctly. You are
|
||||
* strongly encouraged to use them
|
||||
* 1. Because people otherwise forget
|
||||
* 2. Because if the timer wrap changes in future you won't have to
|
||||
* alter your driver code.
|
||||
*
|
||||
* time_after(a,b) returns true if the time a is after time b.
|
||||
*
|
||||
* Do this with "<0" and ">=0" to only test the sign of the result. A
|
||||
* good compiler would generate better code (and a really good compiler
|
||||
* wouldn't care). Gcc is currently neither.
|
||||
*/
|
||||
#define time_after(a,b) \
|
||||
(typecheck(unsigned long, a) && \
|
||||
typecheck(unsigned long, b) && \
|
||||
((long)(b) - (long)(a) < 0))
|
||||
#define time_before(a,b) time_after(b,a)
|
||||
|
||||
#define time_after_eq(a,b) \
|
||||
(typecheck(unsigned long, a) && \
|
||||
typecheck(unsigned long, b) && \
|
||||
((long)(a) - (long)(b) >= 0))
|
||||
#define time_before_eq(a,b) time_after_eq(b,a)
|
||||
|
||||
/*
|
||||
* Calculate whether a is in the range of [b, c].
|
||||
*/
|
||||
#define time_in_range(a,b,c) \
|
||||
(time_after_eq(a,b) && \
|
||||
time_before_eq(a,c))
|
||||
|
||||
/*
|
||||
* Calculate whether a is in the range of [b, c).
|
||||
*/
|
||||
#define time_in_range_open(a,b,c) \
|
||||
(time_after_eq(a,b) && \
|
||||
time_before(a,c))
|
||||
|
||||
/* Same as above, but does so with platform independent 64bit types.
|
||||
* These must be used when utilizing jiffies_64 (i.e. return value of
|
||||
* get_jiffies_64() */
|
||||
#define time_after64(a,b) \
|
||||
(typecheck(__u64, a) && \
|
||||
typecheck(__u64, b) && \
|
||||
((__s64)(b) - (__s64)(a) < 0))
|
||||
#define time_before64(a,b) time_after64(b,a)
|
||||
|
||||
#define time_after_eq64(a,b) \
|
||||
(typecheck(__u64, a) && \
|
||||
typecheck(__u64, b) && \
|
||||
((__s64)(a) - (__s64)(b) >= 0))
|
||||
#define time_before_eq64(a,b) time_after_eq64(b,a)
|
||||
|
||||
/*
|
||||
* These four macros compare jiffies and 'a' for convenience.
|
||||
*/
|
||||
|
||||
/* time_is_before_jiffies(a) return true if a is before jiffies */
|
||||
#define time_is_before_jiffies(a) time_after(jiffies, a)
|
||||
|
||||
/* time_is_after_jiffies(a) return true if a is after jiffies */
|
||||
#define time_is_after_jiffies(a) time_before(jiffies, a)
|
||||
|
||||
/* time_is_before_eq_jiffies(a) return true if a is before or equal to jiffies*/
|
||||
#define time_is_before_eq_jiffies(a) time_after_eq(jiffies, a)
|
||||
|
||||
/* time_is_after_eq_jiffies(a) return true if a is after or equal to jiffies*/
|
||||
#define time_is_after_eq_jiffies(a) time_before_eq(jiffies, a)
|
||||
|
||||
/*
|
||||
* Have the 32 bit jiffies value wrap 5 minutes after boot
|
||||
* so jiffies wrap bugs show up earlier.
|
||||
*/
|
||||
#define INITIAL_JIFFIES ((unsigned long)(unsigned int) (-300*HZ))
|
||||
|
||||
/*
|
||||
* Change timeval to jiffies, trying to avoid the
|
||||
* most obvious overflows..
|
||||
*
|
||||
* And some not so obvious.
|
||||
*
|
||||
* Note that we don't want to return LONG_MAX, because
|
||||
* for various timeout reasons we often end up having
|
||||
* to wait "jiffies+1" in order to guarantee that we wait
|
||||
* at _least_ "jiffies" - so "jiffies+1" had better still
|
||||
* be positive.
|
||||
*/
|
||||
#define MAX_JIFFY_OFFSET ((LONG_MAX >> 1)-1)
|
||||
|
||||
extern unsigned long preset_lpj;
|
||||
|
||||
/*
|
||||
* We want to do realistic conversions of time so we need to use the same
|
||||
* values the update wall clock code uses as the jiffies size. This value
|
||||
* is: TICK_NSEC (which is defined in timex.h). This
|
||||
* is a constant and is in nanoseconds. We will use scaled math
|
||||
* with a set of scales defined here as SEC_JIFFIE_SC, USEC_JIFFIE_SC and
|
||||
* NSEC_JIFFIE_SC. Note that these defines contain nothing but
|
||||
* constants and so are computed at compile time. SHIFT_HZ (computed in
|
||||
* timex.h) adjusts the scaling for different HZ values.
|
||||
|
||||
* Scaled math??? What is that?
|
||||
*
|
||||
* Scaled math is a way to do integer math on values that would,
|
||||
* otherwise, either overflow, underflow, or cause undesired div
|
||||
* instructions to appear in the execution path. In short, we "scale"
|
||||
* up the operands so they take more bits (more precision, less
|
||||
* underflow), do the desired operation and then "scale" the result back
|
||||
* by the same amount. If we do the scaling by shifting we avoid the
|
||||
* costly mpy and the dastardly div instructions.
|
||||
|
||||
* Suppose, for example, we want to convert from seconds to jiffies
|
||||
* where jiffies is defined in nanoseconds as NSEC_PER_JIFFIE. The
|
||||
* simple math is: jiff = (sec * NSEC_PER_SEC) / NSEC_PER_JIFFIE; We
|
||||
* observe that (NSEC_PER_SEC / NSEC_PER_JIFFIE) is a constant which we
|
||||
* might calculate at compile time, however, the result will only have
|
||||
* about 3-4 bits of precision (less for smaller values of HZ).
|
||||
*
|
||||
* So, we scale as follows:
|
||||
* jiff = (sec) * (NSEC_PER_SEC / NSEC_PER_JIFFIE);
|
||||
* jiff = ((sec) * ((NSEC_PER_SEC * SCALE)/ NSEC_PER_JIFFIE)) / SCALE;
|
||||
* Then we make SCALE a power of two so:
|
||||
* jiff = ((sec) * ((NSEC_PER_SEC << SCALE)/ NSEC_PER_JIFFIE)) >> SCALE;
|
||||
* Now we define:
|
||||
* #define SEC_CONV = ((NSEC_PER_SEC << SCALE)/ NSEC_PER_JIFFIE))
|
||||
* jiff = (sec * SEC_CONV) >> SCALE;
|
||||
*
|
||||
* Often the math we use will expand beyond 32-bits so we tell C how to
|
||||
* do this and pass the 64-bit result of the mpy through the ">> SCALE"
|
||||
* which should take the result back to 32-bits. We want this expansion
|
||||
* to capture as much precision as possible. At the same time we don't
|
||||
* want to overflow so we pick the SCALE to avoid this. In this file,
|
||||
* that means using a different scale for each range of HZ values (as
|
||||
* defined in timex.h).
|
||||
*
|
||||
* For those who want to know, gcc will give a 64-bit result from a "*"
|
||||
* operator if the result is a long long AND at least one of the
|
||||
* operands is cast to long long (usually just prior to the "*" so as
|
||||
* not to confuse it into thinking it really has a 64-bit operand,
|
||||
* which, buy the way, it can do, but it takes more code and at least 2
|
||||
* mpys).
|
||||
|
||||
* We also need to be aware that one second in nanoseconds is only a
|
||||
* couple of bits away from overflowing a 32-bit word, so we MUST use
|
||||
* 64-bits to get the full range time in nanoseconds.
|
||||
|
||||
*/
|
||||
|
||||
/*
|
||||
* Here are the scales we will use. One for seconds, nanoseconds and
|
||||
* microseconds.
|
||||
*
|
||||
* Within the limits of cpp we do a rough cut at the SEC_JIFFIE_SC and
|
||||
* check if the sign bit is set. If not, we bump the shift count by 1.
|
||||
* (Gets an extra bit of precision where we can use it.)
|
||||
* We know it is set for HZ = 1024 and HZ = 100 not for 1000.
|
||||
* Haven't tested others.
|
||||
|
||||
* Limits of cpp (for #if expressions) only long (no long long), but
|
||||
* then we only need the most signicant bit.
|
||||
*/
|
||||
|
||||
#define SEC_JIFFIE_SC (31 - SHIFT_HZ)
|
||||
#if !((((NSEC_PER_SEC << 2) / TICK_NSEC) << (SEC_JIFFIE_SC - 2)) & 0x80000000)
|
||||
#undef SEC_JIFFIE_SC
|
||||
#define SEC_JIFFIE_SC (32 - SHIFT_HZ)
|
||||
#endif
|
||||
#define NSEC_JIFFIE_SC (SEC_JIFFIE_SC + 29)
|
||||
#define USEC_JIFFIE_SC (SEC_JIFFIE_SC + 19)
|
||||
#define SEC_CONVERSION ((unsigned long)((((u64)NSEC_PER_SEC << SEC_JIFFIE_SC) +\
|
||||
TICK_NSEC -1) / (u64)TICK_NSEC))
|
||||
|
||||
#define NSEC_CONVERSION ((unsigned long)((((u64)1 << NSEC_JIFFIE_SC) +\
|
||||
TICK_NSEC -1) / (u64)TICK_NSEC))
|
||||
#define USEC_CONVERSION \
|
||||
((unsigned long)((((u64)NSEC_PER_USEC << USEC_JIFFIE_SC) +\
|
||||
TICK_NSEC -1) / (u64)TICK_NSEC))
|
||||
/*
|
||||
* USEC_ROUND is used in the timeval to jiffie conversion. See there
|
||||
* for more details. It is the scaled resolution rounding value. Note
|
||||
* that it is a 64-bit value. Since, when it is applied, we are already
|
||||
* in jiffies (albit scaled), it is nothing but the bits we will shift
|
||||
* off.
|
||||
*/
|
||||
#define USEC_ROUND (u64)(((u64)1 << USEC_JIFFIE_SC) - 1)
|
||||
/*
|
||||
* The maximum jiffie value is (MAX_INT >> 1). Here we translate that
|
||||
* into seconds. The 64-bit case will overflow if we are not careful,
|
||||
* so use the messy SH_DIV macro to do it. Still all constants.
|
||||
*/
|
||||
#if BITS_PER_LONG < 64
|
||||
# define MAX_SEC_IN_JIFFIES \
|
||||
(long)((u64)((u64)MAX_JIFFY_OFFSET * TICK_NSEC) / NSEC_PER_SEC)
|
||||
#else /* take care of overflow on 64 bits machines */
|
||||
# define MAX_SEC_IN_JIFFIES \
|
||||
(SH_DIV((MAX_JIFFY_OFFSET >> SEC_JIFFIE_SC) * TICK_NSEC, NSEC_PER_SEC, 1) - 1)
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Convert various time units to each other:
|
||||
*/
|
||||
extern unsigned int jiffies_to_msecs(const unsigned long j);
|
||||
extern unsigned int jiffies_to_usecs(const unsigned long j);
|
||||
extern unsigned long msecs_to_jiffies(const unsigned int m);
|
||||
extern unsigned long usecs_to_jiffies(const unsigned int u);
|
||||
extern unsigned long timespec_to_jiffies(const struct timespec *value);
|
||||
extern void jiffies_to_timespec(const unsigned long jiffies,
|
||||
struct timespec *value);
|
||||
extern unsigned long timeval_to_jiffies(const struct timeval *value);
|
||||
extern void jiffies_to_timeval(const unsigned long jiffies,
|
||||
struct timeval *value);
|
||||
extern clock_t jiffies_to_clock_t(unsigned long x);
|
||||
extern unsigned long clock_t_to_jiffies(unsigned long x);
|
||||
extern u64 jiffies_64_to_clock_t(u64 x);
|
||||
extern u64 nsec_to_clock_t(u64 x);
|
||||
extern u64 nsecs_to_jiffies64(u64 n);
|
||||
extern unsigned long nsecs_to_jiffies(u64 n);
|
||||
|
||||
#define TIMESTAMP_SIZE 30
|
||||
|
||||
#endif
|
||||
@ -13,6 +13,10 @@
|
||||
#include <linux/compiler.h>
|
||||
#include <linux/bitops.h>
|
||||
|
||||
#include <linux/typecheck.h>
|
||||
|
||||
#define __init
|
||||
|
||||
#define USHRT_MAX ((u16)(~0U))
|
||||
#define SHRT_MAX ((s16)(USHRT_MAX>>1))
|
||||
#define SHRT_MIN ((s16)(-SHRT_MAX - 1))
|
||||
@ -31,6 +35,16 @@
|
||||
#define PTR_ALIGN(p, a) ((typeof(p))ALIGN((unsigned long)(p), (a)))
|
||||
#define IS_ALIGNED(x, a) (((x) & ((typeof(x))(a) - 1)) == 0)
|
||||
|
||||
#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
|
||||
|
||||
#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
|
||||
#define DIV_ROUND_CLOSEST(x, divisor)( \
|
||||
{ \
|
||||
typeof(divisor) __divisor = divisor; \
|
||||
(((x) + ((__divisor) / 2)) / (__divisor)); \
|
||||
} \
|
||||
)
|
||||
|
||||
/**
|
||||
* upper_32_bits - return bits 32-63 of a number
|
||||
* @n: the number we're accessing
|
||||
@ -220,6 +234,119 @@ static inline void *dev_get_drvdata(struct device *dev)
|
||||
typecheck(unsigned long, b) && \
|
||||
((long)(b) - (long)(a) < 0))
|
||||
|
||||
struct tvec_base;
|
||||
|
||||
struct timer_list {
|
||||
struct list_head entry;
|
||||
unsigned long expires;
|
||||
|
||||
void (*function)(unsigned long);
|
||||
unsigned long data;
|
||||
|
||||
// struct tvec_base *base;
|
||||
};
|
||||
|
||||
struct timespec {
|
||||
long tv_sec; /* seconds */
|
||||
long tv_nsec; /* nanoseconds */
|
||||
};
|
||||
|
||||
|
||||
#define build_mmio_read(name, size, type, reg, barrier) \
|
||||
static inline type name(const volatile void __iomem *addr) \
|
||||
{ type ret; asm volatile("mov" size " %1,%0":reg (ret) \
|
||||
:"m" (*(volatile type __force *)addr) barrier); return ret; }
|
||||
|
||||
#define build_mmio_write(name, size, type, reg, barrier) \
|
||||
static inline void name(type val, volatile void __iomem *addr) \
|
||||
{ asm volatile("mov" size " %0,%1": :reg (val), \
|
||||
"m" (*(volatile type __force *)addr) barrier); }
|
||||
|
||||
build_mmio_read(readb, "b", unsigned char, "=q", :"memory")
|
||||
build_mmio_read(readw, "w", unsigned short, "=r", :"memory")
|
||||
build_mmio_read(readl, "l", unsigned int, "=r", :"memory")
|
||||
|
||||
build_mmio_read(__readb, "b", unsigned char, "=q", )
|
||||
build_mmio_read(__readw, "w", unsigned short, "=r", )
|
||||
build_mmio_read(__readl, "l", unsigned int, "=r", )
|
||||
|
||||
build_mmio_write(writeb, "b", unsigned char, "q", :"memory")
|
||||
build_mmio_write(writew, "w", unsigned short, "r", :"memory")
|
||||
build_mmio_write(writel, "l", unsigned int, "r", :"memory")
|
||||
|
||||
build_mmio_write(__writeb, "b", unsigned char, "q", )
|
||||
build_mmio_write(__writew, "w", unsigned short, "r", )
|
||||
build_mmio_write(__writel, "l", unsigned int, "r", )
|
||||
|
||||
#define readb_relaxed(a) __readb(a)
|
||||
#define readw_relaxed(a) __readw(a)
|
||||
#define readl_relaxed(a) __readl(a)
|
||||
#define __raw_readb __readb
|
||||
#define __raw_readw __readw
|
||||
#define __raw_readl __readl
|
||||
|
||||
#define __raw_writeb __writeb
|
||||
#define __raw_writew __writew
|
||||
#define __raw_writel __writel
|
||||
|
||||
static inline __u64 readq(const volatile void __iomem *addr)
|
||||
{
|
||||
const volatile u32 __iomem *p = addr;
|
||||
u32 low, high;
|
||||
|
||||
low = readl(p);
|
||||
high = readl(p + 1);
|
||||
|
||||
return low + ((u64)high << 32);
|
||||
}
|
||||
|
||||
static inline void writeq(__u64 val, volatile void __iomem *addr)
|
||||
{
|
||||
writel(val, addr);
|
||||
writel(val >> 32, addr+4);
|
||||
}
|
||||
|
||||
|
||||
#define mmiowb() barrier()
|
||||
|
||||
#define dev_err(dev, format, arg...) \
|
||||
printk("Error %s " format, __func__ , ## arg)
|
||||
|
||||
#define dev_warn(dev, format, arg...) \
|
||||
printk("Warning %s " format, __func__ , ## arg)
|
||||
|
||||
#define dev_info(dev, format, arg...) \
|
||||
printk("Info %s " format , __func__, ## arg)
|
||||
|
||||
#define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)]))
|
||||
|
||||
|
||||
struct scatterlist {
|
||||
unsigned long page_link;
|
||||
unsigned int offset;
|
||||
unsigned int length;
|
||||
dma_addr_t dma_address;
|
||||
unsigned int dma_length;
|
||||
};
|
||||
|
||||
struct page
|
||||
{
|
||||
unsigned int addr;
|
||||
};
|
||||
|
||||
|
||||
struct vm_fault {
|
||||
unsigned int flags; /* FAULT_FLAG_xxx flags */
|
||||
pgoff_t pgoff; /* Logical page offset based on vma */
|
||||
void __user *virtual_address; /* Faulting virtual address */
|
||||
|
||||
struct page *page; /* ->fault handlers should return a
|
||||
* page here, unless VM_FAULT_NOPAGE
|
||||
* is set (which is also implied by
|
||||
* VM_FAULT_ERROR).
|
||||
*/
|
||||
};
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
@ -542,7 +542,7 @@ do { \
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PROVE_RCU
|
||||
extern void lockdep_rcu_dereference(const char *file, const int line);
|
||||
void lockdep_rcu_suspicious(const char *file, const int line, const char *s);
|
||||
#endif
|
||||
|
||||
#endif /* __LINUX_LOCKDEP_H */
|
||||
|
||||
@ -625,13 +625,17 @@ typedef struct
|
||||
|
||||
int enum_pci_devices(void);
|
||||
|
||||
struct pci_device_id*
|
||||
find_pci_device(pci_dev_t* pdev, struct pci_device_id *idlist);
|
||||
const struct pci_device_id*
|
||||
find_pci_device(pci_dev_t* pdev, const struct pci_device_id *idlist);
|
||||
|
||||
#define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))
|
||||
|
||||
int pci_set_dma_mask(struct pci_dev *dev, u64 mask);
|
||||
|
||||
struct pci_dev *pci_get_bus_and_slot(unsigned int bus, unsigned int devfn);
|
||||
struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
|
||||
|
||||
void __iomem *pci_map_rom(struct pci_dev *pdev, size_t *size);
|
||||
|
||||
#define pci_name(x) "radeon"
|
||||
|
||||
|
||||
@ -663,6 +663,26 @@
|
||||
#define PCI_ATS_CTRL_STU(x) ((x) & 0x1f) /* Smallest Translation Unit */
|
||||
#define PCI_ATS_MIN_STU 12 /* shift of minimum STU block */
|
||||
|
||||
/* Page Request Interface */
|
||||
#define PCI_PRI_CAP 0x13 /* PRI capability ID */
|
||||
#define PCI_PRI_CONTROL_OFF 0x04 /* Offset of control register */
|
||||
#define PCI_PRI_STATUS_OFF 0x06 /* Offset of status register */
|
||||
#define PCI_PRI_ENABLE 0x0001 /* Enable mask */
|
||||
#define PCI_PRI_RESET 0x0002 /* Reset bit mask */
|
||||
#define PCI_PRI_STATUS_RF 0x0001 /* Request Failure */
|
||||
#define PCI_PRI_STATUS_UPRGI 0x0002 /* Unexpected PRG index */
|
||||
#define PCI_PRI_STATUS_STOPPED 0x0100 /* PRI Stopped */
|
||||
#define PCI_PRI_MAX_REQ_OFF 0x08 /* Cap offset for max reqs supported */
|
||||
#define PCI_PRI_ALLOC_REQ_OFF 0x0c /* Cap offset for max reqs allowed */
|
||||
|
||||
/* PASID capability */
|
||||
#define PCI_PASID_CAP 0x1b /* PASID capability ID */
|
||||
#define PCI_PASID_CAP_OFF 0x04 /* PASID feature register */
|
||||
#define PCI_PASID_CONTROL_OFF 0x06 /* PASID control register */
|
||||
#define PCI_PASID_ENABLE 0x01 /* Enable/Supported bit */
|
||||
#define PCI_PASID_EXEC 0x02 /* Exec permissions Enable/Supported */
|
||||
#define PCI_PASID_PRIV 0x04 /* Priviledge Mode Enable/Support */
|
||||
|
||||
/* Single Root I/O Virtualization */
|
||||
#define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */
|
||||
#define PCI_SRIOV_CAP_VFM 0x01 /* VF Migration Capable */
|
||||
|
||||
@ -40,6 +40,12 @@
|
||||
#define RED_INACTIVE 0x09F911029D74E35BULL /* when obj is inactive */
|
||||
#define RED_ACTIVE 0xD84156C5635688C0ULL /* when obj is active */
|
||||
|
||||
#ifdef CONFIG_PHYS_ADDR_T_64BIT
|
||||
#define MEMBLOCK_INACTIVE 0x3a84fb0144c9e71bULL
|
||||
#else
|
||||
#define MEMBLOCK_INACTIVE 0x44c9e71bUL
|
||||
#endif
|
||||
|
||||
#define SLUB_RED_INACTIVE 0xbb
|
||||
#define SLUB_RED_ACTIVE 0xcc
|
||||
|
||||
|
||||
@ -114,6 +114,7 @@ extern int memcmp(const void *,const void *,__kernel_size_t);
|
||||
#ifndef __HAVE_ARCH_MEMCHR
|
||||
extern void * memchr(const void *,int,__kernel_size_t);
|
||||
#endif
|
||||
void *memchr_inv(const void *s, int c, size_t n);
|
||||
|
||||
extern char *kstrdup(const char *s, gfp_t gfp);
|
||||
extern char *kstrndup(const char *s, size_t len, gfp_t gfp);
|
||||
|
||||
@ -246,7 +246,7 @@ struct ustat {
|
||||
|
||||
typedef unsigned char u8_t;
|
||||
typedef unsigned short u16_t;
|
||||
typedef unsigned int u32_t;
|
||||
typedef unsigned long u32_t;
|
||||
typedef unsigned long long u64_t;
|
||||
|
||||
typedef unsigned int addr_t;
|
||||
|
||||
144
drivers/include/linux/wait.h
Normal file
144
drivers/include/linux/wait.h
Normal file
@ -0,0 +1,144 @@
|
||||
#ifndef _LINUX_WAIT_H
|
||||
#define _LINUX_WAIT_H
|
||||
|
||||
typedef struct __wait_queue wait_queue_t;
|
||||
typedef struct __wait_queue_head wait_queue_head_t;
|
||||
|
||||
struct __wait_queue
|
||||
{
|
||||
struct list_head task_list;
|
||||
evhandle_t evnt;
|
||||
};
|
||||
|
||||
struct __wait_queue_head
|
||||
{
|
||||
spinlock_t lock;
|
||||
struct list_head task_list;
|
||||
};
|
||||
|
||||
static inline void __add_wait_queue(wait_queue_head_t *head, wait_queue_t *new)
|
||||
{
|
||||
list_add(&new->task_list, &head->task_list);
|
||||
}
|
||||
|
||||
|
||||
#define __wait_event(wq, condition) \
|
||||
do { \
|
||||
DEFINE_WAIT(__wait); \
|
||||
\
|
||||
for (;;) { \
|
||||
prepare_to_wait(&wq, &__wait, TASK_UNINTERRUPTIBLE); \
|
||||
if (condition) \
|
||||
break; \
|
||||
schedule(); \
|
||||
} \
|
||||
finish_wait(&wq, &__wait); \
|
||||
} while (0)
|
||||
|
||||
|
||||
#define wait_event(wq, condition) \
|
||||
do{ \
|
||||
wait_queue_t __wait = { \
|
||||
.task_list = LIST_HEAD_INIT(__wait.task_list), \
|
||||
.evnt = CreateEvent(NULL, MANUAL_DESTROY), \
|
||||
}; \
|
||||
u32 flags; \
|
||||
\
|
||||
spin_lock_irqsave(&wq.lock, flags); \
|
||||
if (list_empty(&__wait.task_list)) \
|
||||
__add_wait_queue(&wq, &__wait); \
|
||||
spin_unlock_irqrestore(&wq.lock, flags); \
|
||||
\
|
||||
for(;;){ \
|
||||
if (condition) \
|
||||
break; \
|
||||
WaitEvent(__wait.evnt); \
|
||||
}; \
|
||||
if (!list_empty_careful(&__wait.task_list)) { \
|
||||
spin_lock_irqsave(&wq.lock, flags); \
|
||||
list_del_init(&__wait.task_list); \
|
||||
spin_unlock_irqrestore(&wq.lock, flags); \
|
||||
}; \
|
||||
DestroyEvent(__wait.evnt); \
|
||||
} while (0)
|
||||
|
||||
|
||||
static inline
|
||||
void wake_up_all(wait_queue_head_t *q)
|
||||
{
|
||||
wait_queue_t *curr;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&q->lock, flags);
|
||||
list_for_each_entry(curr, &q->task_list, task_list)
|
||||
{
|
||||
kevent_t event;
|
||||
event.code = -1;
|
||||
RaiseEvent(curr->evnt, 0, &event);
|
||||
}
|
||||
spin_unlock_irqrestore(&q->lock, flags);
|
||||
}
|
||||
|
||||
|
||||
static inline void
|
||||
init_waitqueue_head(wait_queue_head_t *q)
|
||||
{
|
||||
spin_lock_init(&q->lock);
|
||||
INIT_LIST_HEAD(&q->task_list);
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* Workqueue flags and constants. For details, please refer to
|
||||
* Documentation/workqueue.txt.
|
||||
*/
|
||||
enum {
|
||||
WQ_NON_REENTRANT = 1 << 0, /* guarantee non-reentrance */
|
||||
WQ_UNBOUND = 1 << 1, /* not bound to any cpu */
|
||||
WQ_FREEZABLE = 1 << 2, /* freeze during suspend */
|
||||
WQ_MEM_RECLAIM = 1 << 3, /* may be used for memory reclaim */
|
||||
WQ_HIGHPRI = 1 << 4, /* high priority */
|
||||
WQ_CPU_INTENSIVE = 1 << 5, /* cpu instensive workqueue */
|
||||
|
||||
WQ_DRAINING = 1 << 6, /* internal: workqueue is draining */
|
||||
WQ_RESCUER = 1 << 7, /* internal: workqueue has rescuer */
|
||||
|
||||
WQ_MAX_ACTIVE = 512, /* I like 512, better ideas? */
|
||||
WQ_MAX_UNBOUND_PER_CPU = 4, /* 4 * #cpus for unbound wq */
|
||||
WQ_DFL_ACTIVE = WQ_MAX_ACTIVE / 2,
|
||||
};
|
||||
|
||||
struct work_struct;
|
||||
|
||||
struct workqueue_struct {
|
||||
spinlock_t lock;
|
||||
struct list_head worklist;
|
||||
};
|
||||
|
||||
typedef void (*work_func_t)(struct work_struct *work);
|
||||
|
||||
struct work_struct {
|
||||
struct list_head entry;
|
||||
struct workqueue_struct *data;
|
||||
work_func_t func;
|
||||
};
|
||||
|
||||
struct delayed_work {
|
||||
struct work_struct work;
|
||||
};
|
||||
|
||||
|
||||
struct workqueue_struct *alloc_workqueue_key(const char *fmt,
|
||||
unsigned int flags, int max_active);
|
||||
|
||||
int queue_delayed_work(struct workqueue_struct *wq,
|
||||
struct delayed_work *dwork, unsigned long delay);
|
||||
|
||||
#define INIT_DELAYED_WORK(_work, _func) \
|
||||
do { \
|
||||
INIT_LIST_HEAD(&(_work)->work.entry); \
|
||||
(_work)->work.func = _func; \
|
||||
} while (0)
|
||||
|
||||
#endif
|
||||
|
||||
@ -37,6 +37,9 @@ u32_t IMPORT GetTimerTicks(void)__asm__("GetTimerTicks");
|
||||
|
||||
addr_t STDCALL AllocPage(void)__asm__("AllocPage");
|
||||
addr_t STDCALL AllocPages(count_t count)__asm__("AllocPages");
|
||||
void IMPORT __attribute__((regparm(1)))
|
||||
FreePage(addr_t page)__asm__("FreePage");
|
||||
|
||||
|
||||
void* STDCALL CreateRingBuffer(size_t size, u32_t map)__asm__("CreateRingBuffer");
|
||||
|
||||
@ -51,6 +54,9 @@ void FASTCALL MutexUnlock(struct mutex*)__asm__("MutexUnlock");
|
||||
addr_t IMPORT GetStackBase(void)__asm__("GetStackBase");
|
||||
u32_t IMPORT GetPid(void)__asm__("GetPid");
|
||||
|
||||
u32 STDCALL TimerHs(u32 delay, u32 interval,
|
||||
void *fn, void *data)asm("TimerHs");
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
void STDCALL SetMouseData(int btn, int x, int y,
|
||||
@ -85,7 +91,6 @@ u32_t STDCALL PciWrite32(u32_t bus, u32_t devfn, u32_t reg,u32_t val)__asm__("Pc
|
||||
#define pciWriteLong(tag, reg, val) \
|
||||
PciWrite32(PCI_BUS_FROM_TAG(tag),PCI_DFN_FROM_TAG(tag),(reg),(val))
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
int dbg_open(char *path);
|
||||
@ -125,6 +130,14 @@ static inline void WaitEvent(evhandle_t evh)
|
||||
__asm__ __volatile__ ("":::"ebx","ecx","edx","esi","edi");
|
||||
};
|
||||
|
||||
static inline void DestroyEvent(evhandle_t evh)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"call *__imp__DestroyEvent"
|
||||
::"a"(evh.handle),"b"(evh.euid));
|
||||
__asm__ __volatile__ ("":::"ebx","ecx","edx","esi","edi");
|
||||
};
|
||||
|
||||
static inline u32_t GetEvent(kevent_t *ev)
|
||||
{
|
||||
u32_t handle;
|
||||
@ -175,7 +188,7 @@ static inline u32_t GetPgAddr(void *mem)
|
||||
|
||||
__asm__ __volatile__ (
|
||||
"call *__imp__GetPgAddr \n\t"
|
||||
:"=eax" (retval)
|
||||
:"=a" (retval)
|
||||
:"a" (mem) );
|
||||
return retval;
|
||||
};
|
||||
@ -216,7 +229,7 @@ static inline void usleep(u32_t delay)
|
||||
static inline void udelay(u32_t delay)
|
||||
{
|
||||
if(!delay) delay++;
|
||||
delay*= 500;
|
||||
delay*= 100;
|
||||
|
||||
while(delay--)
|
||||
{
|
||||
@ -298,7 +311,7 @@ static inline u32_t GetService(const char *name)
|
||||
(
|
||||
"pushl %%eax \n\t"
|
||||
"call *__imp__GetService"
|
||||
:"=eax" (handle)
|
||||
:"=a" (handle)
|
||||
:"a" (name)
|
||||
:"ebx","ecx","edx","esi", "edi"
|
||||
);
|
||||
@ -417,7 +430,7 @@ int drm_order(unsigned long size);
|
||||
|
||||
static inline void __iomem *ioremap(uint32_t offset, size_t size)
|
||||
{
|
||||
return (void __iomem*) MapIoMem(offset, size, 3);
|
||||
return (void __iomem*) MapIoMem(offset, size, PG_SW|PG_NOCACHE);
|
||||
}
|
||||
|
||||
static inline void iounmap(void *addr)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user