libdrm-2.4.66
git-svn-id: svn://kolibrios.org@6110 a494cfbc-eb01-0410-851d-a64ba20cac60
This commit is contained in:
Sergey Semyonov (Serge)
parent
ac054a24fe
commit
8a54b2712a
@ -38,6 +38,7 @@
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#include <stdint.h>
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#include <sys/types.h>
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typedef int8_t __s8;
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typedef uint8_t __u8;
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typedef int16_t __s16;
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@ -627,6 +628,13 @@ struct drm_get_cap {
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*/
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#define DRM_CLIENT_CAP_UNIVERSAL_PLANES 2
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/**
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* DRM_CLIENT_CAP_ATOMIC
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*
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* If set to 1, the DRM core will allow atomic modesetting requests.
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*/
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#define DRM_CLIENT_CAP_ATOMIC 3
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/** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */
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struct drm_set_client_cap {
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__u64 capability;
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@ -673,12 +681,13 @@ struct drm_prime_handle {
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#define SRV_MASK_UPDATE 45
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#define SRV_MASK_UPDATE_EX 46
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#define SRV_I915_GEM_PREAD 47
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#define SRV_I915_GEM_EXECBUFFER 48
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#include "drm_mode.h"
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#define DRM_IOCTL_BASE 'd'
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#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
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#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
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#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)
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#define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)
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#define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)
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@ -829,6 +838,7 @@ struct drm_event_vblank {
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#define DRM_CAP_PRIME 0x5
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#define DRM_CAP_TIMESTAMP_MONOTONIC 0x6
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#define DRM_CAP_ASYNC_PAGE_FLIP 0x7
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#define DRM_CAP_ADDFB2_MODIFIERS 0x10
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#define DRM_PRIME_CAP_IMPORT 0x1
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#define DRM_PRIME_CAP_EXPORT 0x2
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@ -127,4 +127,97 @@
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#define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */
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#define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */
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/*
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* Format Modifiers:
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*
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* Format modifiers describe, typically, a re-ordering or modification
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* of the data in a plane of an FB. This can be used to express tiled/
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* swizzled formats, or compression, or a combination of the two.
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*
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* The upper 8 bits of the format modifier are a vendor-id as assigned
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* below. The lower 56 bits are assigned as vendor sees fit.
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*/
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/* Vendor Ids: */
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#define DRM_FORMAT_MOD_NONE 0
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#define DRM_FORMAT_MOD_VENDOR_INTEL 0x01
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#define DRM_FORMAT_MOD_VENDOR_AMD 0x02
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#define DRM_FORMAT_MOD_VENDOR_NV 0x03
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#define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
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#define DRM_FORMAT_MOD_VENDOR_QCOM 0x05
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/* add more to the end as needed */
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#define fourcc_mod_code(vendor, val) \
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((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | (val & 0x00ffffffffffffffULL))
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/*
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* Format Modifier tokens:
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*
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* When adding a new token please document the layout with a code comment,
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* similar to the fourcc codes above. drm_fourcc.h is considered the
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* authoritative source for all of these.
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*/
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/* Intel framebuffer modifiers */
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/*
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* Intel X-tiling layout
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*
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* This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
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* in row-major layout. Within the tile bytes are laid out row-major, with
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* a platform-dependent stride. On top of that the memory can apply
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* platform-depending swizzling of some higher address bits into bit6.
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*
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* This format is highly platforms specific and not useful for cross-driver
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* sharing. It exists since on a given platform it does uniquely identify the
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* layout in a simple way for i915-specific userspace.
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*/
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#define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1)
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/*
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* Intel Y-tiling layout
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*
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* This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
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* in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
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* chunks column-major, with a platform-dependent height. On top of that the
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* memory can apply platform-depending swizzling of some higher address bits
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* into bit6.
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*
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* This format is highly platforms specific and not useful for cross-driver
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* sharing. It exists since on a given platform it does uniquely identify the
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* layout in a simple way for i915-specific userspace.
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*/
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#define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2)
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/*
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* Intel Yf-tiling layout
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*
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* This is a tiled layout using 4Kb tiles in row-major layout.
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* Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
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* are arranged in four groups (two wide, two high) with column-major layout.
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* Each group therefore consits out of four 256 byte units, which are also laid
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* out as 2x2 column-major.
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* 256 byte units are made out of four 64 byte blocks of pixels, producing
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* either a square block or a 2:1 unit.
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* 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width
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* in pixel depends on the pixel depth.
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*/
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#define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
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/*
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* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
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*
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* Macroblocks are laid in a Z-shape, and each pixel data is following the
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* standard NV12 style.
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* As for NV12, an image is the result of two frame buffers: one for Y,
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* one for the interleaved Cb/Cr components (1/2 the height of the Y buffer).
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* Alignment requirements are (for each buffer):
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* - multiple of 128 pixels for the width
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* - multiple of 32 pixels for the height
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*
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* For more information: see http://linuxtv.org/downloads/v4l-dvb-apis/re32.html
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*/
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#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
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#endif /* DRM_FOURCC_H */
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@ -42,20 +42,20 @@
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/* Video mode flags */
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/* bit compatible with the xorg definitions. */
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#define DRM_MODE_FLAG_PHSYNC (1<<0)
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#define DRM_MODE_FLAG_NHSYNC (1<<1)
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#define DRM_MODE_FLAG_PVSYNC (1<<2)
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#define DRM_MODE_FLAG_NVSYNC (1<<3)
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#define DRM_MODE_FLAG_INTERLACE (1<<4)
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#define DRM_MODE_FLAG_DBLSCAN (1<<5)
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#define DRM_MODE_FLAG_CSYNC (1<<6)
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#define DRM_MODE_FLAG_PCSYNC (1<<7)
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#define DRM_MODE_FLAG_NCSYNC (1<<8)
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#define DRM_MODE_FLAG_HSKEW (1<<9) /* hskew provided */
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#define DRM_MODE_FLAG_BCAST (1<<10)
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#define DRM_MODE_FLAG_PIXMUX (1<<11)
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#define DRM_MODE_FLAG_DBLCLK (1<<12)
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#define DRM_MODE_FLAG_CLKDIV2 (1<<13)
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#define DRM_MODE_FLAG_PHSYNC (1<<0)
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#define DRM_MODE_FLAG_NHSYNC (1<<1)
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#define DRM_MODE_FLAG_PVSYNC (1<<2)
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#define DRM_MODE_FLAG_NVSYNC (1<<3)
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#define DRM_MODE_FLAG_INTERLACE (1<<4)
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#define DRM_MODE_FLAG_DBLSCAN (1<<5)
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#define DRM_MODE_FLAG_CSYNC (1<<6)
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#define DRM_MODE_FLAG_PCSYNC (1<<7)
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#define DRM_MODE_FLAG_NCSYNC (1<<8)
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#define DRM_MODE_FLAG_HSKEW (1<<9) /* hskew provided */
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#define DRM_MODE_FLAG_BCAST (1<<10)
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#define DRM_MODE_FLAG_PIXMUX (1<<11)
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#define DRM_MODE_FLAG_DBLCLK (1<<12)
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#define DRM_MODE_FLAG_CLKDIV2 (1<<13)
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#define DRM_MODE_FLAG_3D_MASK (0x1f<<14)
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#define DRM_MODE_FLAG_3D_NONE (0<<14)
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#define DRM_MODE_FLAG_3D_FRAME_PACKING (1<<14)
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@ -173,6 +173,9 @@ struct drm_mode_get_plane_res {
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#define DRM_MODE_ENCODER_TMDS 2
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#define DRM_MODE_ENCODER_LVDS 3
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#define DRM_MODE_ENCODER_TVDAC 4
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#define DRM_MODE_ENCODER_VIRTUAL 5
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#define DRM_MODE_ENCODER_DSI 6
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#define DRM_MODE_ENCODER_DPMST 7
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struct drm_mode_get_encoder {
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__u32 encoder_id;
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@ -210,6 +213,8 @@ struct drm_mode_get_encoder {
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#define DRM_MODE_CONNECTOR_HDMIB 12
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#define DRM_MODE_CONNECTOR_TV 13
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#define DRM_MODE_CONNECTOR_eDP 14
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#define DRM_MODE_CONNECTOR_VIRTUAL 15
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#define DRM_MODE_CONNECTOR_DSI 16
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struct drm_mode_get_connector {
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@ -239,6 +244,21 @@ struct drm_mode_get_connector {
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#define DRM_MODE_PROP_BLOB (1<<4)
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#define DRM_MODE_PROP_BITMASK (1<<5) /* bitmask of enumerated types */
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/* non-extended types: legacy bitmask, one bit per type: */
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#define DRM_MODE_PROP_LEGACY_TYPE ( \
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DRM_MODE_PROP_RANGE | \
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DRM_MODE_PROP_ENUM | \
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DRM_MODE_PROP_BLOB | \
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DRM_MODE_PROP_BITMASK)
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/* extended-types: rather than continue to consume a bit per type,
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* grab a chunk of the bits to use as integer type id.
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*/
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#define DRM_MODE_PROP_EXTENDED_TYPE 0x0000ffc0
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#define DRM_MODE_PROP_TYPE(n) ((n) << 6)
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#define DRM_MODE_PROP_OBJECT DRM_MODE_PROP_TYPE(1)
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#define DRM_MODE_PROP_SIGNED_RANGE DRM_MODE_PROP_TYPE(2)
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struct drm_mode_property_enum {
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__u64 value;
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char name[DRM_PROP_NAME_LEN];
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@ -302,7 +322,8 @@ struct drm_mode_fb_cmd {
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__u32 handle;
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};
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#define DRM_MODE_FB_INTERLACED (1<<0) /* for interlaced framebuffers */
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#define DRM_MODE_FB_INTERLACED (1<<0) /* for interlaced framebuffers */
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#define DRM_MODE_FB_MODIFIERS (1<<1) /* enables ->modifer[] */
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struct drm_mode_fb_cmd2 {
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__u32 fb_id;
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@ -323,10 +344,18 @@ struct drm_mode_fb_cmd2 {
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* So it would consist of Y as offset[0] and UV as
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* offset[1]. Note that offset[0] will generally
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* be 0.
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*
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* To accommodate tiled, compressed, etc formats, a per-plane
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* modifier can be specified. The default value of zero
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* indicates "native" format as specified by the fourcc.
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* Vendor specific modifier token. This allows, for example,
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* different tiling/swizzling pattern on different planes.
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* See discussion above of DRM_FORMAT_MOD_xxx.
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*/
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__u32 handles[4];
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__u32 pitches[4]; /* pitch for each plane */
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__u32 offsets[4]; /* offset of each plane */
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__u64 modifier[4]; /* ie, tiling, compressed (per plane) */
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};
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#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01
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@ -487,4 +516,41 @@ struct drm_mode_destroy_dumb {
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__u32 handle;
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};
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/* page-flip flags are valid, plus: */
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#define DRM_MODE_ATOMIC_TEST_ONLY 0x0100
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#define DRM_MODE_ATOMIC_NONBLOCK 0x0200
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#define DRM_MODE_ATOMIC_ALLOW_MODESET 0x0400
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struct drm_mode_atomic {
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__u32 flags;
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__u32 count_objs;
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__u64 objs_ptr;
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__u64 count_props_ptr;
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__u64 props_ptr;
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__u64 prop_values_ptr;
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__u64 reserved;
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__u64 user_data;
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};
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/**
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* Create a new 'blob' data property, copying length bytes from data pointer,
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* and returning new blob ID.
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*/
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struct drm_mode_create_blob {
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/** Pointer to data to copy. */
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__u64 data;
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/** Length of data to copy. */
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__u32 length;
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/** Return: new property ID. */
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__u32 blob_id;
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};
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/**
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* Destroy a user-created blob property.
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*/
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struct drm_mode_destroy_blob {
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__u32 blob_id;
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};
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#endif
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@ -165,58 +165,62 @@ typedef struct _drm_i915_sarea {
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/* Flags for perf_boxes
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*/
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#define I915_BOX_RING_EMPTY 0x1
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#define I915_BOX_FLIP 0x2
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#define I915_BOX_WAIT 0x4
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#define I915_BOX_TEXTURE_LOAD 0x8
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#define I915_BOX_LOST_CONTEXT 0x10
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#define I915_BOX_RING_EMPTY 0x1
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#define I915_BOX_FLIP 0x2
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#define I915_BOX_WAIT 0x4
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#define I915_BOX_TEXTURE_LOAD 0x8
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#define I915_BOX_LOST_CONTEXT 0x10
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/* I915 specific ioctls
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* The device specific ioctl range is 0x40 to 0x79.
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/*
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* i915 specific ioctls.
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*
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* The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie
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* [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset
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* against DRM_COMMAND_BASE and should be between [0x0, 0x60).
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*/
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#define DRM_I915_INIT 0x00
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#define DRM_I915_FLUSH 0x01
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#define DRM_I915_FLIP 0x02
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#define DRM_I915_BATCHBUFFER 0x03
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#define DRM_I915_IRQ_EMIT 0x04
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#define DRM_I915_IRQ_WAIT 0x05
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#define DRM_I915_GETPARAM 0x06
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#define DRM_I915_SETPARAM 0x07
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#define DRM_I915_ALLOC 0x08
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#define DRM_I915_FREE 0x09
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#define DRM_I915_INIT_HEAP 0x0a
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#define DRM_I915_CMDBUFFER 0x0b
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#define DRM_I915_DESTROY_HEAP 0x0c
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#define DRM_I915_INIT 0x00
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#define DRM_I915_FLUSH 0x01
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#define DRM_I915_FLIP 0x02
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#define DRM_I915_BATCHBUFFER 0x03
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#define DRM_I915_IRQ_EMIT 0x04
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#define DRM_I915_IRQ_WAIT 0x05
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#define DRM_I915_GETPARAM 0x06
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#define DRM_I915_SETPARAM 0x07
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#define DRM_I915_ALLOC 0x08
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#define DRM_I915_FREE 0x09
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#define DRM_I915_INIT_HEAP 0x0a
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#define DRM_I915_CMDBUFFER 0x0b
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#define DRM_I915_DESTROY_HEAP 0x0c
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#define DRM_I915_SET_VBLANK_PIPE 0x0d
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#define DRM_I915_GET_VBLANK_PIPE 0x0e
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#define DRM_I915_VBLANK_SWAP 0x0f
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#define DRM_I915_HWS_ADDR 0x11
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#define DRM_I915_GEM_INIT 0x13
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#define DRM_I915_GEM_EXECBUFFER 0x14
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#define DRM_I915_GEM_PIN 0x15
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#define DRM_I915_GEM_UNPIN 0x16
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#define DRM_I915_GEM_BUSY 0x17
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#define DRM_I915_GEM_THROTTLE 0x18
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#define DRM_I915_GEM_ENTERVT 0x19
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#define DRM_I915_GEM_LEAVEVT 0x1a
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#define DRM_I915_GEM_CREATE 0x1b
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#define DRM_I915_GEM_PREAD 0x1c
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#define DRM_I915_GEM_PWRITE 0x1d
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#define DRM_I915_GEM_MMAP 0x1e
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#define DRM_I915_GEM_SET_DOMAIN 0x1f
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#define DRM_I915_GEM_SW_FINISH 0x20
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#define DRM_I915_GEM_SET_TILING 0x21
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#define DRM_I915_GEM_GET_TILING 0x22
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#define DRM_I915_GEM_GET_APERTURE 0x23
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#define DRM_I915_GEM_MMAP_GTT 0x24
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#define DRM_I915_VBLANK_SWAP 0x0f
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#define DRM_I915_HWS_ADDR 0x11
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#define DRM_I915_GEM_INIT 0x13
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#define DRM_I915_GEM_EXECBUFFER 0x14
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#define DRM_I915_GEM_PIN 0x15
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#define DRM_I915_GEM_UNPIN 0x16
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#define DRM_I915_GEM_BUSY 0x17
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#define DRM_I915_GEM_THROTTLE 0x18
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#define DRM_I915_GEM_ENTERVT 0x19
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#define DRM_I915_GEM_LEAVEVT 0x1a
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#define DRM_I915_GEM_CREATE 0x1b
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#define DRM_I915_GEM_PREAD 0x1c
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#define DRM_I915_GEM_PWRITE 0x1d
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#define DRM_I915_GEM_MMAP 0x1e
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#define DRM_I915_GEM_SET_DOMAIN 0x1f
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#define DRM_I915_GEM_SW_FINISH 0x20
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#define DRM_I915_GEM_SET_TILING 0x21
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#define DRM_I915_GEM_GET_TILING 0x22
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#define DRM_I915_GEM_GET_APERTURE 0x23
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#define DRM_I915_GEM_MMAP_GTT 0x24
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#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
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#define DRM_I915_GEM_MADVISE 0x26
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#define DRM_I915_GEM_MADVISE 0x26
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#define DRM_I915_OVERLAY_PUT_IMAGE 0x27
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#define DRM_I915_OVERLAY_ATTRS 0x28
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#define DRM_I915_OVERLAY_ATTRS 0x28
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#define DRM_I915_GEM_EXECBUFFER2 0x29
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#define DRM_I915_GET_SPRITE_COLORKEY 0x2a
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#define DRM_I915_SET_SPRITE_COLORKEY 0x2b
|
||||
#define DRM_I915_GEM_WAIT 0x2c
|
||||
#define DRM_I915_GEM_WAIT 0x2c
|
||||
#define DRM_I915_GEM_CONTEXT_CREATE 0x2d
|
||||
#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e
|
||||
#define DRM_I915_GEM_SET_CACHING 0x2f
|
||||
@ -243,7 +247,7 @@ typedef struct _drm_i915_sarea {
|
||||
#define DRM_IOCTL_I915_VBLANK_SWAP
|
||||
#define DRM_IOCTL_I915_HWS_ADDR
|
||||
#define DRM_IOCTL_I915_GEM_INIT
|
||||
#define DRM_IOCTL_I915_GEM_EXECBUFFER
|
||||
#define DRM_IOCTL_I915_GEM_EXECBUFFER SRV_I915_GEM_EXECBUFFER
|
||||
#define DRM_IOCTL_I915_GEM_EXECBUFFER2 SRV_I915_GEM_EXECBUFFER2
|
||||
#define DRM_IOCTL_I915_GEM_PIN SRV_I915_GEM_PIN
|
||||
#define DRM_IOCTL_I915_GEM_UNPIN SRV_I915_GEM_UNPIN
|
||||
@ -254,7 +258,7 @@ typedef struct _drm_i915_sarea {
|
||||
#define DRM_IOCTL_I915_GEM_ENTERVT
|
||||
#define DRM_IOCTL_I915_GEM_LEAVEVT
|
||||
#define DRM_IOCTL_I915_GEM_CREATE SRV_I915_GEM_CREATE
|
||||
#define DRM_IOCTL_I915_GEM_PREAD
|
||||
#define DRM_IOCTL_I915_GEM_PREAD SRV_I915_GEM_PREAD
|
||||
#define DRM_IOCTL_I915_GEM_PWRITE SRV_I915_GEM_PWRITE
|
||||
#define DRM_IOCTL_I915_GEM_MMAP SRV_I915_GEM_MMAP
|
||||
#define DRM_IOCTL_I915_GEM_MMAP_GTT SRV_I915_GEM_MMAP_GTT
|
||||
@ -332,7 +336,7 @@ typedef struct drm_i915_irq_wait {
|
||||
#define I915_PARAM_HAS_WAIT_TIMEOUT 19
|
||||
#define I915_PARAM_HAS_SEMAPHORES 20
|
||||
#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21
|
||||
#define I915_PARAM_HAS_VEBOX 22
|
||||
#define I915_PARAM_HAS_VEBOX 22
|
||||
#define I915_PARAM_HAS_SECURE_BATCHES 23
|
||||
#define I915_PARAM_HAS_PINNED_BATCHES 24
|
||||
#define I915_PARAM_HAS_EXEC_NO_RELOC 25
|
||||
@ -340,9 +344,21 @@ typedef struct drm_i915_irq_wait {
|
||||
#define I915_PARAM_HAS_WT 27
|
||||
#define I915_PARAM_CMD_PARSER_VERSION 28
|
||||
#define I915_PARAM_HAS_COHERENT_PHYS_GTT 29
|
||||
#define I915_PARAM_MMAP_VERSION 30
|
||||
#define I915_PARAM_HAS_BSD2 31
|
||||
#define I915_PARAM_REVISION 32
|
||||
#define I915_PARAM_SUBSLICE_TOTAL 33
|
||||
#define I915_PARAM_EU_TOTAL 34
|
||||
#define I915_PARAM_HAS_GPU_RESET 35
|
||||
#define I915_PARAM_HAS_RESOURCE_STREAMER 36
|
||||
#define I915_PARAM_HAS_EXEC_SOFTPIN 37
|
||||
|
||||
typedef struct drm_i915_getparam {
|
||||
int param;
|
||||
/*
|
||||
* WARNING: Using pointers instead of fixed-size u64 means we need to write
|
||||
* compat32 code. Don't repeat this mistake.
|
||||
*/
|
||||
int *value;
|
||||
} drm_i915_getparam_t;
|
||||
|
||||
@ -487,6 +503,14 @@ struct drm_i915_gem_mmap {
|
||||
* This is a fixed-size type for 32/64 compatibility.
|
||||
*/
|
||||
__u64 addr_ptr;
|
||||
|
||||
/**
|
||||
* Flags for extended behaviour.
|
||||
*
|
||||
* Added in version 2.
|
||||
*/
|
||||
__u64 flags;
|
||||
#define I915_MMAP_WC 0x1
|
||||
};
|
||||
|
||||
struct drm_i915_gem_mmap_gtt {
|
||||
@ -654,15 +678,21 @@ struct drm_i915_gem_exec_object2 {
|
||||
__u64 alignment;
|
||||
|
||||
/**
|
||||
* Returned value of the updated offset of the object, for future
|
||||
* presumed_offset writes.
|
||||
* When the EXEC_OBJECT_PINNED flag is specified this is populated by
|
||||
* the user with the GTT offset at which this object will be pinned.
|
||||
* When the I915_EXEC_NO_RELOC flag is specified this must contain the
|
||||
* presumed_offset of the object.
|
||||
* During execbuffer2 the kernel populates it with the value of the
|
||||
* current GTT offset of the object, for future presumed_offset writes.
|
||||
*/
|
||||
__u64 offset;
|
||||
|
||||
#define EXEC_OBJECT_NEEDS_FENCE (1<<0)
|
||||
#define EXEC_OBJECT_NEEDS_GTT (1<<1)
|
||||
#define EXEC_OBJECT_WRITE (1<<2)
|
||||
#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_WRITE<<1)
|
||||
#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3)
|
||||
#define EXEC_OBJECT_PINNED (1<<4)
|
||||
#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_PINNED<<1)
|
||||
__u64 flags;
|
||||
|
||||
__u64 rsvd1;
|
||||
@ -736,7 +766,18 @@ struct drm_i915_gem_execbuffer2 {
|
||||
*/
|
||||
#define I915_EXEC_HANDLE_LUT (1<<12)
|
||||
|
||||
#define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_HANDLE_LUT<<1)
|
||||
/** Used for switching BSD rings on the platforms with two BSD rings */
|
||||
#define I915_EXEC_BSD_MASK (3<<13)
|
||||
#define I915_EXEC_BSD_DEFAULT (0<<13) /* default ping-pong mode */
|
||||
#define I915_EXEC_BSD_RING1 (1<<13)
|
||||
#define I915_EXEC_BSD_RING2 (2<<13)
|
||||
|
||||
/** Tell the kernel that the batchbuffer is processed by
|
||||
* the resource streamer.
|
||||
*/
|
||||
#define I915_EXEC_RESOURCE_STREAMER (1<<15)
|
||||
|
||||
#define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_RESOURCE_STREAMER<<1)
|
||||
|
||||
#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
|
||||
#define i915_execbuffer2_set_context_id(eb2, context) \
|
||||
@ -972,6 +1013,7 @@ struct drm_intel_overlay_put_image {
|
||||
/* flags */
|
||||
#define I915_OVERLAY_UPDATE_ATTRS (1<<0)
|
||||
#define I915_OVERLAY_UPDATE_GAMMA (1<<1)
|
||||
#define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2)
|
||||
struct drm_intel_overlay_attrs {
|
||||
__u32 flags;
|
||||
__u32 color_key;
|
||||
@ -1038,9 +1080,23 @@ struct drm_i915_gem_context_destroy {
|
||||
};
|
||||
|
||||
struct drm_i915_reg_read {
|
||||
/*
|
||||
* Register offset.
|
||||
* For 64bit wide registers where the upper 32bits don't immediately
|
||||
* follow the lower 32bits, the offset of the lower 32bits must
|
||||
* be specified
|
||||
*/
|
||||
__u64 offset;
|
||||
__u64 val; /* Return value */
|
||||
};
|
||||
/* Known registers:
|
||||
*
|
||||
* Render engine timestamp - 0x2358 + 64bit - gen7+
|
||||
* - Note this register returns an invalid value if using the default
|
||||
* single instruction 8byte read, in order to workaround that use
|
||||
* offset (0x2538 | 1) instead.
|
||||
*
|
||||
*/
|
||||
|
||||
struct drm_i915_reset_stats {
|
||||
__u32 ctx_id;
|
||||
@ -1065,13 +1121,23 @@ struct drm_i915_gem_userptr {
|
||||
#define I915_USERPTR_READ_ONLY 0x1
|
||||
#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
|
||||
/**
|
||||
* Returned handle for the object.
|
||||
*
|
||||
* Object handles are nonzero.
|
||||
*/
|
||||
* Returned handle for the object.
|
||||
*
|
||||
* Object handles are nonzero.
|
||||
*/
|
||||
__u32 handle;
|
||||
};
|
||||
|
||||
struct drm_i915_gem_context_param {
|
||||
__u32 ctx_id;
|
||||
__u32 size;
|
||||
__u64 param;
|
||||
#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
|
||||
#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2
|
||||
#define I915_CONTEXT_PARAM_GTT_SIZE 0x3
|
||||
__u64 value;
|
||||
};
|
||||
|
||||
struct drm_i915_mask {
|
||||
__u32 handle;
|
||||
__u32 width;
|
||||
@ -1102,4 +1168,4 @@ struct drm_i915_mask_update {
|
||||
__u32 forced;
|
||||
};
|
||||
|
||||
#endif /* _I915_DRM_H_ */
|
||||
#endif /* _I915_DRM_H_ */
|
||||
|
||||
@ -37,6 +37,7 @@
|
||||
#include <drm.h>
|
||||
#include <i915_drm.h>
|
||||
//#include <pciaccess.h>
|
||||
#include "libdrm_macros.h"
|
||||
#include "intel_bufmgr.h"
|
||||
#include "intel_bufmgr_priv.h"
|
||||
#include "xf86drm.h"
|
||||
@ -46,20 +47,34 @@
|
||||
* Convenience functions for buffer management methods.
|
||||
*/
|
||||
|
||||
drm_intel_bo *drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name,
|
||||
unsigned long size, unsigned int alignment)
|
||||
drm_intel_bo *
|
||||
drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name,
|
||||
unsigned long size, unsigned int alignment)
|
||||
{
|
||||
return bufmgr->bo_alloc(bufmgr, name, size, alignment);
|
||||
}
|
||||
|
||||
drm_intel_bo *drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
|
||||
const char *name,
|
||||
unsigned long size,
|
||||
unsigned int alignment)
|
||||
drm_intel_bo *
|
||||
drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr, const char *name,
|
||||
unsigned long size, unsigned int alignment)
|
||||
{
|
||||
return bufmgr->bo_alloc_for_render(bufmgr, name, size, alignment);
|
||||
}
|
||||
|
||||
drm_intel_bo *
|
||||
drm_intel_bo_alloc_userptr(drm_intel_bufmgr *bufmgr,
|
||||
const char *name, void *addr,
|
||||
uint32_t tiling_mode,
|
||||
uint32_t stride,
|
||||
unsigned long size,
|
||||
unsigned long flags)
|
||||
{
|
||||
if (bufmgr->bo_alloc_userptr)
|
||||
return bufmgr->bo_alloc_userptr(bufmgr, name, addr, tiling_mode,
|
||||
stride, size, flags);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
drm_intel_bo *
|
||||
drm_intel_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
|
||||
int x, int y, int cpp, uint32_t *tiling_mode,
|
||||
@ -69,12 +84,14 @@ drm_intel_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
|
||||
tiling_mode, pitch, flags);
|
||||
}
|
||||
|
||||
void drm_intel_bo_reference(drm_intel_bo *bo)
|
||||
void
|
||||
drm_intel_bo_reference(drm_intel_bo *bo)
|
||||
{
|
||||
bo->bufmgr->bo_reference(bo);
|
||||
}
|
||||
|
||||
void drm_intel_bo_unreference(drm_intel_bo *bo)
|
||||
void
|
||||
drm_intel_bo_unreference(drm_intel_bo *bo)
|
||||
{
|
||||
if (bo == NULL)
|
||||
return;
|
||||
@ -82,12 +99,14 @@ void drm_intel_bo_unreference(drm_intel_bo *bo)
|
||||
bo->bufmgr->bo_unreference(bo);
|
||||
}
|
||||
|
||||
int drm_intel_bo_map(drm_intel_bo *buf, int write_enable)
|
||||
int
|
||||
drm_intel_bo_map(drm_intel_bo *buf, int write_enable)
|
||||
{
|
||||
return buf->bufmgr->bo_map(buf, write_enable);
|
||||
}
|
||||
|
||||
int drm_intel_bo_unmap(drm_intel_bo *buf)
|
||||
int
|
||||
drm_intel_bo_unmap(drm_intel_bo *buf)
|
||||
{
|
||||
return buf->bufmgr->bo_unmap(buf);
|
||||
}
|
||||
@ -104,8 +123,8 @@ drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
|
||||
unsigned long size, void *data)
|
||||
{
|
||||
int ret;
|
||||
// if (bo->bufmgr->bo_get_subdata)
|
||||
// return bo->bufmgr->bo_get_subdata(bo, offset, size, data);
|
||||
if (bo->bufmgr->bo_get_subdata)
|
||||
return bo->bufmgr->bo_get_subdata(bo, offset, size, data);
|
||||
|
||||
if (size == 0 || data == NULL)
|
||||
return 0;
|
||||
@ -118,12 +137,14 @@ drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
|
||||
return 0;
|
||||
}
|
||||
|
||||
void drm_intel_bo_wait_rendering(drm_intel_bo *bo)
|
||||
void
|
||||
drm_intel_bo_wait_rendering(drm_intel_bo *bo)
|
||||
{
|
||||
bo->bufmgr->bo_wait_rendering(bo);
|
||||
}
|
||||
|
||||
void drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr)
|
||||
void
|
||||
drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr)
|
||||
{
|
||||
bufmgr->destroy(bufmgr);
|
||||
}
|
||||
@ -155,17 +176,20 @@ drm_intel_bo_mrb_exec(drm_intel_bo *bo, int used,
|
||||
}
|
||||
}
|
||||
|
||||
void drm_intel_bufmgr_set_debug(drm_intel_bufmgr *bufmgr, int enable_debug)
|
||||
void
|
||||
drm_intel_bufmgr_set_debug(drm_intel_bufmgr *bufmgr, int enable_debug)
|
||||
{
|
||||
bufmgr->debug = enable_debug;
|
||||
}
|
||||
|
||||
int drm_intel_bufmgr_check_aperture_space(drm_intel_bo ** bo_array, int count)
|
||||
int
|
||||
drm_intel_bufmgr_check_aperture_space(drm_intel_bo ** bo_array, int count)
|
||||
{
|
||||
return bo_array[0]->bufmgr->check_aperture_space(bo_array, count);
|
||||
}
|
||||
|
||||
int drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name)
|
||||
int
|
||||
drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name)
|
||||
{
|
||||
if (bo->bufmgr->bo_flink)
|
||||
return bo->bufmgr->bo_flink(bo, name);
|
||||
@ -195,7 +219,8 @@ drm_intel_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
|
||||
}
|
||||
|
||||
|
||||
int drm_intel_bo_pin(drm_intel_bo *bo, uint32_t alignment)
|
||||
int
|
||||
drm_intel_bo_pin(drm_intel_bo *bo, uint32_t alignment)
|
||||
{
|
||||
if (bo->bufmgr->bo_pin)
|
||||
return bo->bufmgr->bo_pin(bo, alignment);
|
||||
@ -203,7 +228,8 @@ int drm_intel_bo_pin(drm_intel_bo *bo, uint32_t alignment)
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
int drm_intel_bo_unpin(drm_intel_bo *bo)
|
||||
int
|
||||
drm_intel_bo_unpin(drm_intel_bo *bo)
|
||||
{
|
||||
if (bo->bufmgr->bo_unpin)
|
||||
return bo->bufmgr->bo_unpin(bo);
|
||||
@ -211,8 +237,9 @@ int drm_intel_bo_unpin(drm_intel_bo *bo)
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
int drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
|
||||
uint32_t stride)
|
||||
int
|
||||
drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
|
||||
uint32_t stride)
|
||||
{
|
||||
if (bo->bufmgr->bo_set_tiling)
|
||||
return bo->bufmgr->bo_set_tiling(bo, tiling_mode, stride);
|
||||
@ -221,8 +248,9 @@ int drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
|
||||
return 0;
|
||||
}
|
||||
|
||||
int drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
|
||||
uint32_t * swizzle_mode)
|
||||
int
|
||||
drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
|
||||
uint32_t * swizzle_mode)
|
||||
{
|
||||
if (bo->bufmgr->bo_get_tiling)
|
||||
return bo->bufmgr->bo_get_tiling(bo, tiling_mode, swizzle_mode);
|
||||
@ -232,35 +260,60 @@ int drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
|
||||
return 0;
|
||||
}
|
||||
|
||||
int drm_intel_bo_disable_reuse(drm_intel_bo *bo)
|
||||
int
|
||||
drm_intel_bo_set_softpin_offset(drm_intel_bo *bo, uint64_t offset)
|
||||
{
|
||||
if (bo->bufmgr->bo_set_softpin_offset)
|
||||
return bo->bufmgr->bo_set_softpin_offset(bo, offset);
|
||||
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
int
|
||||
drm_intel_bo_disable_reuse(drm_intel_bo *bo)
|
||||
{
|
||||
if (bo->bufmgr->bo_disable_reuse)
|
||||
return bo->bufmgr->bo_disable_reuse(bo);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int drm_intel_bo_is_reusable(drm_intel_bo *bo)
|
||||
int
|
||||
drm_intel_bo_is_reusable(drm_intel_bo *bo)
|
||||
{
|
||||
if (bo->bufmgr->bo_is_reusable)
|
||||
return bo->bufmgr->bo_is_reusable(bo);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int drm_intel_bo_busy(drm_intel_bo *bo)
|
||||
int
|
||||
drm_intel_bo_busy(drm_intel_bo *bo)
|
||||
{
|
||||
if (bo->bufmgr->bo_busy)
|
||||
return bo->bufmgr->bo_busy(bo);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int drm_intel_bo_madvise(drm_intel_bo *bo, int madv)
|
||||
int
|
||||
drm_intel_bo_madvise(drm_intel_bo *bo, int madv)
|
||||
{
|
||||
if (bo->bufmgr->bo_madvise)
|
||||
return bo->bufmgr->bo_madvise(bo, madv);
|
||||
return -1;
|
||||
}
|
||||
|
||||
int drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
|
||||
int
|
||||
drm_intel_bo_use_48b_address_range(drm_intel_bo *bo, uint32_t enable)
|
||||
{
|
||||
if (bo->bufmgr->bo_use_48b_address_range) {
|
||||
bo->bufmgr->bo_use_48b_address_range(bo, enable);
|
||||
return 0;
|
||||
}
|
||||
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
int
|
||||
drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
|
||||
{
|
||||
return bo->bufmgr->bo_references(bo, target_bo);
|
||||
}
|
||||
@ -295,9 +348,8 @@ err:
|
||||
}
|
||||
#endif
|
||||
|
||||
int drm_intel_get_aperture_sizes(int fd,
|
||||
size_t *mappable,
|
||||
size_t *total)
|
||||
int
|
||||
drm_intel_get_aperture_sizes(int fd, size_t *mappable, size_t *total)
|
||||
{
|
||||
|
||||
struct drm_i915_gem_get_aperture aperture;
|
||||
|
||||
@ -38,6 +38,10 @@
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
struct drm_clip_rect;
|
||||
|
||||
typedef struct _drm_intel_bufmgr drm_intel_bufmgr;
|
||||
@ -113,6 +117,11 @@ drm_intel_bo *drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
|
||||
const char *name,
|
||||
unsigned long size,
|
||||
unsigned int alignment);
|
||||
drm_intel_bo *drm_intel_bo_alloc_userptr(drm_intel_bufmgr *bufmgr,
|
||||
const char *name,
|
||||
void *addr, uint32_t tiling_mode,
|
||||
uint32_t stride, unsigned long size,
|
||||
unsigned long flags);
|
||||
drm_intel_bo *drm_intel_bo_alloc_tiled(drm_intel_bufmgr *bufmgr,
|
||||
const char *name,
|
||||
int x, int y, int cpp,
|
||||
@ -155,6 +164,8 @@ int drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
|
||||
int drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name);
|
||||
int drm_intel_bo_busy(drm_intel_bo *bo);
|
||||
int drm_intel_bo_madvise(drm_intel_bo *bo, int madv);
|
||||
int drm_intel_bo_use_48b_address_range(drm_intel_bo *bo, uint32_t enable);
|
||||
int drm_intel_bo_set_softpin_offset(drm_intel_bo *bo, uint64_t offset);
|
||||
|
||||
int drm_intel_bo_disable_reuse(drm_intel_bo *bo);
|
||||
int drm_intel_bo_is_reusable(drm_intel_bo *bo);
|
||||
@ -263,6 +274,9 @@ int drm_intel_get_reset_stats(drm_intel_context *ctx,
|
||||
uint32_t *active,
|
||||
uint32_t *pending);
|
||||
|
||||
int drm_intel_get_subslice_total(int fd, unsigned int *subslice_total);
|
||||
int drm_intel_get_eu_total(int fd, unsigned int *eu_total);
|
||||
|
||||
/** @{ Compatibility defines to keep old code building despite the symbol rename
|
||||
* from dri_* to drm_intel_*
|
||||
*/
|
||||
@ -304,4 +318,8 @@ int drm_intel_get_reset_stats(drm_intel_context *ctx,
|
||||
|
||||
/** @{ */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* INTEL_BUFMGR_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -61,6 +61,18 @@ struct _drm_intel_bufmgr {
|
||||
unsigned long size,
|
||||
unsigned int alignment);
|
||||
|
||||
/**
|
||||
* Allocate a buffer object from an existing user accessible
|
||||
* address malloc'd with the provided size.
|
||||
* Alignment is used when mapping to the gtt.
|
||||
* Flags may be I915_VMAP_READ_ONLY or I915_USERPTR_UNSYNCHRONIZED
|
||||
*/
|
||||
drm_intel_bo *(*bo_alloc_userptr)(drm_intel_bufmgr *bufmgr,
|
||||
const char *name, void *addr,
|
||||
uint32_t tiling_mode, uint32_t stride,
|
||||
unsigned long size,
|
||||
unsigned long flags);
|
||||
|
||||
/**
|
||||
* Allocate a tiled buffer object.
|
||||
*
|
||||
@ -122,8 +134,8 @@ struct _drm_intel_bufmgr {
|
||||
* This is an optional function, if missing,
|
||||
* drm_intel_bo will map/memcpy/unmap.
|
||||
*/
|
||||
// int (*bo_get_subdata) (drm_intel_bo *bo, unsigned long offset,
|
||||
// unsigned long size, void *data);
|
||||
int (*bo_get_subdata) (drm_intel_bo *bo, unsigned long offset,
|
||||
unsigned long size, void *data);
|
||||
|
||||
/**
|
||||
* Waits for rendering to an object by the GPU to have completed.
|
||||
@ -139,6 +151,20 @@ struct _drm_intel_bufmgr {
|
||||
*/
|
||||
void (*destroy) (drm_intel_bufmgr *bufmgr);
|
||||
|
||||
/**
|
||||
* Indicate if the buffer can be placed anywhere in the full ppgtt
|
||||
* address range (2^48).
|
||||
*
|
||||
* Any resource used with flat/heapless (0x00000000-0xfffff000)
|
||||
* General State Heap (GSH) or Intructions State Heap (ISH) must
|
||||
* be in a 32-bit range. 48-bit range will only be used when explicitly
|
||||
* requested.
|
||||
*
|
||||
* \param bo Buffer to set the use_48b_address_range flag.
|
||||
* \param enable The flag value.
|
||||
*/
|
||||
void (*bo_use_48b_address_range) (drm_intel_bo *bo, uint32_t enable);
|
||||
|
||||
/**
|
||||
* Add relocation entry in reloc_buf, which will be updated with the
|
||||
* target buffer's real offset on on command submission.
|
||||
@ -214,6 +240,13 @@ struct _drm_intel_bufmgr {
|
||||
int (*bo_get_tiling) (drm_intel_bo *bo, uint32_t * tiling_mode,
|
||||
uint32_t * swizzle_mode);
|
||||
|
||||
/**
|
||||
* Set the offset at which this buffer will be softpinned
|
||||
* \param bo Buffer to set the softpin offset for
|
||||
* \param offset Softpin offset
|
||||
*/
|
||||
int (*bo_set_softpin_offset) (drm_intel_bo *bo, uint64_t offset);
|
||||
|
||||
/**
|
||||
* Create a visible name for a buffer which can be used by other apps
|
||||
*
|
||||
|
||||
@ -70,8 +70,8 @@
|
||||
#define PCI_CHIP_G45_G 0x2E22
|
||||
#define PCI_CHIP_G41_G 0x2E32
|
||||
|
||||
#define PCI_CHIP_ILD_G 0x0042
|
||||
#define PCI_CHIP_ILM_G 0x0046
|
||||
#define PCI_CHIP_ILD_G 0x0042
|
||||
#define PCI_CHIP_ILM_G 0x0046
|
||||
|
||||
#define PCI_CHIP_SANDYBRIDGE_GT1 0x0102 /* desktop */
|
||||
#define PCI_CHIP_SANDYBRIDGE_GT2 0x0112
|
||||
@ -88,14 +88,14 @@
|
||||
#define PCI_CHIP_IVYBRIDGE_S 0x015a /* server */
|
||||
#define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a /* server */
|
||||
|
||||
#define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */
|
||||
#define PCI_CHIP_HASWELL_GT2 0x0412
|
||||
#define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */
|
||||
#define PCI_CHIP_HASWELL_GT2 0x0412
|
||||
#define PCI_CHIP_HASWELL_GT3 0x0422
|
||||
#define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */
|
||||
#define PCI_CHIP_HASWELL_M_GT2 0x0416
|
||||
#define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */
|
||||
#define PCI_CHIP_HASWELL_M_GT2 0x0416
|
||||
#define PCI_CHIP_HASWELL_M_GT3 0x0426
|
||||
#define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */
|
||||
#define PCI_CHIP_HASWELL_S_GT2 0x041A
|
||||
#define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */
|
||||
#define PCI_CHIP_HASWELL_S_GT2 0x041A
|
||||
#define PCI_CHIP_HASWELL_S_GT3 0x042A
|
||||
#define PCI_CHIP_HASWELL_B_GT1 0x040B /* Reserved */
|
||||
#define PCI_CHIP_HASWELL_B_GT2 0x041B
|
||||
@ -103,14 +103,14 @@
|
||||
#define PCI_CHIP_HASWELL_E_GT1 0x040E /* Reserved */
|
||||
#define PCI_CHIP_HASWELL_E_GT2 0x041E
|
||||
#define PCI_CHIP_HASWELL_E_GT3 0x042E
|
||||
#define PCI_CHIP_HASWELL_SDV_GT1 0x0C02 /* Desktop */
|
||||
#define PCI_CHIP_HASWELL_SDV_GT2 0x0C12
|
||||
#define PCI_CHIP_HASWELL_SDV_GT1 0x0C02 /* Desktop */
|
||||
#define PCI_CHIP_HASWELL_SDV_GT2 0x0C12
|
||||
#define PCI_CHIP_HASWELL_SDV_GT3 0x0C22
|
||||
#define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 /* Mobile */
|
||||
#define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16
|
||||
#define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 /* Mobile */
|
||||
#define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16
|
||||
#define PCI_CHIP_HASWELL_SDV_M_GT3 0x0C26
|
||||
#define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */
|
||||
#define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A
|
||||
#define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */
|
||||
#define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A
|
||||
#define PCI_CHIP_HASWELL_SDV_S_GT3 0x0C2A
|
||||
#define PCI_CHIP_HASWELL_SDV_B_GT1 0x0C0B /* Reserved */
|
||||
#define PCI_CHIP_HASWELL_SDV_B_GT2 0x0C1B
|
||||
@ -118,14 +118,14 @@
|
||||
#define PCI_CHIP_HASWELL_SDV_E_GT1 0x0C0E /* Reserved */
|
||||
#define PCI_CHIP_HASWELL_SDV_E_GT2 0x0C1E
|
||||
#define PCI_CHIP_HASWELL_SDV_E_GT3 0x0C2E
|
||||
#define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */
|
||||
#define PCI_CHIP_HASWELL_ULT_GT2 0x0A12
|
||||
#define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */
|
||||
#define PCI_CHIP_HASWELL_ULT_GT2 0x0A12
|
||||
#define PCI_CHIP_HASWELL_ULT_GT3 0x0A22
|
||||
#define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */
|
||||
#define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16
|
||||
#define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */
|
||||
#define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16
|
||||
#define PCI_CHIP_HASWELL_ULT_M_GT3 0x0A26
|
||||
#define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */
|
||||
#define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
|
||||
#define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */
|
||||
#define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
|
||||
#define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A
|
||||
#define PCI_CHIP_HASWELL_ULT_B_GT1 0x0A0B /* Reserved */
|
||||
#define PCI_CHIP_HASWELL_ULT_B_GT2 0x0A1B
|
||||
@ -165,6 +165,32 @@
|
||||
#define PCI_CHIP_CHERRYVIEW_2 0x22b2
|
||||
#define PCI_CHIP_CHERRYVIEW_3 0x22b3
|
||||
|
||||
#define PCI_CHIP_SKYLAKE_DT_GT1 0x1902
|
||||
#define PCI_CHIP_SKYLAKE_ULT_GT1 0x1906
|
||||
#define PCI_CHIP_SKYLAKE_SRV_GT1 0x190A /* Reserved */
|
||||
#define PCI_CHIP_SKYLAKE_ULX_GT1 0x190E /* Reserved */
|
||||
#define PCI_CHIP_SKYLAKE_DT_GT2 0x1912
|
||||
#define PCI_CHIP_SKYLAKE_FUSED0_GT2 0x1913 /* Reserved */
|
||||
#define PCI_CHIP_SKYLAKE_FUSED1_GT2 0x1915 /* Reserved */
|
||||
#define PCI_CHIP_SKYLAKE_ULT_GT2 0x1916
|
||||
#define PCI_CHIP_SKYLAKE_FUSED2_GT2 0x1917 /* Reserved */
|
||||
#define PCI_CHIP_SKYLAKE_SRV_GT2 0x191A /* Reserved */
|
||||
#define PCI_CHIP_SKYLAKE_HALO_GT2 0x191B
|
||||
#define PCI_CHIP_SKYLAKE_WKS_GT2 0x191D
|
||||
#define PCI_CHIP_SKYLAKE_ULX_GT2 0x191E
|
||||
#define PCI_CHIP_SKYLAKE_MOBILE_GT2 0x1921 /* Reserved */
|
||||
#define PCI_CHIP_SKYLAKE_GT3 0x1926
|
||||
#define PCI_CHIP_SKYLAKE_HALO_GT3 0x192B /* Reserved */
|
||||
#define PCI_CHIP_SKYLAKE_SRV_GT4 0x192A
|
||||
#define PCI_CHIP_SKYLAKE_DT_GT4 0x1932
|
||||
#define PCI_CHIP_SKYLAKE_SRV_GT4X 0x193A
|
||||
#define PCI_CHIP_SKYLAKE_H_GT4 0x193B
|
||||
#define PCI_CHIP_SKYLAKE_WKS_GT4 0x193D
|
||||
|
||||
#define PCI_CHIP_BROXTON_0 0x0A84
|
||||
#define PCI_CHIP_BROXTON_1 0x1A84
|
||||
#define PCI_CHIP_BROXTON_2 0x5A84
|
||||
|
||||
#define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \
|
||||
(devid) == PCI_CHIP_I915_GM || \
|
||||
(devid) == PCI_CHIP_I945_GM || \
|
||||
@ -226,8 +252,8 @@
|
||||
(devid) == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
|
||||
(devid) == PCI_CHIP_SANDYBRIDGE_S)
|
||||
|
||||
#define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \
|
||||
IS_HASWELL(devid) || \
|
||||
#define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \
|
||||
IS_HASWELL(devid) || \
|
||||
IS_VALLEYVIEW(devid))
|
||||
|
||||
#define IS_IVYBRIDGE(devid) ((devid) == PCI_CHIP_IVYBRIDGE_GT1 || \
|
||||
@ -303,7 +329,7 @@
|
||||
(devid) == PCI_CHIP_HASWELL_CRW_B_GT3 || \
|
||||
(devid) == PCI_CHIP_HASWELL_CRW_E_GT3)
|
||||
|
||||
#define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \
|
||||
#define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \
|
||||
IS_HSW_GT2(devid) || \
|
||||
IS_HSW_GT3(devid))
|
||||
|
||||
@ -324,12 +350,50 @@
|
||||
#define IS_GEN8(devid) (IS_BROADWELL(devid) || \
|
||||
IS_CHERRYVIEW(devid))
|
||||
|
||||
#define IS_SKL_GT1(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT1 || \
|
||||
(devid) == PCI_CHIP_SKYLAKE_ULX_GT1 || \
|
||||
(devid) == PCI_CHIP_SKYLAKE_DT_GT1 || \
|
||||
(devid) == PCI_CHIP_SKYLAKE_SRV_GT1)
|
||||
|
||||
#define IS_SKL_GT2(devid) ((devid) == PCI_CHIP_SKYLAKE_DT_GT2 || \
|
||||
(devid) == PCI_CHIP_SKYLAKE_FUSED0_GT2 || \
|
||||
(devid) == PCI_CHIP_SKYLAKE_FUSED1_GT2 || \
|
||||
(devid) == PCI_CHIP_SKYLAKE_ULT_GT2 || \
|
||||
(devid) == PCI_CHIP_SKYLAKE_FUSED2_GT2 || \
|
||||
(devid) == PCI_CHIP_SKYLAKE_SRV_GT2 || \
|
||||
(devid) == PCI_CHIP_SKYLAKE_HALO_GT2 || \
|
||||
(devid) == PCI_CHIP_SKYLAKE_WKS_GT2 || \
|
||||
(devid) == PCI_CHIP_SKYLAKE_ULX_GT2 || \
|
||||
(devid) == PCI_CHIP_SKYLAKE_MOBILE_GT2)
|
||||
|
||||
#define IS_SKL_GT3(devid) ((devid) == PCI_CHIP_SKYLAKE_GT3 || \
|
||||
(devid) == PCI_CHIP_SKYLAKE_HALO_GT3)
|
||||
|
||||
#define IS_SKL_GT4(devid) ((devid) == PCI_CHIP_SKYLAKE_SRV_GT4 || \
|
||||
(devid) == PCI_CHIP_SKYLAKE_DT_GT4 || \
|
||||
(devid) == PCI_CHIP_SKYLAKE_SRV_GT4X || \
|
||||
(devid) == PCI_CHIP_SKYLAKE_H_GT4 || \
|
||||
(devid) == PCI_CHIP_SKYLAKE_WKS_GT4)
|
||||
|
||||
#define IS_SKYLAKE(devid) (IS_SKL_GT1(devid) || \
|
||||
IS_SKL_GT2(devid) || \
|
||||
IS_SKL_GT3(devid) || \
|
||||
IS_SKL_GT4(devid))
|
||||
|
||||
#define IS_BROXTON(devid) ((devid) == PCI_CHIP_BROXTON_0 || \
|
||||
(devid) == PCI_CHIP_BROXTON_1 || \
|
||||
(devid) == PCI_CHIP_BROXTON_2)
|
||||
|
||||
#define IS_GEN9(devid) (IS_SKYLAKE(devid) || \
|
||||
IS_BROXTON(devid))
|
||||
|
||||
#define IS_9XX(dev) (IS_GEN3(dev) || \
|
||||
IS_GEN4(dev) || \
|
||||
IS_GEN5(dev) || \
|
||||
IS_GEN6(dev) || \
|
||||
IS_GEN7(dev) || \
|
||||
IS_GEN8(dev))
|
||||
IS_GEN8(dev) || \
|
||||
IS_GEN9(dev))
|
||||
|
||||
|
||||
#endif /* _INTEL_CHIPSET_H */
|
||||
|
||||
@ -29,10 +29,14 @@
|
||||
#include <stdarg.h>
|
||||
#include <string.h>
|
||||
|
||||
#include "libdrm_macros.h"
|
||||
#include "xf86drm.h"
|
||||
#include "intel_chipset.h"
|
||||
#include "intel_bufmgr.h"
|
||||
|
||||
/* The compiler throws ~90 warnings. Do not spam the build, until we fix them. */
|
||||
#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
|
||||
|
||||
/* Struct for tracking drm_intel_decode state. */
|
||||
struct drm_intel_decode {
|
||||
/** stdio file where the output should land. Defaults to stdout. */
|
||||
@ -3625,7 +3629,6 @@ decode_3d_965(struct drm_intel_decode *ctx)
|
||||
|
||||
case 0x7a00:
|
||||
if (IS_GEN6(devid) || IS_GEN7(devid)) {
|
||||
unsigned int i;
|
||||
if (len != 4 && len != 5)
|
||||
fprintf(out, "Bad count in PIPE_CONTROL\n");
|
||||
|
||||
@ -3727,8 +3730,6 @@ decode_3d_965(struct drm_intel_decode *ctx)
|
||||
if (opcode_3d->func) {
|
||||
return opcode_3d->func(ctx);
|
||||
} else {
|
||||
unsigned int i;
|
||||
|
||||
instr_out(ctx, 0, "%s\n", opcode_3d->name);
|
||||
|
||||
for (i = 1; i < len; i++) {
|
||||
@ -3824,7 +3825,9 @@ drm_intel_decode_context_alloc(uint32_t devid)
|
||||
ctx->devid = devid;
|
||||
ctx->out = stdout;
|
||||
|
||||
if (IS_GEN8(devid))
|
||||
if (IS_GEN9(devid))
|
||||
ctx->gen = 9;
|
||||
else if (IS_GEN8(devid))
|
||||
ctx->gen = 8;
|
||||
else if (IS_GEN7(devid))
|
||||
ctx->gen = 7;
|
||||
@ -3876,9 +3879,9 @@ drm_intel_decode_set_head_tail(struct drm_intel_decode *ctx,
|
||||
|
||||
void
|
||||
drm_intel_decode_set_output_file(struct drm_intel_decode *ctx,
|
||||
FILE *out)
|
||||
FILE *output)
|
||||
{
|
||||
ctx->out = out;
|
||||
ctx->out = output;
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
81
contrib/sdk/sources/libdrm/libdrm_macros.h
Normal file
81
contrib/sdk/sources/libdrm/libdrm_macros.h
Normal file
@ -0,0 +1,81 @@
|
||||
/*
|
||||
* Copyright © 2014 NVIDIA Corporation
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef LIBDRM_LIBDRM_H
|
||||
#define LIBDRM_LIBDRM_H
|
||||
|
||||
#if defined(HAVE_VISIBILITY)
|
||||
# define drm_private __attribute__((visibility("hidden")))
|
||||
#else
|
||||
# define drm_private
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* Static (compile-time) assertion.
|
||||
* Basically, use COND to dimension an array. If COND is false/zero the
|
||||
* array size will be -1 and we'll get a compilation error.
|
||||
*/
|
||||
#define STATIC_ASSERT(COND) \
|
||||
do { \
|
||||
(void) sizeof(char [1 - 2*!(COND)]); \
|
||||
} while (0)
|
||||
|
||||
|
||||
|
||||
#if defined(ANDROID) && !defined(__LP64__)
|
||||
#include <errno.h> /* for EINVAL */
|
||||
|
||||
extern void *__mmap2(void *, size_t, int, int, int, size_t);
|
||||
|
||||
static inline void *drm_mmap(void *addr, size_t length, int prot, int flags,
|
||||
int fd, loff_t offset)
|
||||
{
|
||||
/* offset must be aligned to 4096 (not necessarily the page size) */
|
||||
if (offset & 4095) {
|
||||
errno = EINVAL;
|
||||
return MAP_FAILED;
|
||||
}
|
||||
|
||||
return __mmap2(addr, length, prot, flags, fd, (size_t) (offset >> 12));
|
||||
}
|
||||
|
||||
# define drm_munmap(addr, length) \
|
||||
munmap(addr, length)
|
||||
|
||||
|
||||
#else
|
||||
|
||||
/* assume large file support exists */
|
||||
# define drm_mmap(addr, length, prot, flags, fd, offset) \
|
||||
mmap(addr, length, prot, flags, fd, offset)
|
||||
|
||||
|
||||
static inline int drm_munmap(void *addr, size_t length)
|
||||
{
|
||||
/* Copied from configure code generated by AC_SYS_LARGEFILE */
|
||||
|
||||
return munmap(addr, length);
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -48,7 +48,8 @@ typedef struct {
|
||||
# define atomic_read(x) ((x)->atomic)
|
||||
# define atomic_set(x, val) ((x)->atomic = (val))
|
||||
# define atomic_inc(x) ((void) __sync_fetch_and_add (&(x)->atomic, 1))
|
||||
# define atomic_dec_and_test(x) (__sync_fetch_and_add (&(x)->atomic, -1) == 1)
|
||||
# define atomic_inc_return(x) (__sync_add_and_fetch (&(x)->atomic, 1))
|
||||
# define atomic_dec_and_test(x) (__sync_add_and_fetch (&(x)->atomic, -1) == 0)
|
||||
# define atomic_add(x, v) ((void) __sync_add_and_fetch(&(x)->atomic, (v)))
|
||||
# define atomic_dec(x, v) ((void) __sync_sub_and_fetch(&(x)->atomic, (v)))
|
||||
# define atomic_cmpxchg(x, oldv, newv) __sync_val_compare_and_swap (&(x)->atomic, oldv, newv)
|
||||
@ -66,6 +67,7 @@ typedef struct {
|
||||
# define atomic_read(x) AO_load_full(&(x)->atomic)
|
||||
# define atomic_set(x, val) AO_store_full(&(x)->atomic, (val))
|
||||
# define atomic_inc(x) ((void) AO_fetch_and_add1_full(&(x)->atomic))
|
||||
# define atomic_inc_return(x) (AO_fetch_and_add1_full(&(x)->atomic) + 1)
|
||||
# define atomic_add(x, v) ((void) AO_fetch_and_add_full(&(x)->atomic, (v)))
|
||||
# define atomic_dec(x, v) ((void) AO_fetch_and_add_full(&(x)->atomic, -(v)))
|
||||
# define atomic_dec_and_test(x) (AO_fetch_and_sub1_full(&(x)->atomic) == 1)
|
||||
@ -73,17 +75,24 @@ typedef struct {
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(__sun) && !defined(HAS_ATOMIC_OPS) /* Solaris & OpenSolaris */
|
||||
#if (defined(__sun) || defined(__NetBSD__)) && !defined(HAS_ATOMIC_OPS) /* Solaris & OpenSolaris & NetBSD */
|
||||
|
||||
#include <sys/atomic.h>
|
||||
#define HAS_ATOMIC_OPS 1
|
||||
|
||||
typedef struct { uint_t atomic; } atomic_t;
|
||||
#if defined(__NetBSD__)
|
||||
#define LIBDRM_ATOMIC_TYPE int
|
||||
#else
|
||||
#define LIBDRM_ATOMIC_TYPE uint_t
|
||||
#endif
|
||||
|
||||
typedef struct { LIBDRM_ATOMIC_TYPE atomic; } atomic_t;
|
||||
|
||||
# define atomic_read(x) (int) ((x)->atomic)
|
||||
# define atomic_set(x, val) ((x)->atomic = (uint_t)(val))
|
||||
# define atomic_set(x, val) ((x)->atomic = (LIBDRM_ATOMIC_TYPE)(val))
|
||||
# define atomic_inc(x) (atomic_inc_uint (&(x)->atomic))
|
||||
# define atomic_dec_and_test(x) (atomic_dec_uint_nv(&(x)->atomic) == 1)
|
||||
# define atomic_inc_return(x) (atomic_inc_uint_nv(&(x)->atomic))
|
||||
# define atomic_dec_and_test(x) (atomic_dec_uint_nv(&(x)->atomic) == 0)
|
||||
# define atomic_add(x, v) (atomic_add_int(&(x)->atomic, (v)))
|
||||
# define atomic_dec(x, v) (atomic_add_int(&(x)->atomic, -(v)))
|
||||
# define atomic_cmpxchg(x, oldv, newv) atomic_cas_uint (&(x)->atomic, oldv, newv)
|
||||
@ -94,4 +103,13 @@ typedef struct { uint_t atomic; } atomic_t;
|
||||
#error libdrm requires atomic operations, please define them for your CPU/compiler.
|
||||
#endif
|
||||
|
||||
static inline int atomic_add_unless(atomic_t *v, int add, int unless)
|
||||
{
|
||||
int c, old;
|
||||
c = atomic_read(v);
|
||||
while (c != unless && (old = atomic_cmpxchg(v, c, c + add)) != c)
|
||||
c = old;
|
||||
return c == unless;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/**
|
||||
* \file xf86drm.c
|
||||
* \file xf86drm.c
|
||||
* User-level interface to DRM device
|
||||
*
|
||||
* \author Rickard E. (Rik) Faith <faith@valinux.com>
|
||||
@ -39,9 +39,12 @@
|
||||
#include <string.h>
|
||||
#include <strings.h>
|
||||
#include <ctype.h>
|
||||
#include <stddef.h>
|
||||
#include <fcntl.h>
|
||||
#include <errno.h>
|
||||
#include <time.h>
|
||||
#include <sys/types.h>
|
||||
#include <sys/stat.h>
|
||||
#include <stdarg.h>
|
||||
|
||||
/* Not all systems have MAP_FAILED defined */
|
||||
@ -50,10 +53,12 @@
|
||||
#endif
|
||||
|
||||
#include "xf86drm.h"
|
||||
#include "libdrm_macros.h"
|
||||
|
||||
#include <kos32sys.h>
|
||||
|
||||
#ifndef DRM_MAJOR
|
||||
#define DRM_MAJOR 226 /* Linux */
|
||||
#define DRM_MAJOR 226 /* Linux */
|
||||
#endif
|
||||
|
||||
|
||||
@ -89,7 +94,7 @@ drmVersionPtr drmGetVersion(int fd)
|
||||
v->name_len = 4;
|
||||
v->name = "i915";
|
||||
v->date_len = 8;
|
||||
v->date = "20080730";
|
||||
v->date = "20151010";
|
||||
v->desc_len = 14;
|
||||
v->desc = "Intel Graphics";
|
||||
return v;
|
||||
|
||||
@ -39,7 +39,7 @@
|
||||
#include <stdint.h>
|
||||
#include <drm.h>
|
||||
|
||||
#if defined(__cplusplus) || defined(c_plusplus)
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
@ -66,6 +66,7 @@ extern "C" {
|
||||
#define DRM_DIR_NAME "/dev/dri"
|
||||
#define DRM_DEV_NAME "%s/card%d"
|
||||
#define DRM_CONTROL_DEV_NAME "%s/controlD%d"
|
||||
#define DRM_RENDER_DEV_NAME "%s/renderD%d"
|
||||
#define DRM_PROC_NAME "/proc/dri/" /* For backward Linux compatibility */
|
||||
|
||||
#define DRM_ERR_NO_DEVICE (-1001)
|
||||
@ -537,7 +538,8 @@ do { register unsigned int __old __asm("o0"); \
|
||||
/* General user-level programmer's API: unprivileged */
|
||||
extern int drmAvailable(void);
|
||||
extern int drmOpen(const char *name, const char *busid);
|
||||
extern int drmOpenControl(int minor);
|
||||
extern int drmOpenControl(int minor);
|
||||
extern int drmOpenRender(int minor);
|
||||
extern int drmClose(int fd);
|
||||
extern drmVersionPtr drmGetVersion(int fd);
|
||||
extern drmVersionPtr drmGetLibVersion(int fd);
|
||||
@ -720,6 +722,7 @@ typedef struct _drmEventContext {
|
||||
extern int drmHandleEvent(int fd, drmEventContextPtr evctx);
|
||||
|
||||
extern char *drmGetDeviceNameFromFd(int fd);
|
||||
extern int drmGetNodeTypeFromFd(int fd);
|
||||
|
||||
extern int drmPrimeHandleToFD(int fd, uint32_t handle, uint32_t flags, int *prime_fd);
|
||||
extern int drmPrimeFDToHandle(int fd, int prime_fd, uint32_t *handle);
|
||||
|
||||
@ -36,7 +36,7 @@
|
||||
#ifndef _XF86DRMMODE_H_
|
||||
#define _XF86DRMMODE_H_
|
||||
|
||||
#if defined(__cplusplus) || defined(c_plusplus)
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
@ -240,6 +240,15 @@ typedef struct _drmModeProperty {
|
||||
uint32_t *blob_ids; /* store the blob IDs */
|
||||
} drmModePropertyRes, *drmModePropertyPtr;
|
||||
|
||||
static __inline int drm_property_type_is(drmModePropertyPtr property,
|
||||
uint32_t type)
|
||||
{
|
||||
/* instanceof for props.. handles extended type vs original types: */
|
||||
if (property->flags & DRM_MODE_PROP_EXTENDED_TYPE)
|
||||
return (property->flags & DRM_MODE_PROP_EXTENDED_TYPE) == type;
|
||||
return property->flags & type;
|
||||
}
|
||||
|
||||
typedef struct _drmModeCrtc {
|
||||
uint32_t crtc_id;
|
||||
uint32_t buffer_id; /**< FB id to connect to 0 = disconnect */
|
||||
@ -413,10 +422,23 @@ drmModeEncoderPtr drmModeGetEncoder(int fd, uint32_t encoder_id);
|
||||
*/
|
||||
|
||||
/**
|
||||
* Retrive information about the connector connectorId.
|
||||
* Retrieve all information about the connector connectorId. This will do a
|
||||
* forced probe on the connector to retrieve remote information such as EDIDs
|
||||
* from the display device.
|
||||
*/
|
||||
extern drmModeConnectorPtr drmModeGetConnector(int fd,
|
||||
uint32_t connectorId);
|
||||
uint32_t connectorId);
|
||||
|
||||
/**
|
||||
* Retrieve current information, i.e the currently active mode and encoder,
|
||||
* about the connector connectorId. This will not do any probing on the
|
||||
* connector or remote device, and only reports what is currently known.
|
||||
* For the complete set of modes and encoders associated with the connector
|
||||
* use drmModeGetConnector() which will do a probe to determine any display
|
||||
* link changes first.
|
||||
*/
|
||||
extern drmModeConnectorPtr drmModeGetConnectorCurrent(int fd,
|
||||
uint32_t connector_id);
|
||||
|
||||
/**
|
||||
* Attaches the given mode to an connector.
|
||||
@ -462,7 +484,31 @@ extern int drmModeObjectSetProperty(int fd, uint32_t object_id,
|
||||
uint32_t object_type, uint32_t property_id,
|
||||
uint64_t value);
|
||||
|
||||
#if defined(__cplusplus) || defined(c_plusplus)
|
||||
|
||||
typedef struct _drmModeAtomicReq drmModeAtomicReq, *drmModeAtomicReqPtr;
|
||||
|
||||
extern drmModeAtomicReqPtr drmModeAtomicAlloc(void);
|
||||
extern drmModeAtomicReqPtr drmModeAtomicDuplicate(drmModeAtomicReqPtr req);
|
||||
extern int drmModeAtomicMerge(drmModeAtomicReqPtr base,
|
||||
drmModeAtomicReqPtr augment);
|
||||
extern void drmModeAtomicFree(drmModeAtomicReqPtr req);
|
||||
extern int drmModeAtomicGetCursor(drmModeAtomicReqPtr req);
|
||||
extern void drmModeAtomicSetCursor(drmModeAtomicReqPtr req, int cursor);
|
||||
extern int drmModeAtomicAddProperty(drmModeAtomicReqPtr req,
|
||||
uint32_t object_id,
|
||||
uint32_t property_id,
|
||||
uint64_t value);
|
||||
extern int drmModeAtomicCommit(int fd,
|
||||
drmModeAtomicReqPtr req,
|
||||
uint32_t flags,
|
||||
void *user_data);
|
||||
|
||||
extern int drmModeCreatePropertyBlob(int fd, const void *data, size_t size,
|
||||
uint32_t *id);
|
||||
extern int drmModeDestroyPropertyBlob(int fd, uint32_t id);
|
||||
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user