kms: pre rc7
git-svn-id: svn://kolibrios.org@1275 a494cfbc-eb01-0410-851d-a64ba20cac60
This commit is contained in:
@@ -640,12 +640,6 @@ struct fb_ops {
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/* perform fb specific mmap */
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// int (*fb_mmap)(struct fb_info *info, struct vm_area_struct *vma);
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/* save current hardware state */
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void (*fb_save_state)(struct fb_info *info);
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/* restore saved state */
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void (*fb_restore_state)(struct fb_info *info);
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/* get capability given var */
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void (*fb_get_caps)(struct fb_info *info, struct fb_blit_caps *caps,
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struct fb_var_screeninfo *var);
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@@ -213,8 +213,6 @@ bool radeon_card_posted(struct radeon_device *rdev)
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{
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uint32_t reg;
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ENTER();
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/* first check CRTCs */
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if (ASIC_IS_AVIVO(rdev)) {
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reg = RREG32(AVIVO_D1CRTC_CONTROL) |
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@@ -415,8 +413,6 @@ int radeon_clocks_init(struct radeon_device *rdev)
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{
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int r;
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ENTER();
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r = radeon_static_clocks_init(rdev->ddev);
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if (r) {
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return r;
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@@ -561,8 +557,6 @@ int radeon_device_init(struct radeon_device *rdev,
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int r;
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int dma_bits;
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ENTER();
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DRM_INFO("radeon: Initializing kernel modesetting.\n");
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rdev->shutdown = false;
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rdev->ddev = ddev;
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@@ -901,7 +895,7 @@ u32_t drvEntry(int action, char *cmdline)
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return 0;
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};
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}
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dbgprintf("Radeon RC06 cmdline %s\n", cmdline);
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dbgprintf("Radeon RC07 cmdline %s\n", cmdline);
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enum_pci_devices();
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@@ -77,8 +77,6 @@ int radeon_gart_table_vram_alloc(struct radeon_device *rdev)
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{
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int r;
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ENTER();
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if (rdev->gart.table.vram.robj == NULL) {
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r = radeon_object_create(rdev, NULL,
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rdev->gart.table_size,
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@@ -214,17 +212,11 @@ int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
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}
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mb();
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radeon_gart_tlb_flush(rdev);
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LEAVE();
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return 0;
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}
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int radeon_gart_init(struct radeon_device *rdev)
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{
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ENTER();
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if (rdev->gart.pages) {
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return 0;
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}
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@@ -453,6 +453,8 @@ int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
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// radeon_object_get_tiling_flags(obj->driver_private,
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// &tiling_flags, NULL);
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tiling_flags = 0;
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if (tiling_flags & RADEON_TILING_MICRO)
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DRM_ERROR("trying to scanout microtiled buffer\n");
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@@ -530,10 +532,10 @@ int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
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WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);
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WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
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if (old_fb && old_fb != crtc->fb) {
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radeon_fb = to_radeon_framebuffer(old_fb);
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// if (old_fb && old_fb != crtc->fb) {
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// radeon_fb = to_radeon_framebuffer(old_fb);
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// radeon_gem_object_unpin(radeon_fb->obj);
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}
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// }
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/* Bytes per pixel may have changed */
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radeon_bandwidth_update(rdev);
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@@ -53,7 +53,7 @@ int radeon_object_init(struct radeon_device *rdev)
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ENTER();
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r = drm_mm_init(&mm_vram, 0x800000 >> PAGE_SHIFT,
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((rdev->mc.aper_size - 0x800000) >> PAGE_SHIFT));
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((rdev->mc.real_vram_size - 0x800000) >> PAGE_SHIFT));
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if (r) {
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DRM_ERROR("Failed initializing VRAM heap.\n");
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return r;
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@@ -67,7 +67,7 @@ static void radeon_show_cursor()
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WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN |
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(AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
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} else {
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WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL);
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WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL);
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WREG32_P(RADEON_MM_DATA, (RADEON_CRTC_CUR_EN |
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(RADEON_CRTC_CUR_MODE_24BPP << RADEON_CRTC_CUR_MODE_SHIFT)),
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~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK));
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@@ -139,11 +139,11 @@ void __stdcall move_cursor(cursor_t *cursor, int x, int y)
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WREG32(AVIVO_D1CUR_POSITION, (x << 16) | y);
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WREG32(AVIVO_D1CUR_HOT_SPOT, (hot_x << 16) | hot_y);
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WREG32(AVIVO_D1CUR_SIZE, ((w - 1) << 16) | 31);
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} else {
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} else {
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uint32_t gpu_addr;
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WREG32(RADEON_CUR_HORZ_VERT_OFF,
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(RADEON_CUR_LOCK | (hot_x << 16) | (hot_y << 16)));
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(RADEON_CUR_LOCK | (hot_x << 16) | hot_y ));
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WREG32(RADEON_CUR_HORZ_VERT_POSN,
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(RADEON_CUR_LOCK | (x << 16) | y));
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@@ -163,9 +163,9 @@ void __stdcall restore_cursor(int x, int y)
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bool init_display(struct radeon_device *rdev, mode_t *usermode)
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{
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struct drm_device *dev;
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struct drm_device *dev;
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cursor_t *cursor;
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cursor_t *cursor;
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bool retval = true;
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u32_t ifl;
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@@ -177,17 +177,17 @@ bool init_display(struct radeon_device *rdev, mode_t *usermode)
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ifl = safe_cli();
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{
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list_for_each_entry(cursor, &rdisplay->cursors, list)
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{
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init_cursor(cursor);
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};
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list_for_each_entry(cursor, &rdisplay->cursors, list)
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{
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init_cursor(cursor);
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};
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rdisplay->restore_cursor(0,0);
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rdisplay->init_cursor = init_cursor;
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rdisplay->select_cursor = select_cursor;
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rdisplay->show_cursor = NULL;
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rdisplay->move_cursor = move_cursor;
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rdisplay->restore_cursor = restore_cursor;
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rdisplay->restore_cursor(0,0);
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rdisplay->init_cursor = init_cursor;
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rdisplay->select_cursor = select_cursor;
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rdisplay->show_cursor = NULL;
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rdisplay->move_cursor = move_cursor;
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rdisplay->restore_cursor = restore_cursor;
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select_cursor(rdisplay->cursor);
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radeon_show_cursor();
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@@ -82,7 +82,7 @@ cursor_t* __stdcall select_cursor_kms(cursor_t *cursor)
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if (ASIC_IS_AVIVO(rdev))
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WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, gpu_addr);
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else {
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radeon_crtc->legacy_cursor_offset = gpu_addr - radeon_crtc->legacy_display_base_addr;
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radeon_crtc->legacy_cursor_offset = gpu_addr - rdev->mc.vram_location;
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/* offset is from DISP(2)_BASE_ADDRESS */
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WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, radeon_crtc->legacy_cursor_offset);
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}
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@@ -148,7 +148,7 @@ void __stdcall move_cursor_kms(cursor_t *cursor, int x, int y)
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y *= 2;
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WREG32(RADEON_CUR_HORZ_VERT_OFF + radeon_crtc->crtc_offset,
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(RADEON_CUR_LOCK | (hot_x << 16) | (hot_y << 16)));
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(RADEON_CUR_LOCK | (hot_x << 16) | hot_y ));
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WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset,
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(RADEON_CUR_LOCK | (x << 16) | y));
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