kms: pre rc7

git-svn-id: svn://kolibrios.org@1275 a494cfbc-eb01-0410-851d-a64ba20cac60
This commit is contained in:
Sergey Semyonov (Serge)
2009-11-16 11:28:19 +00:00
parent e586c535b0
commit b81d03be4e
13 changed files with 120 additions and 88 deletions

View File

@@ -640,12 +640,6 @@ struct fb_ops {
/* perform fb specific mmap */
// int (*fb_mmap)(struct fb_info *info, struct vm_area_struct *vma);
/* save current hardware state */
void (*fb_save_state)(struct fb_info *info);
/* restore saved state */
void (*fb_restore_state)(struct fb_info *info);
/* get capability given var */
void (*fb_get_caps)(struct fb_info *info, struct fb_blit_caps *caps,
struct fb_var_screeninfo *var);

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@@ -213,8 +213,6 @@ bool radeon_card_posted(struct radeon_device *rdev)
{
uint32_t reg;
ENTER();
/* first check CRTCs */
if (ASIC_IS_AVIVO(rdev)) {
reg = RREG32(AVIVO_D1CRTC_CONTROL) |
@@ -415,8 +413,6 @@ int radeon_clocks_init(struct radeon_device *rdev)
{
int r;
ENTER();
r = radeon_static_clocks_init(rdev->ddev);
if (r) {
return r;
@@ -561,8 +557,6 @@ int radeon_device_init(struct radeon_device *rdev,
int r;
int dma_bits;
ENTER();
DRM_INFO("radeon: Initializing kernel modesetting.\n");
rdev->shutdown = false;
rdev->ddev = ddev;
@@ -901,7 +895,7 @@ u32_t drvEntry(int action, char *cmdline)
return 0;
};
}
dbgprintf("Radeon RC06 cmdline %s\n", cmdline);
dbgprintf("Radeon RC07 cmdline %s\n", cmdline);
enum_pci_devices();

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@@ -77,8 +77,6 @@ int radeon_gart_table_vram_alloc(struct radeon_device *rdev)
{
int r;
ENTER();
if (rdev->gart.table.vram.robj == NULL) {
r = radeon_object_create(rdev, NULL,
rdev->gart.table_size,
@@ -214,17 +212,11 @@ int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
}
mb();
radeon_gart_tlb_flush(rdev);
LEAVE();
return 0;
}
int radeon_gart_init(struct radeon_device *rdev)
{
ENTER();
if (rdev->gart.pages) {
return 0;
}

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@@ -453,6 +453,8 @@ int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
// radeon_object_get_tiling_flags(obj->driver_private,
// &tiling_flags, NULL);
tiling_flags = 0;
if (tiling_flags & RADEON_TILING_MICRO)
DRM_ERROR("trying to scanout microtiled buffer\n");
@@ -530,10 +532,10 @@ int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);
WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
if (old_fb && old_fb != crtc->fb) {
radeon_fb = to_radeon_framebuffer(old_fb);
// if (old_fb && old_fb != crtc->fb) {
// radeon_fb = to_radeon_framebuffer(old_fb);
// radeon_gem_object_unpin(radeon_fb->obj);
}
// }
/* Bytes per pixel may have changed */
radeon_bandwidth_update(rdev);

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@@ -53,7 +53,7 @@ int radeon_object_init(struct radeon_device *rdev)
ENTER();
r = drm_mm_init(&mm_vram, 0x800000 >> PAGE_SHIFT,
((rdev->mc.aper_size - 0x800000) >> PAGE_SHIFT));
((rdev->mc.real_vram_size - 0x800000) >> PAGE_SHIFT));
if (r) {
DRM_ERROR("Failed initializing VRAM heap.\n");
return r;

View File

@@ -67,7 +67,7 @@ static void radeon_show_cursor()
WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN |
(AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
} else {
WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL);
WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL);
WREG32_P(RADEON_MM_DATA, (RADEON_CRTC_CUR_EN |
(RADEON_CRTC_CUR_MODE_24BPP << RADEON_CRTC_CUR_MODE_SHIFT)),
~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK));
@@ -139,11 +139,11 @@ void __stdcall move_cursor(cursor_t *cursor, int x, int y)
WREG32(AVIVO_D1CUR_POSITION, (x << 16) | y);
WREG32(AVIVO_D1CUR_HOT_SPOT, (hot_x << 16) | hot_y);
WREG32(AVIVO_D1CUR_SIZE, ((w - 1) << 16) | 31);
} else {
} else {
uint32_t gpu_addr;
WREG32(RADEON_CUR_HORZ_VERT_OFF,
(RADEON_CUR_LOCK | (hot_x << 16) | (hot_y << 16)));
(RADEON_CUR_LOCK | (hot_x << 16) | hot_y ));
WREG32(RADEON_CUR_HORZ_VERT_POSN,
(RADEON_CUR_LOCK | (x << 16) | y));
@@ -163,9 +163,9 @@ void __stdcall restore_cursor(int x, int y)
bool init_display(struct radeon_device *rdev, mode_t *usermode)
{
struct drm_device *dev;
struct drm_device *dev;
cursor_t *cursor;
cursor_t *cursor;
bool retval = true;
u32_t ifl;
@@ -177,17 +177,17 @@ bool init_display(struct radeon_device *rdev, mode_t *usermode)
ifl = safe_cli();
{
list_for_each_entry(cursor, &rdisplay->cursors, list)
{
init_cursor(cursor);
};
list_for_each_entry(cursor, &rdisplay->cursors, list)
{
init_cursor(cursor);
};
rdisplay->restore_cursor(0,0);
rdisplay->init_cursor = init_cursor;
rdisplay->select_cursor = select_cursor;
rdisplay->show_cursor = NULL;
rdisplay->move_cursor = move_cursor;
rdisplay->restore_cursor = restore_cursor;
rdisplay->restore_cursor(0,0);
rdisplay->init_cursor = init_cursor;
rdisplay->select_cursor = select_cursor;
rdisplay->show_cursor = NULL;
rdisplay->move_cursor = move_cursor;
rdisplay->restore_cursor = restore_cursor;
select_cursor(rdisplay->cursor);
radeon_show_cursor();

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@@ -82,7 +82,7 @@ cursor_t* __stdcall select_cursor_kms(cursor_t *cursor)
if (ASIC_IS_AVIVO(rdev))
WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, gpu_addr);
else {
radeon_crtc->legacy_cursor_offset = gpu_addr - radeon_crtc->legacy_display_base_addr;
radeon_crtc->legacy_cursor_offset = gpu_addr - rdev->mc.vram_location;
/* offset is from DISP(2)_BASE_ADDRESS */
WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, radeon_crtc->legacy_cursor_offset);
}
@@ -148,7 +148,7 @@ void __stdcall move_cursor_kms(cursor_t *cursor, int x, int y)
y *= 2;
WREG32(RADEON_CUR_HORZ_VERT_OFF + radeon_crtc->crtc_offset,
(RADEON_CUR_LOCK | (hot_x << 16) | (hot_y << 16)));
(RADEON_CUR_LOCK | (hot_x << 16) | hot_y ));
WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset,
(RADEON_CUR_LOCK | (x << 16) | y));