hardware cursor test
git-svn-id: svn://kolibrios.org@3934 a494cfbc-eb01-0410-851d-a64ba20cac60
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@ -1,6 +1,6 @@
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; ;;
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;; Copyright (C) 2010 KolibriOS team. All rights reserved. ;;
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;; Copyright (C) 2010-13 KolibriOS team. All rights reserved. ;;
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;; Distributed under terms of the GNU General Public License ;;
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;; ;;
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;; HT.inc ;; ;;
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@ -113,9 +113,8 @@ fusion_pcie_init:
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xchg dl, al
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mov dword[mmio_pcie_cfg_addr-OS_BASE], eax ; store the physical address
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mov ecx, edx
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and dl, 1
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jz $ ; bit[0] = 1 means no PCIe mapping allowed. Stop.
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shr cl, 2 ; ecx = log2(number of buses)
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shr cl, 2
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mov word[PCIe_bus_range-OS_BASE], cx
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sub cl, 2
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jae @f
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@ -158,19 +157,35 @@ fusion_pcie_init:
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create_mmio_pte:
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mov ecx, mmio_pte ; physical address
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or ecx, (PG_NOCACHE + PG_SHARED + PG_SW)
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or ecx, (PG_NOCACHE + PG_SHARED + PG_UW)
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mov ebx, FUSION_MMIO ; linear address
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shr ebx, 20
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add ebx, (sys_pgdir - OS_BASE) ; PgDir entry @
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mov dword[ebx], ecx ; Fusion MMIO tables
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; ---- short page mapping ----
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; ---- map APIC regs ----
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.map_apic_mmio:
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mov ecx, 0x01B ; APIC BAR
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rdmsr
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and eax, 0xFFFFF000 ; physical address
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or eax, (PG_NOCACHE + PG_SHARED + PG_SW)
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mov dword[mmio_pte + 0], eax
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or eax, (PG_NOCACHE + PG_SHARED + PG_UW)
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mov ebx, mmio_pte
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mov [ebx], eax
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; ---- map GPU MMRegs ----
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.map_gpu_mmr:
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mov eax, [mmio_pcie_cfg_addr-OS_BASE] ; PCIe space
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add eax, 0x08018 ; b:0, d:1, f:0, reg=18
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mov eax, [eax]
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xor al, al ; physical address
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or eax, (PG_NOCACHE + PG_SHARED + PG_UW)
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@@:
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add bl, 4
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mov [ebx], eax
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add eax, 0x01000
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cmp bl, 16*4 ; map 15 pages
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jb @b
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ret ; <<< OK >>>
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@ -308,6 +323,7 @@ apic_data:
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.counter dd ?
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.ticks dd ?
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.t_freq dd ?
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.gpu_r6998 dd ?
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endg
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apic_timer_reset:
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@ -321,8 +337,48 @@ apic_timer_reset:
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mov edx, [ebx]
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and edx, 0xFFFEFF00
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or edx, 0x0002003F ; int vector + restart
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mov [ebx], edx
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;-- mov [ebx], edx
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mov dword [LAPIC_BAR + 0x380], eax ; load APICTIC
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; ret
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init_hw_cursor:
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call alloc_page ; eax = phys. addr
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push eax
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or eax, (PG_NOCACHE + PG_SHARED + PG_UW) ; i like dirty hacks
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mov [mmio_pte + OS_BASE + 15*4], eax ; mapped to the end of GPU MMRegs
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mov edi, GPU_CURSOR ; lin. addr
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invlpg [edi]
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xor ecx, ecx
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.fill64pix:
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xor ebx, ebx
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mov eax, 0x80000000 ; black, non-transparent
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.check_pix:
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cmp ebx, ecx
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jbe @f
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xor eax, eax ; transparent
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@@:
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mov [edi + ebx*4], eax
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inc ebx
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cmp bl, 64
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jb .check_pix
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inc ecx
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cmp ecx, 16
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je @f
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add edi, 64*4 ; new line
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jmp .fill64pix
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@@:
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pop eax
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mov dword[GPU_MMR + 0x0699C], eax ; cur_surface_addr
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mov dword[GPU_MMR + 0x069A0], 0x000F000F ; cur_size = 16x16
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mov dword[GPU_MMR + 0x069A4], 0 ; cur_adr_hi
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mov dword[GPU_MMR + 0x069A8], 0x02000100 ; cur_pos = 512,256
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mov dword[GPU_MMR + 0x069AC], 0 ; cur_hotspot = 0,0
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mov dword[GPU_MMR + 0x06998], 0x00000301 ; set it!
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ret
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@ -322,7 +322,9 @@ PCIe_CONFIG_SPACE equ 0xF0000000
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USER_DMA_BUFFER equ 0xFD000000 ; linear addr.
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USER_DMA_SIZE equ 0x00800000
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FUSION_MMIO equ 0xFD800000
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LAPIC_BAR equ 0xFD800000 ; ==
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LAPIC_BAR equ 0xFD800000 ; 1 page
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GPU_MMR equ 0xFD801000 ; 14 pages
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GPU_CURSOR equ 0xFD80F000 ; 1 page
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page_tabs equ 0xFDC00000
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app_page_tabs equ 0xFDC00000
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