ddk: update includes
git-svn-id: svn://kolibrios.org@5272 a494cfbc-eb01-0410-851d-a64ba20cac60
This commit is contained in:
Sergey Semyonov (Serge)
109
drivers/include/asm/preempt.h
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109
drivers/include/asm/preempt.h
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#ifndef __ASM_PREEMPT_H
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#define __ASM_PREEMPT_H
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#include <asm/rmwcc.h>
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#include <asm/percpu.h>
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//#include <linux/thread_info.h>
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DECLARE_PER_CPU(int, __preempt_count);
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/*
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* We use the PREEMPT_NEED_RESCHED bit as an inverted NEED_RESCHED such
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* that a decrement hitting 0 means we can and should reschedule.
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*/
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#define PREEMPT_ENABLED (0 + PREEMPT_NEED_RESCHED)
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/*
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* We mask the PREEMPT_NEED_RESCHED bit so as not to confuse all current users
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* that think a non-zero value indicates we cannot preempt.
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*/
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static __always_inline int preempt_count(void)
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{
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return raw_cpu_read_4(__preempt_count) & ~PREEMPT_NEED_RESCHED;
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}
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static __always_inline void preempt_count_set(int pc)
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{
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raw_cpu_write_4(__preempt_count, pc);
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}
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/*
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* must be macros to avoid header recursion hell
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*/
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#define init_task_preempt_count(p) do { \
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task_thread_info(p)->saved_preempt_count = PREEMPT_DISABLED; \
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} while (0)
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#define init_idle_preempt_count(p, cpu) do { \
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task_thread_info(p)->saved_preempt_count = PREEMPT_ENABLED; \
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per_cpu(__preempt_count, (cpu)) = PREEMPT_ENABLED; \
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} while (0)
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/*
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* We fold the NEED_RESCHED bit into the preempt count such that
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* preempt_enable() can decrement and test for needing to reschedule with a
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* single instruction.
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*
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* We invert the actual bit, so that when the decrement hits 0 we know we both
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* need to resched (the bit is cleared) and can resched (no preempt count).
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*/
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static __always_inline void set_preempt_need_resched(void)
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{
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raw_cpu_and_4(__preempt_count, ~PREEMPT_NEED_RESCHED);
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}
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static __always_inline void clear_preempt_need_resched(void)
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{
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raw_cpu_or_4(__preempt_count, PREEMPT_NEED_RESCHED);
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}
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static __always_inline bool test_preempt_need_resched(void)
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{
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return !(raw_cpu_read_4(__preempt_count) & PREEMPT_NEED_RESCHED);
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}
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/*
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* The various preempt_count add/sub methods
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*/
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static __always_inline void __preempt_count_add(int val)
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{
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raw_cpu_add_4(__preempt_count, val);
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}
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static __always_inline void __preempt_count_sub(int val)
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{
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raw_cpu_add_4(__preempt_count, -val);
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}
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/*
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* Because we keep PREEMPT_NEED_RESCHED set when we do _not_ need to reschedule
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* a decrement which hits zero means we have no preempt_count and should
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* reschedule.
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*/
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static __always_inline bool __preempt_count_dec_and_test(void)
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{
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GEN_UNARY_RMWcc("decl", __preempt_count, __percpu_arg(0), "e");
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}
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/*
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* Returns true when we need to resched and can (barring IRQ state).
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*/
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static __always_inline bool should_resched(void)
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{
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return unlikely(!raw_cpu_read_4(__preempt_count));
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}
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#ifdef CONFIG_PREEMPT
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extern asmlinkage void ___preempt_schedule(void);
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# define __preempt_schedule() asm ("call ___preempt_schedule")
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extern asmlinkage void preempt_schedule(void);
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# ifdef CONFIG_CONTEXT_TRACKING
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extern asmlinkage void ___preempt_schedule_context(void);
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# define __preempt_schedule_context() asm ("call ___preempt_schedule_context")
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extern asmlinkage void preempt_schedule_context(void);
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# endif
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#endif
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#endif /* __ASM_PREEMPT_H */
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225
drivers/include/asm/rwsem.h
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225
drivers/include/asm/rwsem.h
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/* rwsem.h: R/W semaphores implemented using XADD/CMPXCHG for i486+
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*
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* Written by David Howells (dhowells@redhat.com).
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*
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* Derived from asm-x86/semaphore.h
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*
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*
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* The MSW of the count is the negated number of active writers and waiting
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* lockers, and the LSW is the total number of active locks
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*
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* The lock count is initialized to 0 (no active and no waiting lockers).
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*
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* When a writer subtracts WRITE_BIAS, it'll get 0xffff0001 for the case of an
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* uncontended lock. This can be determined because XADD returns the old value.
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* Readers increment by 1 and see a positive value when uncontended, negative
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* if there are writers (and maybe) readers waiting (in which case it goes to
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* sleep).
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*
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* The value of WAITING_BIAS supports up to 32766 waiting processes. This can
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* be extended to 65534 by manually checking the whole MSW rather than relying
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* on the S flag.
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*
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* The value of ACTIVE_BIAS supports up to 65535 active processes.
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*
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* This should be totally fair - if anything is waiting, a process that wants a
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* lock will go to the back of the queue. When the currently active lock is
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* released, if there's a writer at the front of the queue, then that and only
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* that will be woken up; if there's a bunch of consequtive readers at the
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* front, then they'll all be woken up, but no other readers will be.
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*/
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#ifndef _ASM_X86_RWSEM_H
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#define _ASM_X86_RWSEM_H
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#ifndef _LINUX_RWSEM_H
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#error "please don't include asm/rwsem.h directly, use linux/rwsem.h instead"
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#endif
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#ifdef __KERNEL__
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#include <asm/asm.h>
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/*
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* The bias values and the counter type limits the number of
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* potential readers/writers to 32767 for 32 bits and 2147483647
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* for 64 bits.
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*/
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#ifdef CONFIG_X86_64
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# define RWSEM_ACTIVE_MASK 0xffffffffL
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#else
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# define RWSEM_ACTIVE_MASK 0x0000ffffL
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#endif
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#define RWSEM_UNLOCKED_VALUE 0x00000000L
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#define RWSEM_ACTIVE_BIAS 0x00000001L
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#define RWSEM_WAITING_BIAS (-RWSEM_ACTIVE_MASK-1)
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#define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS
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#define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
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/*
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* lock for reading
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*/
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static inline void __down_read(struct rw_semaphore *sem)
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{
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asm volatile("# beginning down_read\n\t"
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LOCK_PREFIX _ASM_INC "(%1)\n\t"
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/* adds 0x00000001 */
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" jns 1f\n"
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" call call_rwsem_down_read_failed\n"
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"1:\n\t"
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"# ending down_read\n\t"
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: "+m" (sem->count)
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: "a" (sem)
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: "memory", "cc");
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}
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/*
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* trylock for reading -- returns 1 if successful, 0 if contention
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*/
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static inline int __down_read_trylock(struct rw_semaphore *sem)
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{
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long result, tmp;
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asm volatile("# beginning __down_read_trylock\n\t"
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" mov %0,%1\n\t"
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"1:\n\t"
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" mov %1,%2\n\t"
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" add %3,%2\n\t"
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" jle 2f\n\t"
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LOCK_PREFIX " cmpxchg %2,%0\n\t"
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" jnz 1b\n\t"
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"2:\n\t"
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"# ending __down_read_trylock\n\t"
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: "+m" (sem->count), "=&a" (result), "=&r" (tmp)
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: "i" (RWSEM_ACTIVE_READ_BIAS)
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: "memory", "cc");
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return result >= 0 ? 1 : 0;
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}
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/*
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* lock for writing
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*/
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static inline void __down_write_nested(struct rw_semaphore *sem, int subclass)
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{
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long tmp;
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asm volatile("# beginning down_write\n\t"
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LOCK_PREFIX " xadd %1,(%2)\n\t"
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/* adds 0xffff0001, returns the old value */
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" test " __ASM_SEL(%w1,%k1) "," __ASM_SEL(%w1,%k1) "\n\t"
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/* was the active mask 0 before? */
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" jz 1f\n"
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" call call_rwsem_down_write_failed\n"
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"1:\n"
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"# ending down_write"
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: "+m" (sem->count), "=d" (tmp)
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: "a" (sem), "1" (RWSEM_ACTIVE_WRITE_BIAS)
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: "memory", "cc");
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}
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static inline void __down_write(struct rw_semaphore *sem)
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{
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__down_write_nested(sem, 0);
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}
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/*
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* trylock for writing -- returns 1 if successful, 0 if contention
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*/
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static inline int __down_write_trylock(struct rw_semaphore *sem)
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{
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long result, tmp;
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asm volatile("# beginning __down_write_trylock\n\t"
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" mov %0,%1\n\t"
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"1:\n\t"
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" test " __ASM_SEL(%w1,%k1) "," __ASM_SEL(%w1,%k1) "\n\t"
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/* was the active mask 0 before? */
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" jnz 2f\n\t"
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" mov %1,%2\n\t"
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" add %3,%2\n\t"
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LOCK_PREFIX " cmpxchg %2,%0\n\t"
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" jnz 1b\n\t"
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"2:\n\t"
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" sete %b1\n\t"
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" movzbl %b1, %k1\n\t"
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"# ending __down_write_trylock\n\t"
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: "+m" (sem->count), "=&a" (result), "=&r" (tmp)
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: "er" (RWSEM_ACTIVE_WRITE_BIAS)
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: "memory", "cc");
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return result;
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}
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/*
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* unlock after reading
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*/
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static inline void __up_read(struct rw_semaphore *sem)
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{
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long tmp;
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asm volatile("# beginning __up_read\n\t"
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LOCK_PREFIX " xadd %1,(%2)\n\t"
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/* subtracts 1, returns the old value */
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" jns 1f\n\t"
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" call call_rwsem_wake\n" /* expects old value in %edx */
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"1:\n"
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"# ending __up_read\n"
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: "+m" (sem->count), "=d" (tmp)
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: "a" (sem), "1" (-RWSEM_ACTIVE_READ_BIAS)
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: "memory", "cc");
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}
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/*
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* unlock after writing
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*/
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static inline void __up_write(struct rw_semaphore *sem)
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{
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long tmp;
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asm volatile("# beginning __up_write\n\t"
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LOCK_PREFIX " xadd %1,(%2)\n\t"
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/* subtracts 0xffff0001, returns the old value */
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" jns 1f\n\t"
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" call call_rwsem_wake\n" /* expects old value in %edx */
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"1:\n\t"
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"# ending __up_write\n"
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: "+m" (sem->count), "=d" (tmp)
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: "a" (sem), "1" (-RWSEM_ACTIVE_WRITE_BIAS)
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: "memory", "cc");
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}
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/*
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* downgrade write lock to read lock
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*/
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static inline void __downgrade_write(struct rw_semaphore *sem)
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{
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asm volatile("# beginning __downgrade_write\n\t"
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LOCK_PREFIX _ASM_ADD "%2,(%1)\n\t"
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/*
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* transitions 0xZZZZ0001 -> 0xYYYY0001 (i386)
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* 0xZZZZZZZZ00000001 -> 0xYYYYYYYY00000001 (x86_64)
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*/
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" jns 1f\n\t"
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" call call_rwsem_downgrade_wake\n"
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"1:\n\t"
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"# ending __downgrade_write\n"
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: "+m" (sem->count)
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: "a" (sem), "er" (-RWSEM_WAITING_BIAS)
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: "memory", "cc");
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}
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/*
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* implement atomic add functionality
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*/
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static inline void rwsem_atomic_add(long delta, struct rw_semaphore *sem)
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{
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asm volatile(LOCK_PREFIX _ASM_ADD "%1,%0"
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: "+m" (sem->count)
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: "er" (delta));
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}
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/*
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* implement exchange and add functionality
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*/
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static inline long rwsem_atomic_update(long delta, struct rw_semaphore *sem)
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{
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return delta + xadd(&sem->count, delta);
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}
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#endif /* __KERNEL__ */
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#endif /* _ASM_X86_RWSEM_H */
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