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Replaced all 'equ' with '=' for network drivers, where possible.

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git-svn-id: svn://kolibrios.org@2852 a494cfbc-eb01-0410-851d-a64ba20cac60
This commit is contained in:
hidnplayr 2012-07-09 11:31:56 +00:00
parent bf6bf90871
commit fd138cc362
11 changed files with 2075 additions and 2075 deletions
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326
kernel/branches/net/drivers/3c59x.asm
View File

@ -82,16 +82,16 @@
format MS COFF
API_VERSION equ 0x01000100
DRIVER_VERSION equ 5
API_VERSION = 0x01000100
DRIVER_VERSION = 5
MAX_DEVICES equ 16
FORCE_FD equ 0 ; forcing full duplex mode makes sense at some cards and link types
PROMISCIOUS equ 0 ; enables promiscous mode
MAX_DEVICES = 16
FORCE_FD = 0 ; forcing full duplex mode makes sense at some cards and link types
PROMISCIOUS = 0 ; enables promiscous mode
DEBUG equ 1
__DEBUG__ equ 1
__DEBUG_LEVEL__ equ 1
DEBUG = 1
__DEBUG__ = 1
__DEBUG_LEVEL__ = 1
include 'proc32.inc'
include 'imports.inc'
@ -133,207 +133,207 @@ virtual at 0
end virtual
; Ethernet frame symbols
ETH_ALEN equ 6
ETH_HLEN equ (2*ETH_ALEN+2)
ETH_ZLEN equ 60 ; 60 + 4bytes auto payload for
ETH_ALEN = 6
ETH_HLEN = (2*ETH_ALEN+2)
ETH_ZLEN = 60 ; 60 + 4bytes auto payload for
; mininmum 64bytes frame length
; Registers
REG_POWER_MGMT_CTRL equ 0x7c
REG_UP_LIST_PTR equ 0x38
REG_UP_PKT_STATUS equ 0x30
REG_TX_FREE_THRESH equ 0x2f
REG_DN_LIST_PTR equ 0x24
REG_DMA_CTRL equ 0x20
REG_TX_STATUS equ 0x1b
REG_RX_STATUS equ 0x18
REG_TX_DATA equ 0x10
REG_POWER_MGMT_CTRL = 0x7c
REG_UP_LIST_PTR = 0x38
REG_UP_PKT_STATUS = 0x30
REG_TX_FREE_THRESH = 0x2f
REG_DN_LIST_PTR = 0x24
REG_DMA_CTRL = 0x20
REG_TX_STATUS = 0x1b
REG_RX_STATUS = 0x18
REG_TX_DATA = 0x10
; Common window registers
REG_INT_STATUS equ 0xe
REG_COMMAND equ 0xe
REG_INT_STATUS = 0xe
REG_COMMAND = 0xe
; Register window 7
REG_MASTER_STATUS equ 0xc
REG_POWER_MGMT_EVENT equ 0xc
REG_MASTER_LEN equ 0x6
REG_VLAN_ETHER_TYPE equ 0x4
REG_VLAN_MASK equ 0x0
REG_MASTER_ADDRESS equ 0x0
REG_MASTER_STATUS = 0xc
REG_POWER_MGMT_EVENT = 0xc
REG_MASTER_LEN = 0x6
REG_VLAN_ETHER_TYPE = 0x4
REG_VLAN_MASK = 0x0
REG_MASTER_ADDRESS = 0x0
; Register window 6
REG_BYTES_XMITTED_OK equ 0xc
REG_BYTES_RCVD_OK equ 0xa
REG_UPPER_FRAMES_OK equ 0x9
REG_FRAMES_DEFERRED equ 0x8
REG_FRAMES_RCVD_OK equ 0x7
REG_FRAMES_XMITTED_OK equ 0x6
REG_RX_OVERRUNS equ 0x5
REG_LATE_COLLISIONS equ 0x4
REG_SINGLE_COLLISIONS equ 0x3
REG_MULTIPLE_COLLISIONS equ 0x2
REG_SQE_ERRORS equ 0x1
REG_CARRIER_LOST equ 0x0
REG_BYTES_XMITTED_OK = 0xc
REG_BYTES_RCVD_OK = 0xa
REG_UPPER_FRAMES_OK = 0x9
REG_FRAMES_DEFERRED = 0x8
REG_FRAMES_RCVD_OK = 0x7
REG_FRAMES_XMITTED_OK = 0x6
REG_RX_OVERRUNS = 0x5
REG_LATE_COLLISIONS = 0x4
REG_SINGLE_COLLISIONS = 0x3
REG_MULTIPLE_COLLISIONS = 0x2
REG_SQE_ERRORS = 0x1
REG_CARRIER_LOST = 0x0
; Register window 5
REG_INDICATION_ENABLE equ 0xc
REG_INTERRUPT_ENABLE equ 0xa
REG_TX_RECLAIM_THRESH equ 0x9
REG_RX_FILTER equ 0x8
REG_RX_EARLY_THRESH equ 0x6
REG_TX_START_THRESH equ 0x0
REG_INDICATION_ENABLE = 0xc
REG_INTERRUPT_ENABLE = 0xa
REG_TX_RECLAIM_THRESH = 0x9
REG_RX_FILTER = 0x8
REG_RX_EARLY_THRESH = 0x6
REG_TX_START_THRESH = 0x0
; Register window 4
REG_UPPER_BYTES_OK equ 0xe
REG_BAD_SSD equ 0xc
REG_MEDIA_STATUS equ 0xa
REG_PHYSICAL_MGMT equ 0x8
REG_NETWORK_DIAGNOSTIC equ 0x6
REG_FIFO_DIAGNOSTIC equ 0x4
REG_VCO_DIAGNOSTIC equ 0x2 ; may not supported
REG_UPPER_BYTES_OK = 0xe
REG_BAD_SSD = 0xc
REG_MEDIA_STATUS = 0xa
REG_PHYSICAL_MGMT = 0x8
REG_NETWORK_DIAGNOSTIC = 0x6
REG_FIFO_DIAGNOSTIC = 0x4
REG_VCO_DIAGNOSTIC = 0x2 ; may not supported
; Bits in register window 4
BIT_AUTOSELECT equ 24
BIT_AUTOSELECT = 24
; Register window 3
REG_TX_FREE equ 0xc
REG_RX_FREE equ 0xa
REG_MEDIA_OPTIONS equ 0x8
REG_MAC_CONTROL equ 0x6
REG_MAX_PKT_SIZE equ 0x4
REG_INTERNAL_CONFIG equ 0x0
REG_TX_FREE = 0xc
REG_RX_FREE = 0xa
REG_MEDIA_OPTIONS = 0x8
REG_MAC_CONTROL = 0x6
REG_MAX_PKT_SIZE = 0x4
REG_INTERNAL_CONFIG = 0x0
; Register window 2
REG_RESET_OPTIONS equ 0xc
REG_STATION_MASK_HI equ 0xa
REG_STATION_MASK_MID equ 0x8
REG_STATION_MASK_LO equ 0x6
REG_STATION_ADDRESS_HI equ 0x4
REG_STATION_ADDRESS_MID equ 0x2
REG_STATION_ADDRESS_LO equ 0x0
REG_RESET_OPTIONS = 0xc
REG_STATION_MASK_HI = 0xa
REG_STATION_MASK_MID = 0x8
REG_STATION_MASK_LO = 0x6
REG_STATION_ADDRESS_HI = 0x4
REG_STATION_ADDRESS_MID = 0x2
REG_STATION_ADDRESS_LO = 0x0
; Register window 1
REG_TRIGGER_BITS equ 0xc
REG_SOS_BITS equ 0xa
REG_WAKE_ON_TIMER equ 0x8
REG_SMB_RXBYTES equ 0x7
REG_SMB_DIAG equ 0x5
REG_SMB_ARB equ 0x4
REG_SMB_STATUS equ 0x2
REG_SMB_ADDRESS equ 0x1
REG_SMB_FIFO_DATA equ 0x0
REG_TRIGGER_BITS = 0xc
REG_SOS_BITS = 0xa
REG_WAKE_ON_TIMER = 0x8
REG_SMB_RXBYTES = 0x7
REG_SMB_DIAG = 0x5
REG_SMB_ARB = 0x4
REG_SMB_STATUS = 0x2
REG_SMB_ADDRESS = 0x1
REG_SMB_FIFO_DATA = 0x0
; Register window 0
REG_EEPROM_DATA equ 0xc
REG_EEPROM_COMMAND equ 0xa
REG_BIOS_ROM_DATA equ 0x8
REG_BIOS_ROM_ADDR equ 0x4
REG_EEPROM_DATA = 0xc
REG_EEPROM_COMMAND = 0xa
REG_BIOS_ROM_DATA = 0x8
REG_BIOS_ROM_ADDR = 0x4
; Physical management bits
BIT_MGMT_DIR equ 2 ; drive with the data written in mgmtData
BIT_MGMT_DATA equ 1 ; MII management data bit
BIT_MGMT_CLK equ 0 ; MII management clock
BIT_MGMT_DIR = 2 ; drive with the data written in mgmtData
BIT_MGMT_DATA = 1 ; MII management data bit
BIT_MGMT_CLK = 0 ; MII management clock
; MII commands
MII_CMD_MASK equ (1111b shl 10)
MII_CMD_READ equ (0110b shl 10)
MII_CMD_WRITE equ (0101b shl 10)
MII_CMD_MASK = (1111b shl 10)
MII_CMD_READ = (0110b shl 10)
MII_CMD_WRITE = (0101b shl 10)
; MII registers
REG_MII_BMCR equ 0 ; basic mode control register
REG_MII_BMSR equ 1 ; basic mode status register
REG_MII_ANAR equ 4 ; auto negotiation advertisement register
REG_MII_ANLPAR equ 5 ; auto negotiation link partner ability register
REG_MII_ANER equ 6 ; auto negotiation expansion register
REG_MII_BMCR = 0 ; basic mode control register
REG_MII_BMSR = 1 ; basic mode status register
REG_MII_ANAR = 4 ; auto negotiation advertisement register
REG_MII_ANLPAR = 5 ; auto negotiation link partner ability register
REG_MII_ANER = 6 ; auto negotiation expansion register
; MII bits
BIT_MII_AUTONEG_COMPLETE equ 5 ; auto-negotiation complete
BIT_MII_PREAMBLE_SUPPRESSION equ 6
BIT_MII_AUTONEG_COMPLETE = 5 ; auto-negotiation complete
BIT_MII_PREAMBLE_SUPPRESSION = 6
; eeprom bits and commands
EEPROM_CMD_READ equ 0x80
EEPROM_BIT_BUSY equ 15
EEPROM_CMD_READ = 0x80
EEPROM_BIT_BUSY = 15
; eeprom registers
EEPROM_REG_OEM_NODE_ADDR equ 0xa
EEPROM_REG_CAPABILITIES equ 0x10
EEPROM_REG_OEM_NODE_ADDR = 0xa
EEPROM_REG_CAPABILITIES = 0x10
; Commands for command register
SELECT_REGISTER_WINDOW equ (1 shl 11)
SELECT_REGISTER_WINDOW = (1 shl 11)
IS_VORTEX equ 0x1
IS_BOOMERANG equ 0x2
IS_CYCLONE equ 0x4
IS_TORNADO equ 0x8
EEPROM_8BIT equ 0x10
HAS_PWR_CTRL equ 0x20
HAS_MII equ 0x40
HAS_NWAY equ 0x80
HAS_CB_FNS equ 0x100
INVERT_MII_PWR equ 0x200
INVERT_LED_PWR equ 0x400
MAX_COLLISION_RESET equ 0x800
EEPROM_OFFSET equ 0x1000
HAS_HWCKSM equ 0x2000
EXTRA_PREAMBLE equ 0x4000
IS_VORTEX = 0x1
IS_BOOMERANG = 0x2
IS_CYCLONE = 0x4
IS_TORNADO = 0x8
EEPROM_8BIT = 0x10
HAS_PWR_CTRL = 0x20
HAS_MII = 0x40
HAS_NWAY = 0x80
HAS_CB_FNS = 0x100
INVERT_MII_PWR = 0x200
INVERT_LED_PWR = 0x400
MAX_COLLISION_RESET = 0x800
EEPROM_OFFSET = 0x1000
HAS_HWCKSM = 0x2000
EXTRA_PREAMBLE = 0x4000
; Status
IntLatch equ 0x0001
HostError equ 0x0002
TxComplete equ 0x0004
TxAvailable equ 0x0008
RxComplete equ 0x0010
RxEarly equ 0x0020
IntReq equ 0x0040
StatsFull equ 0x0080
DMADone equ 0x0100
DownComplete equ 0x0200
UpComplete equ 0x0400
DMAInProgress equ 0x0800 ; 1 shl 11 (DMA controller is still busy)
CmdInProgress equ 0x1000 ; 1 shl 12 (EL3_CMD is still busy)
IntLatch = 0x0001
HostError = 0x0002
TxComplete = 0x0004
TxAvailable = 0x0008
RxComplete = 0x0010
RxEarly = 0x0020
IntReq = 0x0040
StatsFull = 0x0080
DMADone = 0x0100
DownComplete = 0x0200
UpComplete = 0x0400
DMAInProgress = 0x0800 ; 1 shl 11 (DMA controller is still busy)
CmdInProgress = 0x1000 ; 1 shl 12 (EL3_CMD is still busy)
S_5_INTS equ HostError + RxEarly + UpComplete + DownComplete ;+ TxComplete + RxComplete + TxAvailable
S_5_INTS = HostError + RxEarly + UpComplete + DownComplete ;+ TxComplete + RxComplete + TxAvailable
; Commands
TotalReset equ 0 shl 11
SelectWindow equ 1 shl 11
StartCoax equ 2 shl 11
RxDisable equ 3 shl 11
RxEnable equ 4 shl 11
RxReset equ 5 shl 11
UpStall equ 6 shl 11
UpUnstall equ (6 shl 11)+1
DownStall equ (6 shl 11)+2
DownUnstall equ (6 shl 11)+3
RxDiscard equ 8 shl 11
TxEnable equ 9 shl 11
TxDisable equ 10 shl 11
TxReset equ 11 shl 11
FakeIntr equ 12 shl 11
AckIntr equ 13 shl 11
SetIntrEnb equ 14 shl 11
SetStatusEnb equ 15 shl 11
SetRxFilter equ 16 shl 11
SetRxThreshold equ 17 shl 11
SetTxThreshold equ 18 shl 11
SetTxStart equ 19 shl 11
StartDMAUp equ 20 shl 11
StartDMADown equ (20 shl 11)+1
StatsEnable equ 21 shl 11
StatsDisable equ 22 shl 11
StopCoax equ 23 shl 11
SetFilterBit equ 25 shl 11
TotalReset = 0 shl 11
SelectWindow = 1 shl 11
StartCoax = 2 shl 11
RxDisable = 3 shl 11
RxEnable = 4 shl 11
RxReset = 5 shl 11
UpStall = 6 shl 11
UpUnstall = (6 shl 11)+1
DownStall = (6 shl 11)+2
DownUnstall = (6 shl 11)+3
RxDiscard = 8 shl 11
TxEnable = 9 shl 11
TxDisable = 10 shl 11
TxReset = 11 shl 11
FakeIntr = 12 shl 11
AckIntr = 13 shl 11
SetIntrEnb = 14 shl 11
SetStatusEnb = 15 shl 11
SetRxFilter = 16 shl 11
SetRxThreshold = 17 shl 11
SetTxThreshold = 18 shl 11
SetTxStart = 19 shl 11
StartDMAUp = 20 shl 11
StartDMADown = (20 shl 11)+1
StatsEnable = 21 shl 11
StatsDisable = 22 shl 11
StopCoax = 23 shl 11
SetFilterBit = 25 shl 11
; Rx mode bits
RxStation equ 1
RxMulticast equ 2
RxBroadcast equ 4
RxProm equ 8
RxStation = 1
RxMulticast = 2
RxBroadcast = 4
RxProm = 8
; RX/TX buffers sizes
MAX_ETH_PKT_SIZE equ 1536 ; max packet size
NUM_RX_DESC equ 4 ; a power of 2 number
NUM_TX_DESC equ 4 ; a power of 2 number
MAX_ETH_FRAME_SIZE equ 1520 ; size of ethernet frame + bytes alignment
MAX_ETH_PKT_SIZE = 1536 ; max packet size
NUM_RX_DESC = 4 ; a power of 2 number
NUM_TX_DESC = 4 ; a power of 2 number
MAX_ETH_FRAME_SIZE = 1520 ; size of ethernet frame + bytes alignment
virtual at ebx

202
kernel/branches/net/drivers/R6040.asm
View File

@ -17,33 +17,33 @@
format MS COFF
API_VERSION equ 0x01000100
DRIVER_VERSION equ 5
API_VERSION = 0x01000100
DRIVER_VERSION = 5
MAX_DEVICES equ 16
MAX_DEVICES = 16
DEBUG equ 1
__DEBUG__ equ 1
__DEBUG_LEVEL__ equ 2
DEBUG = 1
__DEBUG__ = 1
__DEBUG_LEVEL__ = 2
W_MAX_TIMEOUT equ 0x0FFF ; max time out delay time
W_MAX_TIMEOUT = 0x0FFF ; max time out delay time
TX_TIMEOUT equ 6000 ; Time before concluding the transmitter is hung, in ms
TX_TIMEOUT = 6000 ; Time before concluding the transmitter is hung, in ms
TX_RING_SIZE equ 4 ; RING sizes must be a power of 2
RX_RING_SIZE equ 4
TX_RING_SIZE = 4 ; RING sizes must be a power of 2
RX_RING_SIZE = 4
RX_BUF_LEN_IDX equ 3 ; 0==8K, 1==16K, 2==32K, 3==64K
RX_BUF_LEN_IDX = 3 ; 0==8K, 1==16K, 2==32K, 3==64K
; Threshold is bytes transferred to chip before transmission starts.
TX_FIFO_THRESH equ 256 ; In bytes, rounded down to 32 byte units.
TX_FIFO_THRESH = 256 ; In bytes, rounded down to 32 byte units.
; The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024.
RX_FIFO_THRESH equ 4 ; Rx buffer level before first PCI xfer.
RX_DMA_BURST equ 4 ; Maximum PCI burst, '4' is 256 bytes
TX_DMA_BURST equ 4
RX_FIFO_THRESH = 4 ; Rx buffer level before first PCI xfer.
RX_DMA_BURST = 4 ; Maximum PCI burst, '4' is 256 bytes
TX_DMA_BURST = 4
@ -58,106 +58,106 @@ public version
; Operational parameters that usually are not changed.
PHY1_ADDR equ 1 ;For MAC1
PHY2_ADDR equ 3 ;For MAC2
PHY_MODE equ 0x3100 ;PHY CHIP Register 0
PHY_CAP equ 0x01E1 ;PHY CHIP Register 4
PHY1_ADDR = 1 ;For MAC1
PHY2_ADDR = 3 ;For MAC2
PHY_MODE = 0x3100 ;PHY CHIP Register 0
PHY_CAP = 0x01E1 ;PHY CHIP Register 4
;**************************************************************************
; RDC R6040 Register Definitions
;**************************************************************************
MCR0 equ 0x00 ;Control register 0
MCR1 equ 0x01 ;Control register 1
MAC_RST equ 0x0001 ;Reset the MAC
MBCR equ 0x08 ;Bus control
MT_ICR equ 0x0C ;TX interrupt control
MR_ICR equ 0x10 ;RX interrupt control
MTPR equ 0x14 ;TX poll command register
MR_BSR equ 0x18 ;RX buffer size
MR_DCR equ 0x1A ;RX descriptor control
MLSR equ 0x1C ;Last status
MMDIO equ 0x20 ;MDIO control register
MDIO_WRITE equ 0x4000 ;MDIO write
MDIO_READ equ 0x2000 ;MDIO read
MMRD equ 0x24 ;MDIO read data register
MMWD equ 0x28 ;MDIO write data register
MTD_SA0 equ 0x2C ;TX descriptor start address 0
MTD_SA1 equ 0x30 ;TX descriptor start address 1
MRD_SA0 equ 0x34 ;RX descriptor start address 0
MRD_SA1 equ 0x38 ;RX descriptor start address 1
MISR equ 0x3C ;Status register
MIER equ 0x40 ;INT enable register
MSK_INT equ 0x0000 ;Mask off interrupts
RX_FINISH equ 0x0001 ;RX finished
RX_NO_DESC equ 0x0002 ;No RX descriptor available
RX_FIFO_FULL equ 0x0004 ;RX FIFO full
RX_EARLY equ 0x0008 ;RX early
TX_FINISH equ 0x0010 ;TX finished
TX_EARLY equ 0x0080 ;TX early
EVENT_OVRFL equ 0x0100 ;Event counter overflow
LINK_CHANGED equ 0x0200 ;PHY link changed
ME_CISR equ 0x44 ;Event counter INT status
ME_CIER equ 0x48 ;Event counter INT enable
MR_CNT equ 0x50 ;Successfully received packet counter
ME_CNT0 equ 0x52 ;Event counter 0
ME_CNT1 equ 0x54 ;Event counter 1
ME_CNT2 equ 0x56 ;Event counter 2
ME_CNT3 equ 0x58 ;Event counter 3
MT_CNT equ 0x5A ;Successfully transmit packet counter
ME_CNT4 equ 0x5C ;Event counter 4
MP_CNT equ 0x5E ;Pause frame counter register
MAR0 equ 0x60 ;Hash table 0
MAR1 equ 0x62 ;Hash table 1
MAR2 equ 0x64 ;Hash table 2
MAR3 equ 0x66 ;Hash table 3
MID_0L equ 0x68 ;Multicast address MID0 Low
MID_0M equ 0x6A ;Multicast address MID0 Medium
MID_0H equ 0x6C ;Multicast address MID0 High
MID_1L equ 0x70 ;MID1 Low
MID_1M equ 0x72 ;MID1 Medium
MID_1H equ 0x74 ;MID1 High
MID_2L equ 0x78 ;MID2 Low
MID_2M equ 0x7A ;MID2 Medium
MID_2H equ 0x7C ;MID2 High
MID_3L equ 0x80 ;MID3 Low
MID_3M equ 0x82 ;MID3 Medium
MID_3H equ 0x84 ;MID3 High
PHY_CC equ 0x88 ;PHY status change configuration register
PHY_ST equ 0x8A ;PHY status register
MAC_SM equ 0xAC ;MAC status machine
MAC_ID equ 0xBE ;Identifier register
MCR0 = 0x00 ;Control register 0
MCR1 = 0x01 ;Control register 1
MAC_RST = 0x0001 ;Reset the MAC
MBCR = 0x08 ;Bus control
MT_ICR = 0x0C ;TX interrupt control
MR_ICR = 0x10 ;RX interrupt control
MTPR = 0x14 ;TX poll command register
MR_BSR = 0x18 ;RX buffer size
MR_DCR = 0x1A ;RX descriptor control
MLSR = 0x1C ;Last status
MMDIO = 0x20 ;MDIO control register
MDIO_WRITE = 0x4000 ;MDIO write
MDIO_READ = 0x2000 ;MDIO read
MMRD = 0x24 ;MDIO read data register
MMWD = 0x28 ;MDIO write data register
MTD_SA0 = 0x2C ;TX descriptor start address 0
MTD_SA1 = 0x30 ;TX descriptor start address 1
MRD_SA0 = 0x34 ;RX descriptor start address 0
MRD_SA1 = 0x38 ;RX descriptor start address 1
MISR = 0x3C ;Status register
MIER = 0x40 ;INT enable register
MSK_INT = 0x0000 ;Mask off interrupts
RX_FINISH = 0x0001 ;RX finished
RX_NO_DESC = 0x0002 ;No RX descriptor available
RX_FIFO_FULL = 0x0004 ;RX FIFO full
RX_EARLY = 0x0008 ;RX early
TX_FINISH = 0x0010 ;TX finished
TX_EARLY = 0x0080 ;TX early
EVENT_OVRFL = 0x0100 ;Event counter overflow
LINK_CHANGED = 0x0200 ;PHY link changed
ME_CISR = 0x44 ;Event counter INT status
ME_CIER = 0x48 ;Event counter INT enable
MR_CNT = 0x50 ;Successfully received packet counter
ME_CNT0 = 0x52 ;Event counter 0
ME_CNT1 = 0x54 ;Event counter 1
ME_CNT2 = 0x56 ;Event counter 2
ME_CNT3 = 0x58 ;Event counter 3
MT_CNT = 0x5A ;Successfully transmit packet counter
ME_CNT4 = 0x5C ;Event counter 4
MP_CNT = 0x5E ;Pause frame counter register
MAR0 = 0x60 ;Hash table 0
MAR1 = 0x62 ;Hash table 1
MAR2 = 0x64 ;Hash table 2
MAR3 = 0x66 ;Hash table 3
MID_0L = 0x68 ;Multicast address MID0 Low
MID_0M = 0x6A ;Multicast address MID0 Medium
MID_0H = 0x6C ;Multicast address MID0 High
MID_1L = 0x70 ;MID1 Low
MID_1M = 0x72 ;MID1 Medium
MID_1H = 0x74 ;MID1 High
MID_2L = 0x78 ;MID2 Low
MID_2M = 0x7A ;MID2 Medium
MID_2H = 0x7C ;MID2 High
MID_3L = 0x80 ;MID3 Low
MID_3M = 0x82 ;MID3 Medium
MID_3H = 0x84 ;MID3 High
PHY_CC = 0x88 ;PHY status change configuration register
PHY_ST = 0x8A ;PHY status register
MAC_SM = 0xAC ;MAC status machine
MAC_ID = 0xBE ;Identifier register
MAX_BUF_SIZE equ 0x600 ;1536
MAX_BUF_SIZE = 0x600 ;1536
MBCR_DEFAULT equ 0x012A ;MAC Bus Control Register
MCAST_MAX equ 3 ;Max number multicast addresses to filter
MBCR_DEFAULT = 0x012A ;MAC Bus Control Register
MCAST_MAX = 3 ;Max number multicast addresses to filter
;Descriptor status
DSC_OWNER_MAC equ 0x8000 ;MAC is the owner of this descriptor
DSC_RX_OK equ 0x4000 ;RX was successfull
DSC_RX_ERR equ 0x0800 ;RX PHY error
DSC_RX_ERR_DRI equ 0x0400 ;RX dribble packet
DSC_RX_ERR_BUF equ 0x0200 ;RX length exceeds buffer size
DSC_RX_ERR_LONG equ 0x0100 ;RX length > maximum packet length
DSC_RX_ERR_RUNT equ 0x0080 ;RX packet length < 64 byte
DSC_RX_ERR_CRC equ 0x0040 ;RX CRC error
DSC_RX_BCAST equ 0x0020 ;RX broadcast (no error)
DSC_RX_MCAST equ 0x0010 ;RX multicast (no error)
DSC_RX_MCH_HIT equ 0x0008 ;RX multicast hit in hash table (no error)
DSC_RX_MIDH_HIT equ 0x0004 ;RX MID table hit (no error)
DSC_RX_IDX_MID_MASK equ 3 ;RX mask for the index of matched MIDx
DSC_OWNER_MAC = 0x8000 ;MAC is the owner of this descriptor
DSC_RX_OK = 0x4000 ;RX was successfull
DSC_RX_ERR = 0x0800 ;RX PHY error
DSC_RX_ERR_DRI = 0x0400 ;RX dribble packet
DSC_RX_ERR_BUF = 0x0200 ;RX length exceeds buffer size
DSC_RX_ERR_LONG = 0x0100 ;RX length > maximum packet length
DSC_RX_ERR_RUNT = 0x0080 ;RX packet length < 64 byte
DSC_RX_ERR_CRC = 0x0040 ;RX CRC error
DSC_RX_BCAST = 0x0020 ;RX broadcast (no error)
DSC_RX_MCAST = 0x0010 ;RX multicast (no error)
DSC_RX_MCH_HIT = 0x0008 ;RX multicast hit in hash table (no error)
DSC_RX_MIDH_HIT = 0x0004 ;RX MID table hit (no error)
DSC_RX_IDX_MID_MASK = 3 ;RX mask for the index of matched MIDx
;PHY settings
ICPLUS_PHY_ID equ 0x0243
ICPLUS_PHY_ID = 0x0243
RX_INTS equ RX_FIFO_FULL or RX_NO_DESC or RX_FINISH
TX_INTS equ TX_FINISH
INT_MASK equ RX_INTS or TX_INTS
RX_INTS = RX_FIFO_FULL or RX_NO_DESC or RX_FINISH
TX_INTS = TX_FINISH
INT_MASK = RX_INTS or TX_INTS
RX_BUF_LEN equ (8192 << RX_BUF_LEN_IDX) ; Size of the in-memory receive ring.
IO_SIZE equ 256 ; RDC MAC I/O Size
MAX_MAC equ 2 ; MAX RDC MAC
IO_SIZE = 256 ; RDC MAC I/O Size
MAX_MAC = 2 ; MAX RDC MAC
virtual at 0

156
kernel/branches/net/drivers/RTL8029.asm
View File

@ -18,14 +18,14 @@
format MS COFF
API_VERSION equ 0x01000100
DRIVER_VERSION equ 5
API_VERSION = 0x01000100
DRIVER_VERSION = 5
MAX_DEVICES equ 16
MAX_DEVICES = 16
DEBUG equ 1
__DEBUG__ equ 1
__DEBUG_LEVEL__ equ 1
DEBUG = 1
__DEBUG__ = 1
__DEBUG_LEVEL__ = 1
include 'proc32.inc'
include 'imports.inc'
@ -62,92 +62,92 @@ public START
public service_proc
public version
P0_PSTART equ 0x01
P0_PSTOP equ 0x02
P0_BOUND equ 0x03
P0_TSR equ 0x04
P0_TPSR equ 0x04
P0_TBCR0 equ 0x05
P0_TBCR1 equ 0x06
P0_ISR equ 0x07
P0_RSAR0 equ 0x08
P0_RSAR1 equ 0x09
P0_RBCR0 equ 0x0A
P0_RBCR1 equ 0x0B
P0_RSR equ 0x0C
P0_RCR equ 0x0C
P0_TCR equ 0x0D
P0_DCR equ 0x0E
P0_IMR equ 0x0F
P0_PSTART = 0x01
P0_PSTOP = 0x02
P0_BOUND = 0x03
P0_TSR = 0x04
P0_TPSR = 0x04
P0_TBCR0 = 0x05
P0_TBCR1 = 0x06
P0_ISR = 0x07
P0_RSAR0 = 0x08
P0_RSAR1 = 0x09
P0_RBCR0 = 0x0A
P0_RBCR1 = 0x0B
P0_RSR = 0x0C
P0_RCR = 0x0C
P0_TCR = 0x0D
P0_DCR = 0x0E
P0_IMR = 0x0F
P1_PAR0 equ 0x01
P1_PAR1 equ 0x02
P1_PAR2 equ 0x03
P1_PAR3 equ 0x04
P1_PAR4 equ 0x05
P1_PAR5 equ 0x06
P1_CURR equ 0x07
P1_MAR0 equ 0x08
P1_PAR0 = 0x01
P1_PAR1 = 0x02
P1_PAR2 = 0x03
P1_PAR3 = 0x04
P1_PAR4 = 0x05
P1_PAR5 = 0x06
P1_CURR = 0x07
P1_MAR0 = 0x08
CMD_PS0 equ 0x00 ; Page 0 select
CMD_PS1 equ 0x40 ; Page 1 select
CMD_PS2 equ 0x80 ; Page 2 select
CMD_RD2 equ 0x20 ; Remote DMA control
CMD_RD1 equ 0x10
CMD_RD0 equ 0x08
CMD_TXP equ 0x04 ; transmit packet
CMD_STA equ 0x02 ; start
CMD_STP equ 0x01 ; stop
CMD_PS0 = 0x00 ; Page 0 select
CMD_PS1 = 0x40 ; Page 1 select
CMD_PS2 = 0x80 ; Page 2 select
CMD_RD2 = 0x20 ; Remote DMA control
CMD_RD1 = 0x10
CMD_RD0 = 0x08
CMD_TXP = 0x04 ; transmit packet
CMD_STA = 0x02 ; start
CMD_STP = 0x01 ; stop
RCR_MON equ 0x20 ; monitor mode
RCR_MON = 0x20 ; monitor mode
DCR_FT1 equ 0x40
DCR_LS equ 0x08 ; Loopback select
DCR_WTS equ 0x01 ; Word transfer select
DCR_FT1 = 0x40
DCR_LS = 0x08 ; Loopback select
DCR_WTS = 0x01 ; Word transfer select
ISR_PRX equ 0x01 ; successful recv
ISR_PTX equ 0x02 ; successful xmit
ISR_RXE equ 0x04 ; receive error
ISR_TXE equ 0x08 ; transmit error
ISR_OVW equ 0x10 ; Overflow
ISR_CNT equ 0x20 ; Counter overflow
ISR_RDC equ 0x40 ; Remote DMA complete
ISR_RST equ 0x80 ; reset
ISR_PRX = 0x01 ; successful recv
ISR_PTX = 0x02 ; successful xmit
ISR_RXE = 0x04 ; receive error
ISR_TXE = 0x08 ; transmit error
ISR_OVW = 0x10 ; Overflow
ISR_CNT = 0x20 ; Counter overflow
ISR_RDC = 0x40 ; Remote DMA complete
ISR_RST = 0x80 ; reset
IRQ_MASK equ ISR_PRX ; + ISR_PTX + ISR_TXE
IRQ_MASK = ISR_PRX ; + ISR_PTX + ISR_TXE
RSTAT_PRX equ 0x01 ; successful recv
RSTAT_CRC equ 0x02 ; CRC error
RSTAT_FAE equ 0x04 ; Frame alignment error
RSTAT_OVER equ 0x08 ; FIFO overrun
RSTAT_PRX = 0x01 ; successful recv
RSTAT_CRC = 0x02 ; CRC error
RSTAT_FAE = 0x04 ; Frame alignment error
RSTAT_OVER = 0x08 ; FIFO overrun
TXBUF_SIZE equ 6
RXBUF_END equ 32
PAGE_SIZE equ 256
TXBUF_SIZE = 6
RXBUF_END = 32
PAGE_SIZE = 256
ETH_ALEN equ 6
ETH_HLEN equ 14
ETH_ZLEN equ 60
ETH_FRAME_LEN equ 1514
ETH_ALEN = 6
ETH_HLEN = 14
ETH_ZLEN = 60
ETH_FRAME_LEN = 1514
FLAG_PIO equ 0x01
FLAG_16BIT equ 0x02
ASIC_PIO equ 0
FLAG_PIO = 0x01
FLAG_16BIT = 0x02
ASIC_PIO = 0
VENDOR_NONE equ 0
VENDOR_WD equ 1
VENDOR_NOVELL equ 2
VENDOR_3COM equ 3
VENDOR_NONE = 0
VENDOR_WD = 1
VENDOR_NOVELL = 2
VENDOR_3COM = 3
NE_ASIC_OFFSET equ 0x10
NE_RESET equ 0x0F ; Used to reset card
NE_DATA equ 0x00 ; Used to read/write NIC mem
NE_ASIC_OFFSET = 0x10
NE_RESET = 0x0F ; Used to reset card
NE_DATA = 0x00 ; Used to read/write NIC mem
MEM_8192 equ 32
MEM_16384 equ 64
MEM_32768 equ 128
MEM_8192 = 32
MEM_16384 = 64
MEM_32768 = 128
ISA_MAX_ADDR equ 0x400
ISA_MAX_ADDR = 0x400

252
kernel/branches/net/drivers/RTL8139.asm
View File

@ -17,16 +17,16 @@
format MS COFF
API_VERSION equ 0x01000100
DRIVER_VERSION equ 5
API_VERSION = 0x01000100
DRIVER_VERSION = 5
MAX_DEVICES equ 16
MAX_DEVICES = 16
RBLEN equ 3 ; Receive buffer size: 0==8K 1==16k 2==32k 3==64k
RBLEN = 3 ; Receive buffer size: 0==8K 1==16k 2==32k 3==64k
DEBUG equ 1
__DEBUG__ equ 1
__DEBUG_LEVEL__ equ 2
DEBUG = 1
__DEBUG__ = 1
__DEBUG_LEVEL__ = 2
include 'proc32.inc'
include 'imports.inc'
@ -37,94 +37,94 @@ public START
public service_proc
public version
REG_IDR0 equ 0x00
REG_MAR0 equ 0x08 ; multicast filter register 0
REG_MAR4 equ 0x0c ; multicast filter register 4
REG_TSD0 equ 0x10 ; transmit status of descriptor
REG_TSAD0 equ 0x20 ; transmit start address of descriptor
REG_RBSTART equ 0x30 ; RxBuffer start address
REG_COMMAND equ 0x37 ; command register
REG_CAPR equ 0x38 ; current address of packet read (word) R/W
REG_IMR equ 0x3c ; interrupt mask register
REG_ISR equ 0x3e ; interrupt status register
REG_TXCONFIG equ 0x40 ; transmit configuration register
REG_RXCONFIG equ 0x44 ; receive configuration register 0
REG_MPC equ 0x4c ; missed packet counter
REG_9346CR equ 0x50 ; serial eeprom 93C46 command register
REG_CONFIG1 equ 0x52 ; configuration register 1
REG_MSR equ 0x58
REG_CONFIG4 equ 0x5a ; configuration register 4
REG_HLTCLK equ 0x5b ; undocumented halt clock register
REG_BMCR equ 0x62 ; basic mode control register
REG_ANAR equ 0x66 ; auto negotiation advertisement register
REG_9346CR_WE equ 11b SHL 6
REG_IDR0 = 0x00
REG_MAR0 = 0x08 ; multicast filter register 0
REG_MAR4 = 0x0c ; multicast filter register 4
REG_TSD0 = 0x10 ; transmit status of descriptor
REG_TSAD0 = 0x20 ; transmit start address of descriptor
REG_RBSTART = 0x30 ; RxBuffer start address
REG_COMMAND = 0x37 ; command register
REG_CAPR = 0x38 ; current address of packet read (word) R/W
REG_IMR = 0x3c ; interrupt mask register
REG_ISR = 0x3e ; interrupt status register
REG_TXCONFIG = 0x40 ; transmit configuration register
REG_RXCONFIG = 0x44 ; receive configuration register 0
REG_MPC = 0x4c ; missed packet counter
REG_9346CR = 0x50 ; serial eeprom 93C46 command register
REG_CONFIG1 = 0x52 ; configuration register 1
REG_MSR = 0x58
REG_CONFIG4 = 0x5a ; configuration register 4
REG_HLTCLK = 0x5b ; undocumented halt clock register
REG_BMCR = 0x62 ; basic mode control register
REG_ANAR = 0x66 ; auto negotiation advertisement register
REG_9346CR_WE = 11b SHL 6
BIT_RUNT equ 4 ; total packet length < 64 bytes
BIT_LONG equ 3 ; total packet length > 4k
BIT_CRC equ 2 ; crc error occured
BIT_FAE equ 1 ; frame alignment error occured
BIT_ROK equ 0 ; received packet is ok
BIT_RUNT = 4 ; total packet length < 64 bytes
BIT_LONG = 3 ; total packet length > 4k
BIT_CRC = 2 ; crc error occured
BIT_FAE = 1 ; frame alignment error occured
BIT_ROK = 0 ; received packet is ok
BIT_RST equ 4 ; reset bit
BIT_RE equ 3 ; receiver enabled
BIT_TE equ 2 ; transmitter enabled
BUFE equ 1 ; rx buffer is empty, no packet stored
BIT_RST = 4 ; reset bit
BIT_RE = 3 ; receiver enabled
BIT_TE = 2 ; transmitter enabled
BUFE = 1 ; rx buffer is empty, no packet stored
BIT_ISR_TOK equ 2 ; transmit ok
BIT_ISR_RER equ 1 ; receive error interrupt
BIT_ISR_ROK equ 0 ; receive ok
BIT_ISR_TOK = 2 ; transmit ok
BIT_ISR_RER = 1 ; receive error interrupt
BIT_ISR_ROK = 0 ; receive ok
BIT_TX_MXDMA equ 8 ; Max DMA burst size per Tx DMA burst
BIT_TXRR equ 4 ; Tx Retry count 16+(TXRR*16)
BIT_TX_MXDMA = 8 ; Max DMA burst size per Tx DMA burst
BIT_TXRR = 4 ; Tx Retry count 16+(TXRR*16)
BIT_RXFTH equ 13 ; Rx fifo threshold
BIT_RBLEN equ 11 ; Ring buffer length indicator
BIT_RX_MXDMA equ 8 ; Max DMA burst size per Rx DMA burst
BIT_NOWRAP equ 7 ; transfered data wrapping
BIT_9356SEL equ 6 ; eeprom selector 9346/9356
BIT_AER equ 5 ; accept error packets
BIT_AR equ 4 ; accept runt packets
BIT_AB equ 3 ; accept broadcast packets
BIT_AM equ 2 ; accept multicast packets
BIT_APM equ 1 ; accept physical match packets
BIT_AAP equ 0 ; accept all packets
BIT_RXFTH = 13 ; Rx fifo threshold
BIT_RBLEN = 11 ; Ring buffer length indicator
BIT_RX_MXDMA = 8 ; Max DMA burst size per Rx DMA burst
BIT_NOWRAP = 7 ; transfered data wrapping
BIT_9356SEL = 6 ; eeprom selector 9346/9356
BIT_AER = 5 ; accept error packets
BIT_AR = 4 ; accept runt packets
BIT_AB = 3 ; accept broadcast packets
BIT_AM = 2 ; accept multicast packets
BIT_APM = 1 ; accept physical match packets
BIT_AAP = 0 ; accept all packets
BIT_93C46_EEM1 equ 7 ; RTL8139 eeprom operating mode1
BIT_93C46_EEM0 equ 6 ; RTL8139 eeprom operating mode0
BIT_93C46_EECS equ 3 ; chip select
BIT_93C46_EESK equ 2 ; serial data clock
BIT_93C46_EEDI equ 1 ; serial data input
BIT_93C46_EEDO equ 0 ; serial data output
BIT_93C46_EEM1 = 7 ; RTL8139 eeprom operating mode1
BIT_93C46_EEM0 = 6 ; RTL8139 eeprom operating mode0
BIT_93C46_EECS = 3 ; chip select
BIT_93C46_EESK = 2 ; serial data clock
BIT_93C46_EEDI = 1 ; serial data input
BIT_93C46_EEDO = 0 ; serial data output
BIT_LWACT equ 4 ; see REG_CONFIG1
BIT_SLEEP equ 1 ; sleep bit at older chips
BIT_PWRDWN equ 0 ; power down bit at older chips
BIT_PMEn equ 0 ; power management enabled
BIT_LWACT = 4 ; see REG_CONFIG1
BIT_SLEEP = 1 ; sleep bit at older chips
BIT_PWRDWN = 0 ; power down bit at older chips
BIT_PMEn = 0 ; power management enabled
BIT_LWPTN equ 2 ; see REG_CONFIG4
BIT_LWPTN = 2 ; see REG_CONFIG4
BIT_ERTXTH equ 16 ; early TX threshold
BIT_TOK equ 15 ; transmit ok
BIT_OWN equ 13 ; tx DMA operation is completed
BIT_ERTXTH = 16 ; early TX threshold
BIT_TOK = 15 ; transmit ok
BIT_OWN = 13 ; tx DMA operation is completed
BIT_ANE equ 12 ; auto negotiation enable
BIT_ANE = 12 ; auto negotiation enable
BIT_TXFD equ 8 ; 100base-T full duplex
BIT_TX equ 7 ; 100base-T
BIT_10FD equ 6 ; 10base-T full duplex
BIT_10 equ 5 ; 10base-T
BIT_SELECTOR equ 0 ; binary encoded selector CSMA/CD=00001
BIT_TXFD = 8 ; 100base-T full duplex
BIT_TX = 7 ; 100base-T
BIT_10FD = 6 ; 10base-T full duplex
BIT_10 = 5 ; 10base-T
BIT_SELECTOR = 0 ; binary encoded selector CSMA/CD=00001
BIT_IFG1 equ 25
BIT_IFG0 equ 24
BIT_IFG1 = 25
BIT_IFG0 = 24
TXRR equ 8 ; total retries = 16+(TXRR*16)
TX_MXDMA equ 6 ; 0=16 1=32 2=64 3=128 4=256 5=512 6=1024 7=2048
ERTXTH equ 8 ; in unit of 32 bytes e.g:(8*32)=256
RX_MXDMA equ 7 ; 0=16 1=32 2=64 3=128 4=256 5=512 6=1024 7=unlimited
RXFTH equ 7 ; 0=16 1=32 2=64 3=128 4=256 5=512 6=1024 7=no threshold
TXRR = 8 ; total retries = 16+(TXRR*16)
TX_MXDMA = 6 ; 0=16 1=32 2=64 3=128 4=256 5=512 6=1024 7=2048
ERTXTH = 8 ; in unit of 32 bytes e.g:(8*32)=256
RX_MXDMA = 7 ; 0=16 1=32 2=64 3=128 4=256 5=512 6=1024 7=unlimited
RXFTH = 7 ; 0=16 1=32 2=64 3=128 4=256 5=512 6=1024 7=no threshold
RX_CONFIG equ (RBLEN shl BIT_RBLEN) or \
RX_CONFIG = (RBLEN shl BIT_RBLEN) or \
(RX_MXDMA shl BIT_RX_MXDMA) or \
(1 shl BIT_NOWRAP) or \
(RXFTH shl BIT_RXFTH) or\
@ -134,49 +134,49 @@ public version
(1 shl BIT_AR) or \ ; Accept Runt packets (smaller then 64 bytes)
(1 shl BIT_AM) ; Accept multicast packets
RX_BUFFER_SIZE equ (8192 shl RBLEN);+16
MAX_ETH_FRAME_SIZE equ 1516 ; exactly 1514 wthout CRC
NUM_TX_DESC equ 4
RX_BUFFER_SIZE = (8192 shl RBLEN);+16
MAX_ETH_FRAME_SIZE = 1516 ; exactly 1514 wthout CRC
NUM_TX_DESC = 4
EE_93C46_REG_ETH_ID equ 7 ; MAC offset
EE_93C46_READ_CMD equ (6 shl 6) ; 110b + 6bit address
EE_93C56_READ_CMD equ (6 shl 8) ; 110b + 8bit address
EE_93C46_CMD_LENGTH equ 9 ; start bit + cmd + 6bit address
EE_93C56_CMD_LENGTH equ 11 ; start bit + cmd + 8bit ddress
EE_93C46_REG_ETH_ID = 7 ; MAC offset
EE_93C46_READ_CMD = (6 shl 6) ; 110b + 6bit address
EE_93C56_READ_CMD = (6 shl 8) ; 110b + 8bit address
EE_93C46_CMD_LENGTH = 9 ; start bit + cmd + 6bit address
EE_93C56_CMD_LENGTH = 11 ; start bit + cmd + 8bit ddress
VER_RTL8139 equ 1100000b
VER_RTL8139A equ 1110000b
VER_RTL8139AG equ 1110100b
VER_RTL8139B equ 1111000b
VER_RTL8130 equ VER_RTL8139B
VER_RTL8139C equ 1110100b
VER_RTL8100 equ 1111010b
VER_RTL8100B equ 1110101b
VER_RTL8139D equ VER_RTL8100B
VER_RTL8139CP equ 1110110b
VER_RTL8101 equ 1110111b
VER_RTL8139 = 1100000b
VER_RTL8139A = 1110000b
VER_RTL8139AG = 1110100b
VER_RTL8139B = 1111000b
VER_RTL8130 = VER_RTL8139B
VER_RTL8139C = 1110100b
VER_RTL8100 = 1111010b
VER_RTL8100B = 1110101b
VER_RTL8139D = VER_RTL8100B
VER_RTL8139CP = 1110110b
VER_RTL8101 = 1110111b
IDX_RTL8139 equ 0
IDX_RTL8139A equ 1
IDX_RTL8139B equ 2
IDX_RTL8139C equ 3
IDX_RTL8100 equ 4
IDX_RTL8139D equ 5
IDX_RTL8139D equ 6
IDX_RTL8101 equ 7
IDX_RTL8139 = 0
IDX_RTL8139A = 1
IDX_RTL8139B = 2
IDX_RTL8139C = 3
IDX_RTL8100 = 4
IDX_RTL8139D = 5
IDX_RTL8139D = 6
IDX_RTL8101 = 7
ISR_SERR equ 1 SHL 15
ISR_TIMEOUT equ 1 SHL 14
ISR_LENCHG equ 1 SHL 13
ISR_FIFOOVW equ 1 SHL 6
ISR_PUN equ 1 SHL 5
ISR_RXOVW equ 1 SHL 4
ISR_TER equ 1 SHL 3
ISR_TOK equ 1 SHL 2
ISR_RER equ 1 SHL 1
ISR_ROK equ 1 SHL 0
ISR_SERR = 1 SHL 15
ISR_TIMEOUT = 1 SHL 14
ISR_LENCHG = 1 SHL 13
ISR_FIFOOVW = 1 SHL 6
ISR_PUN = 1 SHL 5
ISR_RXOVW = 1 SHL 4
ISR_TER = 1 SHL 3
ISR_TOK = 1 SHL 2
ISR_RER = 1 SHL 1
ISR_ROK = 1 SHL 0
INTERRUPT_MASK equ ISR_ROK or \
INTERRUPT_MASK = ISR_ROK or \
ISR_RXOVW or \
ISR_PUN or \
ISR_FIFOOVW or \
@ -184,14 +184,14 @@ public version
ISR_TOK or \
ISR_TER
TSR_OWN equ 1 SHL 13
TSR_TUN equ 1 SHL 14
TSR_TOK equ 1 SHL 15
TSR_OWN = 1 SHL 13
TSR_TUN = 1 SHL 14
TSR_TOK = 1 SHL 15
TSR_CDH equ 1 SHL 28
TSR_OWC equ 1 SHL 29
TSR_TABT equ 1 SHL 30
TSR_CRS equ 1 SHL 31
TSR_CDH = 1 SHL 28
TSR_OWC = 1 SHL 29
TSR_TABT = 1 SHL 30
TSR_CRS = 1 SHL 31
virtual at ebx

284
kernel/branches/net/drivers/RTL8169.asm
View File

@ -22,17 +22,17 @@
format MS COFF
API_VERSION equ 0x01000100
DRIVER_VERSION equ 5
API_VERSION = 0x01000100
DRIVER_VERSION = 5
MAX_DEVICES equ 16
MAX_DEVICES = 16
DEBUG equ 1
__DEBUG__ equ 1
__DEBUG_LEVEL__ equ 1
DEBUG = 1
__DEBUG__ = 1
__DEBUG_LEVEL__ = 1
NUM_TX_DESC equ 4
NUM_RX_DESC equ 4
NUM_TX_DESC = 4
NUM_RX_DESC = 4
include 'proc32.inc'
include 'imports.inc'
@ -44,198 +44,198 @@ public service_proc
public version
REG_MAC0 equ 0x0 ; Ethernet hardware address
REG_MAR0 equ 0x8 ; Multicast filter
REG_TxDescStartAddr equ 0x20
REG_TxHDescStartAddr equ 0x28
REG_FLASH equ 0x30
REG_ERSR equ 0x36
REG_ChipCmd equ 0x37
REG_TxPoll equ 0x38
REG_IntrMask equ 0x3C
REG_IntrStatus equ 0x3E
REG_TxConfig equ 0x40
REG_RxConfig equ 0x44
REG_RxMissed equ 0x4C
REG_Cfg9346 equ 0x50
REG_Config0 equ 0x51
REG_Config1 equ 0x52
REG_Config2 equ 0x53
REG_Config3 equ 0x54
REG_Config4 equ 0x55
REG_Config5 equ 0x56
REG_MultiIntr equ 0x5C
REG_PHYAR equ 0x60
REG_TBICSR equ 0x64
REG_TBI_ANAR equ 0x68
REG_TBI_LPAR equ 0x6A
REG_PHYstatus equ 0x6C
REG_RxMaxSize equ 0xDA
REG_CPlusCmd equ 0xE0
REG_RxDescStartAddr equ 0xE4
REG_ETThReg equ 0xEC
REG_FuncEvent equ 0xF0
REG_FuncEventMask equ 0xF4
REG_FuncPresetState equ 0xF8
REG_FuncForceEvent equ 0xFC
REG_MAC0 = 0x0 ; Ethernet hardware address
REG_MAR0 = 0x8 ; Multicast filter
REG_TxDescStartAddr = 0x20
REG_TxHDescStartAddr = 0x28
REG_FLASH = 0x30
REG_ERSR = 0x36
REG_ChipCmd = 0x37
REG_TxPoll = 0x38
REG_IntrMask = 0x3C
REG_IntrStatus = 0x3E
REG_TxConfig = 0x40
REG_RxConfig = 0x44
REG_RxMissed = 0x4C
REG_Cfg9346 = 0x50
REG_Config0 = 0x51
REG_Config1 = 0x52
REG_Config2 = 0x53
REG_Config3 = 0x54
REG_Config4 = 0x55
REG_Config5 = 0x56
REG_MultiIntr = 0x5C
REG_PHYAR = 0x60
REG_TBICSR = 0x64
REG_TBI_ANAR = 0x68
REG_TBI_LPAR = 0x6A
REG_PHYstatus = 0x6C
REG_RxMaxSize = 0xDA
REG_CPlusCmd = 0xE0
REG_RxDescStartAddr = 0xE4
REG_ETThReg = 0xEC
REG_FuncEvent = 0xF0
REG_FuncEventMask = 0xF4
REG_FuncPresetState = 0xF8
REG_FuncForceEvent = 0xFC
; InterruptStatusBits
ISB_SYSErr equ 0x8000
ISB_PCSTimeout equ 0x4000
ISB_SWInt equ 0x0100
ISB_TxDescUnavail equ 0x80
ISB_RxFIFOOver equ 0x40
ISB_LinkChg equ 0x20
ISB_RxOverflow equ 0x10
ISB_TxErr equ 0x08
ISB_TxOK equ 0x04
ISB_RxErr equ 0x02
ISB_RxOK equ 0x01
ISB_SYSErr = 0x8000
ISB_PCSTimeout = 0x4000
ISB_SWInt = 0x0100
ISB_TxDescUnavail = 0x80
ISB_RxFIFOOver = 0x40
ISB_LinkChg = 0x20
ISB_RxOverflow = 0x10
ISB_TxErr = 0x08
ISB_TxOK = 0x04
ISB_RxErr = 0x02
ISB_RxOK = 0x01
; RxStatusDesc
SD_RxRES equ 0x00200000
SD_RxCRC equ 0x00080000
SD_RxRUNT equ 0x00100000
SD_RxRWT equ 0x00400000
SD_RxRES = 0x00200000
SD_RxCRC = 0x00080000
SD_RxRUNT = 0x00100000
SD_RxRWT = 0x00400000
; ChipCmdBits
CMD_Reset equ 0x10
CMD_RxEnb equ 0x08
CMD_TxEnb equ 0x04
CMD_RxBufEmpty equ 0x01
CMD_Reset = 0x10
CMD_RxEnb = 0x08
CMD_TxEnb = 0x04
CMD_RxBufEmpty = 0x01
; Cfg9346Bits
CFG_9346_Lock equ 0x00
CFG_9346_Unlock equ 0xC0
CFG_9346_Lock = 0x00
CFG_9346_Unlock = 0xC0
; rx_mode_bits
RXM_AcceptErr equ 0x20
RXM_AcceptRunt equ 0x10
RXM_AcceptBroadcast equ 0x08
RXM_AcceptMulticast equ 0x04
RXM_AcceptMyPhys equ 0x02
RXM_AcceptAllPhys equ 0x01
RXM_AcceptErr = 0x20
RXM_AcceptRunt = 0x10
RXM_AcceptBroadcast = 0x08
RXM_AcceptMulticast = 0x04
RXM_AcceptMyPhys = 0x02
RXM_AcceptAllPhys = 0x01
; RxConfigBits
RXC_FIFOShift equ 13
RXC_DMAShift equ 8
RXC_FIFOShift = 13
RXC_DMAShift = 8
; TxConfigBits
TXC_InterFrameGapShift equ 24
TXC_DMAShift equ 8 ; DMA burst value (0-7) is shift this many bits
TXC_InterFrameGapShift = 24
TXC_DMAShift = 8 ; DMA burst value (0-7) is shift this many bits
; PHYstatus
PHYS_TBI_Enable equ 0x80
PHYS_TxFlowCtrl equ 0x40
PHYS_RxFlowCtrl equ 0x20
PHYS_1000bpsF equ 0x10
PHYS_100bps equ 0x08
PHYS_10bps equ 0x04
PHYS_LinkStatus equ 0x02
PHYS_FullDup equ 0x01
PHYS_TBI_Enable = 0x80
PHYS_TxFlowCtrl = 0x40
PHYS_RxFlowCtrl = 0x20
PHYS_1000bpsF = 0x10
PHYS_100bps = 0x08
PHYS_10bps = 0x04
PHYS_LinkStatus = 0x02
PHYS_FullDup = 0x01
; GIGABIT_PHY_registers
PHY_CTRL_REG equ 0
PHY_STAT_REG equ 1
PHY_AUTO_NEGO_REG equ 4
PHY_1000_CTRL_REG equ 9
PHY_CTRL_REG = 0
PHY_STAT_REG = 1
PHY_AUTO_NEGO_REG = 4
PHY_1000_CTRL_REG = 9
; GIGABIT_PHY_REG_BIT
PHY_Restart_Auto_Nego equ 0x0200
PHY_Enable_Auto_Nego equ 0x1000
PHY_Restart_Auto_Nego = 0x0200
PHY_Enable_Auto_Nego = 0x1000
; PHY_STAT_REG = 1;
PHY_Auto_Neco_Comp equ 0x0020
PHY_Auto_Neco_Comp = 0x0020
; PHY_AUTO_NEGO_REG = 4;
PHY_Cap_10_Half equ 0x0020
PHY_Cap_10_Full equ 0x0040
PHY_Cap_100_Half equ 0x0080
PHY_Cap_100_Full equ 0x0100
PHY_Cap_10_Half = 0x0020
PHY_Cap_10_Full = 0x0040
PHY_Cap_100_Half = 0x0080
PHY_Cap_100_Full = 0x0100
; PHY_1000_CTRL_REG = 9;
PHY_Cap_1000_Full equ 0x0200
PHY_Cap_1000_Half equ 0x0100
PHY_Cap_1000_Full = 0x0200
PHY_Cap_1000_Half = 0x0100
PHY_Cap_PAUSE equ 0x0400
PHY_Cap_ASYM_PAUSE equ 0x0800
PHY_Cap_PAUSE = 0x0400
PHY_Cap_ASYM_PAUSE = 0x0800
PHY_Cap_Null equ 0x0
PHY_Cap_Null = 0x0
; _MediaType
MT_10_Half equ 0x01
MT_10_Full equ 0x02
MT_100_Half equ 0x04
MT_100_Full equ 0x08
MT_1000_Full equ 0x10
MT_10_Half = 0x01
MT_10_Full = 0x02
MT_100_Half = 0x04
MT_100_Full = 0x08
MT_1000_Full = 0x10
; _TBICSRBit
TBI_LinkOK equ 0x02000000
TBI_LinkOK = 0x02000000
; _DescStatusBit
DSB_OWNbit equ 0x80000000
DSB_EORbit equ 0x40000000
DSB_FSbit equ 0x20000000
DSB_LSbit equ 0x10000000
DSB_OWNbit = 0x80000000
DSB_EORbit = 0x40000000
DSB_FSbit = 0x20000000
DSB_LSbit = 0x10000000
RX_BUF_SIZE equ 1536 ; Rx Buffer size
RX_BUF_SIZE = 1536 ; Rx Buffer size
ETH_ALEN equ 6
ETH_HLEN equ (2 * ETH_ALEN + 2)
ETH_ZLEN equ 60 ; 60 + 4bytes auto payload for
ETH_ALEN = 6
ETH_HLEN = (2 * ETH_ALEN + 2)
ETH_ZLEN = 60 ; 60 + 4bytes auto payload for
; mininmum 64bytes frame length
; MAC address length
MAC_ADDR_LEN equ 6
MAC_ADDR_LEN = 6
; max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4)
MAX_ETH_FRAME_SIZE equ 1536
MAX_ETH_FRAME_SIZE = 1536
TX_FIFO_THRESH equ 256 ; In bytes
TX_FIFO_THRESH = 256 ; In bytes
RX_FIFO_THRESH equ 7 ; 7 means NO threshold, Rx buffer level before first PCI xfer
RX_DMA_BURST equ 7 ; Maximum PCI burst, '6' is 1024
TX_DMA_BURST equ 7 ; Maximum PCI burst, '6' is 1024
ETTh equ 0x3F ; 0x3F means NO threshold
RX_FIFO_THRESH = 7 ; 7 means NO threshold, Rx buffer level before first PCI xfer
RX_DMA_BURST = 7 ; Maximum PCI burst, '6' is 1024
TX_DMA_BURST = 7 ; Maximum PCI burst, '6' is 1024
ETTh = 0x3F ; 0x3F means NO threshold
EarlyTxThld equ 0x3F ; 0x3F means NO early transmit
RxPacketMaxSize equ 0x0800 ; Maximum size supported is 16K-1
InterFrameGap equ 0x03 ; 3 means InterFrameGap = the shortest one
EarlyTxThld = 0x3F ; 0x3F means NO early transmit
RxPacketMaxSize = 0x0800 ; Maximum size supported is 16K-1
InterFrameGap = 0x03 ; 3 means InterFrameGap = the shortest one
HZ equ 1000
HZ = 1000
RTL_MIN_IO_SIZE equ 0x80
TX_TIMEOUT equ (6*HZ)
RTL_MIN_IO_SIZE = 0x80
TX_TIMEOUT = (6*HZ)
TIMER_EXPIRE_TIME equ 100
TIMER_EXPIRE_TIME = 100
ETH_HDR_LEN equ 14
DEFAULT_MTU equ 1500
DEFAULT_RX_BUF_LEN equ 1536
ETH_HDR_LEN = 14
DEFAULT_MTU = 1500
DEFAULT_RX_BUF_LEN = 1536
;#ifdef JUMBO_FRAME_SUPPORT
;#define MAX_JUMBO_FRAME_MTU ( 10000 )
;#define MAX_RX_SKBDATA_SIZE ( MAX_JUMBO_FRAME_MTU + ETH_HDR_LEN )
;#else
MAX_RX_SKBDATA_SIZE equ 1600
MAX_RX_SKBDATA_SIZE = 1600
;#endif //end #ifdef JUMBO_FRAME_SUPPORT
MCFG_METHOD_01 equ 0x01
MCFG_METHOD_02 equ 0x02
MCFG_METHOD_03 equ 0x03
MCFG_METHOD_04 equ 0x04
MCFG_METHOD_05 equ 0x05
MCFG_METHOD_11 equ 0x0b
MCFG_METHOD_12 equ 0x0c
MCFG_METHOD_13 equ 0x0d
MCFG_METHOD_14 equ 0x0e
MCFG_METHOD_15 equ 0x0f
MCFG_METHOD_01 = 0x01
MCFG_METHOD_02 = 0x02
MCFG_METHOD_03 = 0x03
MCFG_METHOD_04 = 0x04
MCFG_METHOD_05 = 0x05
MCFG_METHOD_11 = 0x0b
MCFG_METHOD_12 = 0x0c
MCFG_METHOD_13 = 0x0d
MCFG_METHOD_14 = 0x0e
MCFG_METHOD_15 = 0x0f
PCFG_METHOD_1 equ 0x01 ; PHY Reg 0x03 bit0-3 == 0x0000
PCFG_METHOD_2 equ 0x02 ; PHY Reg 0x03 bit0-3 == 0x0001
PCFG_METHOD_3 equ 0x03 ; PHY Reg 0x03 bit0-3 == 0x0002
PCFG_METHOD_1 = 0x01 ; PHY Reg 0x03 bit0-3 == 0x0000
PCFG_METHOD_2 = 0x02 ; PHY Reg 0x03 bit0-3 == 0x0001
PCFG_METHOD_3 = 0x03 ; PHY Reg 0x03 bit0-3 == 0x0002
virtual at 0
tx_desc:

342
kernel/branches/net/drivers/dec21x4x.asm
View File

@ -18,14 +18,14 @@
format MS COFF
API_VERSION equ 0x01000100
DRIVER_VERSION equ 5
API_VERSION = 0x01000100
DRIVER_VERSION = 5
MAX_DEVICES equ 16
MAX_DEVICES = 16
DEBUG equ 1
__DEBUG__ equ 1
__DEBUG_LEVEL__ equ 1
DEBUG = 1
__DEBUG__ = 1
__DEBUG_LEVEL__ = 1
include 'proc32.inc'
include 'imports.inc'
@ -61,117 +61,117 @@ end virtual
;-------------------------------------------
; configuration registers
;-------------------------------------------
CFCS equ 4 ; configuration and status register
CFCS = 4 ; configuration and status register
CSR0 equ 0x00 ; Bus mode
CSR1 equ 0x08 ; Transmit Poll Command
CSR2 equ 0x10 ; Receive Poll Command
CSR3 equ 0x18 ; Receive list base address
CSR4 equ 0x20 ; Transmit list base address
CSR5 equ 0x28 ; Status
CSR6 equ 0x30 ; Operation mode
CSR7 equ 0x38 ; Interrupt enable
CSR8 equ 0x40 ; Missed frames and overflow counter
CSR9 equ 0x48 ; Boot ROM, serial ROM, and MII management
CSR10 equ 0x50 ; Boot ROM programming address
CSR11 equ 0x58 ; General-purpose timer
CSR12 equ 0x60 ; General-purpose port
CSR13 equ 0x68
CSR14 equ 0x70
CSR15 equ 0x78 ; Watchdog timer
CSR0 = 0x00 ; Bus mode
CSR1 = 0x08 ; Transmit Poll Command
CSR2 = 0x10 ; Receive Poll Command
CSR3 = 0x18 ; Receive list base address
CSR4 = 0x20 ; Transmit list base address
CSR5 = 0x28 ; Status
CSR6 = 0x30 ; Operation mode
CSR7 = 0x38 ; Interrupt enable
CSR8 = 0x40 ; Missed frames and overflow counter
CSR9 = 0x48 ; Boot ROM, serial ROM, and MII management
CSR10 = 0x50 ; Boot ROM programming address
CSR11 = 0x58 ; General-purpose timer
CSR12 = 0x60 ; General-purpose port
CSR13 = 0x68
CSR14 = 0x70
CSR15 = 0x78 ; Watchdog timer
;--------bits/commands of CSR0-------------------
CSR0_RESET equ 1b
CSR0_RESET = 1b
CSR0_WIE equ 1 SHL 24 ; Write and Invalidate Enable
CSR0_RLE equ 1 SHL 23 ; PCI Read Line Enable
CSR0_RML equ 1 SHL 21 ; PCI Read Multiple
CSR0_WIE = 1 SHL 24 ; Write and Invalidate Enable
CSR0_RLE = 1 SHL 23 ; PCI Read Line Enable
CSR0_RML = 1 SHL 21 ; PCI Read Multiple
CSR0_CACHEALIGN_NONE equ 00b SHL 14
CSR0_CACHEALIGN_32 equ 01b SHL 14
CSR0_CACHEALIGN_64 equ 10b SHL 14
CSR0_CACHEALIGN_128 equ 11b SHL 14
CSR0_CACHEALIGN_NONE = 00b SHL 14
CSR0_CACHEALIGN_32 = 01b SHL 14
CSR0_CACHEALIGN_64 = 10b SHL 14
CSR0_CACHEALIGN_128 = 11b SHL 14
; using values from linux driver.. :P
CSR0_DEFAULT equ CSR0_WIE+CSR0_RLE+CSR0_RML+CSR0_CACHEALIGN_NONE ;32
CSR0_DEFAULT = CSR0_WIE+CSR0_RLE+CSR0_RML+CSR0_CACHEALIGN_NONE ;32
;------- CSR5 -STATUS- bits --------------------------------
CSR5_TI equ 1 SHL 0 ; Transmit interupt - frame transmition completed
CSR5_TPS equ 1 SHL 1 ; Transmit process stopped
CSR5_TU equ 1 SHL 2 ; Transmit Buffer unavailable
CSR5_TJT equ 1 SHL 3 ; Transmit Jabber Timeout (transmitter had been excessively active)
CSR5_UNF equ 1 SHL 5 ; Transmit underflow - FIFO underflow
CSR5_RI equ 1 SHL 6 ; Receive Interrupt
CSR5_RU equ 1 SHL 7 ; Receive Buffer unavailable
CSR5_RPS equ 1 SHL 8 ; Receive Process stopped
CSR5_RWT equ 1 SHL 9 ; Receive Watchdow Timeout
CSR5_ETI equ 1 SHL 10 ; Early transmit Interrupt
CSR5_GTE equ 1 SHL 11 ; General Purpose Timer Expired
CSR5_FBE equ 1 SHL 13 ; Fatal bus error
CSR5_ERI equ 1 SHL 14 ; Early receive Interrupt
CSR5_AIS equ 1 SHL 15 ; Abnormal interrupt summary
CSR5_NIS equ 1 SHL 16 ; normal interrupt summary
CSR5_RS_SH equ 1 SHL 17 ; Receive process state -shift
CSR5_RS_MASK equ 111b ; -mask
CSR5_TS_SH equ 1 SHL 20 ; Transmit process state -shift
CSR5_TS_MASK equ 111b ; -mask
CSR5_EB_SH equ 1 SHL 23 ; Error bits -shift
CSR5_EB_MASK equ 111b ; Error bits -mask
CSR5_TI = 1 SHL 0 ; Transmit interupt - frame transmition completed
CSR5_TPS = 1 SHL 1 ; Transmit process stopped
CSR5_TU = 1 SHL 2 ; Transmit Buffer unavailable
CSR5_TJT = 1 SHL 3 ; Transmit Jabber Timeout (transmitter had been excessively active)
CSR5_UNF = 1 SHL 5 ; Transmit underflow - FIFO underflow
CSR5_RI = 1 SHL 6 ; Receive Interrupt
CSR5_RU = 1 SHL 7 ; Receive Buffer unavailable
CSR5_RPS = 1 SHL 8 ; Receive Process stopped
CSR5_RWT = 1 SHL 9 ; Receive Watchdow Timeout
CSR5_ETI = 1 SHL 10 ; Early transmit Interrupt
CSR5_GTE = 1 SHL 11 ; General Purpose Timer Expired
CSR5_FBE = 1 SHL 13 ; Fatal bus error
CSR5_ERI = 1 SHL 14 ; Early receive Interrupt
CSR5_AIS = 1 SHL 15 ; Abnormal interrupt summary
CSR5_NIS = 1 SHL 16 ; normal interrupt summary
CSR5_RS_SH = 1 SHL 17 ; Receive process state -shift
CSR5_RS_MASK = 111b ; -mask
CSR5_TS_SH = 1 SHL 20 ; Transmit process state -shift
CSR5_TS_MASK = 111b ; -mask
CSR5_EB_SH = 1 SHL 23 ; Error bits -shift
CSR5_EB_MASK = 111b ; Error bits -mask
;CSR5 TS values
CSR5_TS_STOPPED equ 000b
CSR5_TS_RUNNING_FETCHING_DESC equ 001b
CSR5_TS_RUNNING_WAITING_TX equ 010b
CSR5_TS_RUNNING_READING_BUFF equ 011b
CSR5_TS_RUNNING_SETUP_PCKT equ 101b
CSR5_TS_SUSPENDED equ 110b
CSR5_TS_RUNNING_CLOSING_DESC equ 111b
CSR5_TS_STOPPED = 000b
CSR5_TS_RUNNING_FETCHING_DESC = 001b
CSR5_TS_RUNNING_WAITING_TX = 010b
CSR5_TS_RUNNING_READING_BUFF = 011b
CSR5_TS_RUNNING_SETUP_PCKT = 101b
CSR5_TS_SUSPENDED = 110b
CSR5_TS_RUNNING_CLOSING_DESC = 111b
;------- CSR6 -OPERATION MODE- bits --------------------------------
CSR6_HP equ 1 SHL 0 ; Hash/Perfect Receive Filtering mode
CSR6_SR equ 1 SHL 1 ; Start/Stop receive
CSR6_HO equ 1 SHL 2 ; Hash only Filtering mode
CSR6_PB equ 1 SHL 3 ; Pass bad frames
CSR6_IF equ 1 SHL 4 ; Inverse filtering
CSR6_SB equ 1 SHL 5 ; Start/Stop backoff counter
CSR6_PR equ 1 SHL 6 ; Promiscuos mode -default after reset
CSR6_PM equ 1 SHL 7 ; Pass all multicast
CSR6_F equ 1 SHL 9 ; Full Duplex mode
CSR6_OM_SH equ 1 SHL 10 ; Operating Mode -shift
CSR6_OM_MASK equ 11b ; -mask
CSR6_FC equ 1 SHL 12 ; Force Collision Mode
CSR6_ST equ 1 SHL 13 ; Start/Stop Transmission Command
CSR6_TR_SH equ 1 SHL 14 ; Threshold Control -shift
CSR6_TR_MASK equ 11b ; -mask
CSR6_CA equ 1 SHL 17 ; Capture Effect Enable
CSR6_PS equ 1 SHL 18 ; Port select SRL / MII/SYM
CSR6_HBD equ 1 SHL 19 ; Heartbeat Disable
CSR6_SF equ 1 SHL 21 ; Store and Forward -transmit full packet only
CSR6_TTM equ 1 SHL 22 ; Transmit Threshold Mode -
CSR6_PCS equ 1 SHL 23 ; PCS active and MII/SYM port operates in symbol mode
CSR6_SCR equ 1 SHL 24 ; Scrambler Mode
CSR6_MBO equ 1 SHL 25 ; Must Be One
CSR6_RA equ 1 SHL 30 ; Receive All
CSR6_SC equ 1 SHL 31 ; Special Capture Effect Enable
CSR6_HP = 1 SHL 0 ; Hash/Perfect Receive Filtering mode
CSR6_SR = 1 SHL 1 ; Start/Stop receive
CSR6_HO = 1 SHL 2 ; Hash only Filtering mode
CSR6_PB = 1 SHL 3 ; Pass bad frames
CSR6_IF = 1 SHL 4 ; Inverse filtering
CSR6_SB = 1 SHL 5 ; Start/Stop backoff counter
CSR6_PR = 1 SHL 6 ; Promiscuos mode -default after reset
CSR6_PM = 1 SHL 7 ; Pass all multicast
CSR6_F = 1 SHL 9 ; Full Duplex mode
CSR6_OM_SH = 1 SHL 10 ; Operating Mode -shift
CSR6_OM_MASK = 11b ; -mask
CSR6_FC = 1 SHL 12 ; Force Collision Mode
CSR6_ST = 1 SHL 13 ; Start/Stop Transmission Command
CSR6_TR_SH = 1 SHL 14 ; Threshold Control -shift
CSR6_TR_MASK = 11b ; -mask
CSR6_CA = 1 SHL 17 ; Capture Effect Enable
CSR6_PS = 1 SHL 18 ; Port select SRL / MII/SYM
CSR6_HBD = 1 SHL 19 ; Heartbeat Disable
CSR6_SF = 1 SHL 21 ; Store and Forward -transmit full packet only
CSR6_TTM = 1 SHL 22 ; Transmit Threshold Mode -
CSR6_PCS = 1 SHL 23 ; PCS active and MII/SYM port operates in symbol mode
CSR6_SCR = 1 SHL 24 ; Scrambler Mode
CSR6_MBO = 1 SHL 25 ; Must Be One
CSR6_RA = 1 SHL 30 ; Receive All
CSR6_SC = 1 SHL 31 ; Special Capture Effect Enable
;------- CSR7 -INTERRUPT ENABLE- bits --------------------------------
CSR7_TI equ 1 SHL 0 ; transmit Interrupt Enable (set with CSR7<16> & CSR5<0> )
CSR7_TS equ 1 SHL 1 ; transmit Stopped Enable (set with CSR7<15> & CSR5<1> )
CSR7_TU equ 1 SHL 2 ; transmit buffer underrun Enable (set with CSR7<16> & CSR5<2> )
CSR7_TJ equ 1 SHL 3 ; transmit jabber timeout enable (set with CSR7<15> & CSR5<3> )
CSR7_UN equ 1 SHL 5 ; underflow Interrupt enable (set with CSR7<15> & CSR5<5> )
CSR7_RI equ 1 SHL 6 ; receive Interrupt enable (set with CSR7<16> & CSR5<5> )
CSR7_RU equ 1 SHL 7 ; receive buffer unavailable enable (set with CSR7<15> & CSR5<7> )
CSR7_RS equ 1 SHL 8 ; Receive stopped enable (set with CSR7<15> & CSR5<8> )
CSR7_RW equ 1 SHL 9 ; receive watchdog timeout enable (set with CSR7<15> & CSR5<9> )
CSR7_ETE equ 1 SHL 10 ; Early transmit Interrupt enable (set with CSR7<15> & CSR5<10> )
CSR7_GPT equ 1 SHL 11 ; general purpose timer enable (set with CSR7<15> & CSR5<11> )
CSR7_FBE equ 1 SHL 13 ; Fatal bus error enable (set with CSR7<15> & CSR5<13> )
CSR7_ERE equ 1 SHL 14 ; Early receive enable (set with CSR7<16> & CSR5<14> )
CSR7_AI equ 1 SHL 15 ; Abnormal Interrupt Summary Enable (enables CSR5<0,3,7,8,9,10,13>)
CSR7_NI equ 1 SHL 16 ; Normal Interrup Enable (enables CSR5<0,2,6,11,14>)
CSR7_DEFAULT equ CSR7_TI+CSR7_TS+CSR7_RI+CSR7_RS+CSR7_TU+CSR7_TJ+CSR7_UN+\
CSR7_TI = 1 SHL 0 ; transmit Interrupt Enable (set with CSR7<16> & CSR5<0> )
CSR7_TS = 1 SHL 1 ; transmit Stopped Enable (set with CSR7<15> & CSR5<1> )
CSR7_TU = 1 SHL 2 ; transmit buffer underrun Enable (set with CSR7<16> & CSR5<2> )
CSR7_TJ = 1 SHL 3 ; transmit jabber timeout enable (set with CSR7<15> & CSR5<3> )
CSR7_UN = 1 SHL 5 ; underflow Interrupt enable (set with CSR7<15> & CSR5<5> )
CSR7_RI = 1 SHL 6 ; receive Interrupt enable (set with CSR7<16> & CSR5<5> )
CSR7_RU = 1 SHL 7 ; receive buffer unavailable enable (set with CSR7<15> & CSR5<7> )
CSR7_RS = 1 SHL 8 ; Receive stopped enable (set with CSR7<15> & CSR5<8> )
CSR7_RW = 1 SHL 9 ; receive watchdog timeout enable (set with CSR7<15> & CSR5<9> )
CSR7_ETE = 1 SHL 10 ; Early transmit Interrupt enable (set with CSR7<15> & CSR5<10> )
CSR7_GPT = 1 SHL 11 ; general purpose timer enable (set with CSR7<15> & CSR5<11> )
CSR7_FBE = 1 SHL 13 ; Fatal bus error enable (set with CSR7<15> & CSR5<13> )
CSR7_ERE = 1 SHL 14 ; Early receive enable (set with CSR7<16> & CSR5<14> )
CSR7_AI = 1 SHL 15 ; Abnormal Interrupt Summary Enable (enables CSR5<0,3,7,8,9,10,13>)
CSR7_NI = 1 SHL 16 ; Normal Interrup Enable (enables CSR5<0,2,6,11,14>)
CSR7_DEFAULT = CSR7_TI+CSR7_TS+CSR7_RI+CSR7_RS+CSR7_TU+CSR7_TJ+CSR7_UN+\
CSR7_RU+CSR7_RW+CSR7_FBE+CSR7_AI+CSR7_NI
;----------- descriptor structure ---------------------
@ -189,83 +189,83 @@ virtual at 0
end virtual
;common to Rx and Tx
DES0_OWN equ 1 SHL 31 ; if set, the NIC controls the descriptor, otherwise driver 'owns' the descriptors
DES0_OWN = 1 SHL 31 ; if set, the NIC controls the descriptor, otherwise driver 'owns' the descriptors
;receive
RDES0_ZER equ 1 SHL 0 ; must be 0 if legal length :D
RDES0_CE equ 1 SHL 1 ; CRC error, valid only on last desc (RDES0<8>=1)
RDES0_DB equ 1 SHL 2 ; dribbling bit - not multiple of 8 bits, valid only on last desc (RDES0<8>=1)
RDES0_RE equ 1 SHL 3 ; Report on MII error.. i dont realy know what this means :P
RDES0_RW equ 1 SHL 4 ; received watchdog timer expiration - must set CSR5<9>, valid only on last desc (RDES0<8>=1)
RDES0_FT equ 1 SHL 5 ; frame type: 0->IEEE802.0 (len<1500) 1-> ETHERNET frame (len>1500), valid only on last desc (RDES0<8>=1)
RDES0_CS equ 1 SHL 6 ; Collision seen, valid only on last desc (RDES0<8>=1)
RDES0_TL equ 1 SHL 7 ; Too long(>1518)-NOT AN ERROR, valid only on last desc (RDES0<8>=1)
RDES0_LS equ 1 SHL 8 ; Last descriptor of current frame
RDES0_FS equ 1 SHL 9 ; First descriptor of current frame
RDES0_MF equ 1 SHL 10 ; Multicast frame, valid only on last desc (RDES0<8>=1)
RDES0_RF equ 1 SHL 11 ; Runt frame, valid only on last desc (RDES0<8>=1) and id overflow
RDES0_DT_SERIAL equ 00b SHL 12 ; Data type-Serial recv frame, valid only on last desc (RDES0<8>=1)
RDES0_DT_INTERNAL equ 01b SHL 12 ; Data type-Internal loopback recv frame, valid only on last desc (RDES0<8>=1)
RDES0_DT_EXTERNAL equ 11b SHL 12 ; Data type-External loopback recv frame, valid only on last desc (RDES0<8>=1)
RDES0_DE equ 1 SHL 14 ; Descriptor error - cant own a new desc and frame doesnt fit, valid only on last desc (RDES0<8>=1)
RDES0_ES equ 1 SHL 15 ; Error Summmary - bits 1+6+11+14, valid only on last desc (RDES0<8>=1)
RDES0_FL_SH equ 16 ; Field length shift, valid only on last desc (RDES0<8>=1)
RDES0_FL_MASK equ 11111111111111b ; Field length mask (+CRC), valid only on last desc (RDES0<8>=1)
RDES0_FF equ 1 SHL 30 ; Filtering fail-frame failed address recognition test(must CSR6<30>=1), valid only on last desc (RDES0<8>=1)
RDES0_ZER = 1 SHL 0 ; must be 0 if legal length :D
RDES0_CE = 1 SHL 1 ; CRC error, valid only on last desc (RDES0<8>=1)
RDES0_DB = 1 SHL 2 ; dribbling bit - not multiple of 8 bits, valid only on last desc (RDES0<8>=1)
RDES0_RE = 1 SHL 3 ; Report on MII error.. i dont realy know what this means :P
RDES0_RW = 1 SHL 4 ; received watchdog timer expiration - must set CSR5<9>, valid only on last desc (RDES0<8>=1)
RDES0_FT = 1 SHL 5 ; frame type: 0->IEEE802.0 (len<1500) 1-> ETHERNET frame (len>1500), valid only on last desc (RDES0<8>=1)
RDES0_CS = 1 SHL 6 ; Collision seen, valid only on last desc (RDES0<8>=1)
RDES0_TL = 1 SHL 7 ; Too long(>1518)-NOT AN ERROR, valid only on last desc (RDES0<8>=1)
RDES0_LS = 1 SHL 8 ; Last descriptor of current frame
RDES0_FS = 1 SHL 9 ; First descriptor of current frame
RDES0_MF = 1 SHL 10 ; Multicast frame, valid only on last desc (RDES0<8>=1)
RDES0_RF = 1 SHL 11 ; Runt frame, valid only on last desc (RDES0<8>=1) and id overflow
RDES0_DT_SERIAL = 00b SHL 12 ; Data type-Serial recv frame, valid only on last desc (RDES0<8>=1)
RDES0_DT_INTERNAL = 01b SHL 12 ; Data type-Internal loopback recv frame, valid only on last desc (RDES0<8>=1)
RDES0_DT_EXTERNAL = 11b SHL 12 ; Data type-External loopback recv frame, valid only on last desc (RDES0<8>=1)
RDES0_DE = 1 SHL 14 ; Descriptor error - cant own a new desc and frame doesnt fit, valid only on last desc (RDES0<8>=1)
RDES0_ES = 1 SHL 15 ; Error Summmary - bits 1+6+11+14, valid only on last desc (RDES0<8>=1)
RDES0_FL_SH = 16 ; Field length shift, valid only on last desc (RDES0<8>=1)
RDES0_FL_MASK = 11111111111111b ; Field length mask (+CRC), valid only on last desc (RDES0<8>=1)
RDES0_FF = 1 SHL 30 ; Filtering fail-frame failed address recognition test(must CSR6<30>=1), valid only on last desc (RDES0<8>=1)
RDES1_RBS1_MASK equ 11111111111b ; firsd buffer size MASK
RDES1_RBS2_SH equ 1 SHL 11 ; second buffer size SHIFT
RDES1_RBS2_MASK equ 11111111111b ; second buffer size MASK
RDES1_RCH equ 1 SHL 24 ; Second address chained - second address (buffer) is next desc address
RDES1_RER equ 1 SHL 25 ; Receive End of Ring - final descriptor, NIC must return to first desc
RDES1_RBS1_MASK = 11111111111b ; firsd buffer size MASK
RDES1_RBS2_SH = 1 SHL 11 ; second buffer size SHIFT
RDES1_RBS2_MASK = 11111111111b ; second buffer size MASK
RDES1_RCH = 1 SHL 24 ; Second address chained - second address (buffer) is next desc address
RDES1_RER = 1 SHL 25 ; Receive End of Ring - final descriptor, NIC must return to first desc
;transmition
TDES0_DE equ 1 SHL 0 ; Deffered
TDES0_UF equ 1 SHL 1 ; Underflow error
TDES0_LF equ 1 SHL 2 ; Link fail report (only if CSR6<23>=1)
TDES0_CC_SH equ 3 ; Collision Count shift - no of collision before transmition
TDES0_CC_MASK equ 1111b ; Collision Count mask
TDES0_HF equ 1 SHL 7 ; Heartbeat fail
TDES0_EC equ 1 SHL 8 ; Excessive Collisions - >16 collisions
TDES0_LC equ 1 SHL 9 ; Late collision
TDES0_NC equ 1 SHL 10 ; No carrier
TDES0_LO equ 1 SHL 11 ; Loss of carrier
TDES0_TO equ 1 SHL 14 ; Transmit Jabber Timeout
TDES0_ES equ 1 SHL 15 ; Error summary TDES0<1+8+9+10+11+14>=1
TDES0_DE = 1 SHL 0 ; Deffered
TDES0_UF = 1 SHL 1 ; Underflow error
TDES0_LF = 1 SHL 2 ; Link fail report (only if CSR6<23>=1)
TDES0_CC_SH = 3 ; Collision Count shift - no of collision before transmition
TDES0_CC_MASK = 1111b ; Collision Count mask
TDES0_HF = 1 SHL 7 ; Heartbeat fail
TDES0_EC = 1 SHL 8 ; Excessive Collisions - >16 collisions
TDES0_LC = 1 SHL 9 ; Late collision
TDES0_NC = 1 SHL 10 ; No carrier
TDES0_LO = 1 SHL 11 ; Loss of carrier
TDES0_TO = 1 SHL 14 ; Transmit Jabber Timeout
TDES0_ES = 1 SHL 15 ; Error summary TDES0<1+8+9+10+11+14>=1
TDES1_TBS1_MASK equ 11111111111b ; Buffer 1 size mask
TDES1_TBS2_SH equ 11 ; Buffer 2 size shift
TDES1_TBS2_MASK equ 11111111111b ; Buffer 2 size mask
TDES1_FT0 equ 1 SHL 22 ; Filtering type 0
TDES1_DPD equ 1 SHL 23 ; Disabled padding for packets <64bytes, no padding
TDES1_TCH equ 1 SHL 24 ; Second address chained - second buffer pointer is to next desc
TDES1_TER equ 1 SHL 25 ; Transmit end of ring - final descriptor
TDES1_AC equ 1 SHL 26 ; Add CRC disable -pretty obvious
TDES1_SET equ 1 SHL 27 ; Setup packet
TDES1_FT1 equ 1 SHL 28 ; Filtering type 1
TDES1_FS equ 1 SHL 29 ; First segment - buffer is first segment of frame
TDES1_LS equ 1 SHL 30 ; Last segment
TDES1_IC equ 1 SHL 31 ; Interupt on completion (CSR5<0>=1) valid when TDES1<30>=1
TDES1_TBS1_MASK = 11111111111b ; Buffer 1 size mask
TDES1_TBS2_SH = 11 ; Buffer 2 size shift
TDES1_TBS2_MASK = 11111111111b ; Buffer 2 size mask
TDES1_FT0 = 1 SHL 22 ; Filtering type 0
TDES1_DPD = 1 SHL 23 ; Disabled padding for packets <64bytes, no padding
TDES1_TCH = 1 SHL 24 ; Second address chained - second buffer pointer is to next desc
TDES1_TER = 1 SHL 25 ; Transmit end of ring - final descriptor
TDES1_AC = 1 SHL 26 ; Add CRC disable -pretty obvious
TDES1_SET = 1 SHL 27 ; Setup packet
TDES1_FT1 = 1 SHL 28 ; Filtering type 1
TDES1_FS = 1 SHL 29 ; First segment - buffer is first segment of frame
TDES1_LS = 1 SHL 30 ; Last segment
TDES1_IC = 1 SHL 31 ; Interupt on completion (CSR5<0>=1) valid when TDES1<30>=1
MAX_ETH_FRAME_SIZE equ 1514
MAX_ETH_FRAME_SIZE = 1514
RX_DES_COUNT equ 4 ; no of RX descriptors, must be power of 2
RX_BUFF_SIZE equ 2048 ; size of buffer for each descriptor, must be multiple of 4 and <= 2048 TDES1_TBS1_MASK
TX_DES_COUNT equ 4 ; no of TX descriptors, must be power of 2
TX_BUFF_SIZE equ 2048 ; size of buffer for each descriptor, used for memory allocation only
RX_DES_COUNT = 4 ; no of RX descriptors, must be power of 2
RX_BUFF_SIZE = 2048 ; size of buffer for each descriptor, must be multiple of 4 and <= 2048 TDES1_TBS1_MASK
TX_DES_COUNT = 4 ; no of TX descriptors, must be power of 2
TX_BUFF_SIZE = 2048 ; size of buffer for each descriptor, used for memory allocation only
RX_MEM_TOTAL_SIZE equ RX_DES_COUNT*(DES.size+RX_BUFF_SIZE)
TX_MEM_TOTAL_SIZE equ TX_DES_COUNT*(DES.size+TX_BUFF_SIZE)
RX_MEM_TOTAL_SIZE = RX_DES_COUNT*(DES.size+RX_BUFF_SIZE)
TX_MEM_TOTAL_SIZE = TX_DES_COUNT*(DES.size+TX_BUFF_SIZE)
;=============================================================================
; serial ROM operations
;=============================================================================
CSR9_SR equ 1 SHL 11 ; SROM Select
CSR9_RD equ 1 SHL 14 ; ROM Read Operation
CSR9_SROM_DO equ 1 SHL 3 ; Data Out for SROM
CSR9_SROM_DI equ 1 SHL 2 ; Data In to SROM
CSR9_SROM_CK equ 1 SHL 1 ; clock for SROM
CSR9_SROM_CS equ 1 SHL 0 ; chip select.. always needed
CSR9_SR = 1 SHL 11 ; SROM Select
CSR9_RD = 1 SHL 14 ; ROM Read Operation
CSR9_SROM_DO = 1 SHL 3 ; Data Out for SROM
CSR9_SROM_DI = 1 SHL 2 ; Data In to SROM
CSR9_SROM_CK = 1 SHL 1 ; clock for SROM
CSR9_SROM_CS = 1 SHL 0 ; chip select.. always needed
; assume dx is CSR9
macro SROM_Delay {
@ -1487,12 +1487,12 @@ SROM_Read_Word:
; MDIO protocol. It is just different enough from the EEPROM protocol
; to not share code. The maxium data clock rate is 2.5 Mhz.
MDIO_SHIFT_CLK equ 0x10000
MDIO_DATA_WRITE0 equ 0x00000
MDIO_DATA_WRITE1 equ 0x20000
MDIO_ENB equ 0x00000 ; Ignore the 0x02000 databook setting.
MDIO_ENB_IN equ 0x40000
MDIO_DATA_READ equ 0x80000
MDIO_SHIFT_CLK = 0x10000
MDIO_DATA_WRITE0 = 0x00000
MDIO_DATA_WRITE1 = 0x20000
MDIO_ENB = 0x00000 ; Ignore the 0x02000 databook setting.
MDIO_ENB_IN = 0x40000
MDIO_DATA_READ = 0x80000
; MII transceiver control section.
; Read and write the MII registers using software-generated serial

76
kernel/branches/net/drivers/i8255x.asm
View File

@ -19,14 +19,14 @@
format MS COFF
API_VERSION equ 0x01000100
DRIVER_VERSION equ 5
API_VERSION = 0x01000100
DRIVER_VERSION = 5
MAX_DEVICES equ 16
MAX_DEVICES = 16
DEBUG equ 1
__DEBUG__ equ 1
__DEBUG_LEVEL__ equ 1
DEBUG = 1
__DEBUG__ = 1
__DEBUG_LEVEL__ = 1
include 'proc32.inc'
include 'imports.inc'
@ -109,46 +109,46 @@ end virtual
; Serial EEPROM
EE_SK equ 1 shl 16 ; serial clock
EE_CS equ 1 shl 17 ; chip select
EE_DI equ 1 shl 18 ; data in
EE_DO equ 1 shl 19 ; data out
EE_SK = 1 shl 16 ; serial clock
EE_CS = 1 shl 17 ; chip select
EE_DI = 1 shl 18 ; data in
EE_DO = 1 shl 19 ; data out
EE_READ equ 110b
EE_WRITE equ 101b
EE_ERASE equ 111b
EE_READ = 110b
EE_WRITE = 101b
EE_ERASE = 111b
; The SCB accepts the following controls for the Tx and Rx units:
CU_START equ 0x0010
CU_RESUME equ 0x0020
CU_STATSADDR equ 0x0040
CU_SHOWSTATS equ 0x0050 ; Dump statistics counters.
CU_CMD_BASE equ 0x0060 ; Base address to add to add CU commands.
CU_DUMPSTATS equ 0x0070 ; Dump then reset stats counters.
CU_START = 0x0010
CU_RESUME = 0x0020
CU_STATSADDR = 0x0040
CU_SHOWSTATS = 0x0050 ; Dump statistics counters.
CU_CMD_BASE = 0x0060 ; Base address to add to add CU commands.
CU_DUMPSTATS = 0x0070 ; Dump then reset stats counters.
RX_START equ 0x0001
RX_RESUME equ 0x0002
RX_ABORT equ 0x0004
RX_ADDR_LOAD equ 0x0006
RX_RESUMENR equ 0x0007
INT_MASK equ 0x0100
DRVR_INT equ 0x0200 ; Driver generated interrupt
RX_START = 0x0001
RX_RESUME = 0x0002
RX_ABORT = 0x0004
RX_ADDR_LOAD = 0x0006
RX_RESUMENR = 0x0007
INT_MASK = 0x0100
DRVR_INT = 0x0200 ; Driver generated interrupt
CmdIASetup equ 0x0001
CmdConfigure equ 0x0002
CmdTx equ 0x0004 ;;;;
CmdTxFlex equ 0x0008 ;;;
Cmdsuspend equ 0x4000
CmdIASetup = 0x0001
CmdConfigure = 0x0002
CmdTx = 0x0004 ;;;;
CmdTxFlex = 0x0008 ;;;
Cmdsuspend = 0x4000
reg_scb_status equ 0
reg_scb_cmd equ 2
reg_scb_ptr equ 4
reg_port equ 8
reg_eeprom_ctrl equ 12
reg_eeprom equ 14
reg_mdi_ctrl equ 16
reg_scb_status = 0
reg_scb_cmd = 2
reg_scb_ptr = 4
reg_port = 8
reg_eeprom_ctrl = 12
reg_eeprom = 14
reg_mdi_ctrl = 16
macro delay {

438
kernel/branches/net/drivers/mtd80x.asm
View File

@ -16,17 +16,17 @@
format MS COFF
API_VERSION equ 0x01000100
DRIVER_VERSION equ 5
API_VERSION = 0x01000100
DRIVER_VERSION = 5
MAX_DEVICES equ 16
MAX_DEVICES = 16
DEBUG equ 1
__DEBUG__ equ 1
__DEBUG_LEVEL__ equ 1
DEBUG = 1
__DEBUG__ = 1
__DEBUG_LEVEL__ = 1
NUM_TX_DESC equ 4
NUM_RX_DESC equ 4
NUM_TX_DESC = 4
NUM_RX_DESC = 4
include 'proc32.inc'
include 'imports.inc'
@ -40,210 +40,210 @@ public version
; for different PHY
MysonPHY equ 1
AhdocPHY equ 2
SeeqPHY equ 3
MarvellPHY equ 4
Myson981 equ 5
LevelOnePHY equ 6
OtherPHY equ 10
MysonPHY = 1
AhdocPHY = 2
SeeqPHY = 3
MarvellPHY = 4
Myson981 = 5
LevelOnePHY = 6
OtherPHY = 10
; Offsets to the Command and Status Registers.
PAR0 equ 0x0 ; physical address 0-3
PAR1 equ 0x04 ; physical address 4-5
MAR0 equ 0x08 ; multicast address 0-3
MAR1 equ 0x0C ; multicast address 4-7
FAR0 equ 0x10 ; flow-control address 0-3
FAR1 equ 0x14 ; flow-control address 4-5
TCRRCR equ 0x18 ; receive & transmit configuration
BCR equ 0x1C ; bus command
TXPDR equ 0x20 ; transmit polling demand
RXPDR equ 0x24 ; receive polling demand
RXCWP equ 0x28 ; receive current word pointer
TXLBA equ 0x2C ; transmit list base address
RXLBA equ 0x30 ; receive list base address
ISR equ 0x34 ; interrupt status
IMR equ 0x38 ; interrupt mask
FTH equ 0x3C ; flow control high/low threshold
MANAGEMENT equ 0x40 ; bootrom/eeprom and mii management
TALLY equ 0x44 ; tally counters for crc and mpa
TSR equ 0x48 ; tally counter for transmit status
BMCRSR equ 0x4c ; basic mode control and status
PHYIDENTIFIER equ 0x50 ; phy identifier
ANARANLPAR equ 0x54 ; auto-negotiation advertisement and link partner ability
ANEROCR equ 0x58 ; auto-negotiation expansion and pci conf.
BPREMRPSR equ 0x5c ; bypass & receive error mask and phy status
PAR0 = 0x0 ; physical address 0-3
PAR1 = 0x04 ; physical address 4-5
MAR0 = 0x08 ; multicast address 0-3
MAR1 = 0x0C ; multicast address 4-7
FAR0 = 0x10 ; flow-control address 0-3
FAR1 = 0x14 ; flow-control address 4-5
TCRRCR = 0x18 ; receive & transmit configuration
BCR = 0x1C ; bus command
TXPDR = 0x20 ; transmit polling demand
RXPDR = 0x24 ; receive polling demand
RXCWP = 0x28 ; receive current word pointer
TXLBA = 0x2C ; transmit list base address
RXLBA = 0x30 ; receive list base address
ISR = 0x34 ; interrupt status
IMR = 0x38 ; interrupt mask
FTH = 0x3C ; flow control high/low threshold
MANAGEMENT = 0x40 ; bootrom/eeprom and mii management
TALLY = 0x44 ; tally counters for crc and mpa
TSR = 0x48 ; tally counter for transmit status
BMCRSR = 0x4c ; basic mode control and status
PHYIDENTIFIER = 0x50 ; phy identifier
ANARANLPAR = 0x54 ; auto-negotiation advertisement and link partner ability
ANEROCR = 0x58 ; auto-negotiation expansion and pci conf.
BPREMRPSR = 0x5c ; bypass & receive error mask and phy status
; Bits in the interrupt status/enable registers.
RFCON equ 0x00020000 ; receive flow control xon packet
RFCOFF equ 0x00010000 ; receive flow control xoff packet
LSCStatus equ 0x00008000 ; link status change
ANCStatus equ 0x00004000 ; autonegotiation completed
FBE equ 0x00002000 ; fatal bus error
FBEMask equ 0x00001800 ; mask bit12-11
ParityErr equ 0x00000000 ; parity error
TargetErr equ 0x00001000 ; target abort
MasterErr equ 0x00000800 ; master error
TUNF equ 0x00000400 ; transmit underflow
ROVF equ 0x00000200 ; receive overflow
ETI equ 0x00000100 ; transmit early int
ERI equ 0x00000080 ; receive early int
CNTOVF equ 0x00000040 ; counter overflow
RBU equ 0x00000020 ; receive buffer unavailable
TBU equ 0x00000010 ; transmit buffer unavilable
TI equ 0x00000008 ; transmit interrupt
RI equ 0x00000004 ; receive interrupt
RxErr equ 0x00000002 ; receive error
RFCON = 0x00020000 ; receive flow control xon packet
RFCOFF = 0x00010000 ; receive flow control xoff packet
LSCStatus = 0x00008000 ; link status change
ANCStatus = 0x00004000 ; autonegotiation completed
FBE = 0x00002000 ; fatal bus error
FBEMask = 0x00001800 ; mask bit12-11
ParityErr = 0x00000000 ; parity error
TargetErr = 0x00001000 ; target abort
MasterErr = 0x00000800 ; master error
TUNF = 0x00000400 ; transmit underflow
ROVF = 0x00000200 ; receive overflow
ETI = 0x00000100 ; transmit early int
ERI = 0x00000080 ; receive early int
CNTOVF = 0x00000040 ; counter overflow
RBU = 0x00000020 ; receive buffer unavailable
TBU = 0x00000010 ; transmit buffer unavilable
TI = 0x00000008 ; transmit interrupt
RI = 0x00000004 ; receive interrupt
RxErr = 0x00000002 ; receive error
; Bits in the NetworkConfig register.
RxModeMask equ 0xe0
AcceptAllPhys equ 0x80 ; promiscuous mode
AcceptBroadcast equ 0x40 ; accept broadcast
AcceptMulticast equ 0x20 ; accept mutlicast
AcceptRunt equ 0x08 ; receive runt pkt
ALP equ 0x04 ; receive long pkt
AcceptErr equ 0x02 ; receive error pkt
RxModeMask = 0xe0
AcceptAllPhys = 0x80 ; promiscuous mode
AcceptBroadcast = 0x40 ; accept broadcast
AcceptMulticast = 0x20 ; accept mutlicast
AcceptRunt = 0x08 ; receive runt pkt
ALP = 0x04 ; receive long pkt
AcceptErr = 0x02 ; receive error pkt
AcceptMyPhys equ 0x00000000
RxEnable equ 0x00000001
RxFlowCtrl equ 0x00002000
TxEnable equ 0x00040000
TxModeFDX equ 0x00100000
TxThreshold equ 0x00e00000
AcceptMyPhys = 0x00000000
RxEnable = 0x00000001
RxFlowCtrl = 0x00002000
TxEnable = 0x00040000
TxModeFDX = 0x00100000
TxThreshold = 0x00e00000
PS1000 equ 0x00010000
PS10 equ 0x00080000
FD equ 0x00100000
PS1000 = 0x00010000
PS10 = 0x00080000
FD = 0x00100000
; Bits in network_desc.status
RXOWN equ 0x80000000 ; own bit
FLNGMASK equ 0x0fff0000 ; frame length
FLNGShift equ 16
MARSTATUS equ 0x00004000 ; multicast address received
BARSTATUS equ 0x00002000 ; broadcast address received
PHYSTATUS equ 0x00001000 ; physical address received
RXFSD equ 0x00000800 ; first descriptor
RXLSD equ 0x00000400 ; last descriptor
ErrorSummary equ 0x80 ; error summary
RUNT equ 0x40 ; runt packet received
LONG equ 0x20 ; long packet received
FAE equ 0x10 ; frame align error
CRC equ 0x08 ; crc error
RXER equ 0x04 ; receive error
RXOWN = 0x80000000 ; own bit
FLNGMASK = 0x0fff0000 ; frame length
FLNGShift = 16
MARSTATUS = 0x00004000 ; multicast address received
BARSTATUS = 0x00002000 ; broadcast address received
PHYSTATUS = 0x00001000 ; physical address received
RXFSD = 0x00000800 ; first descriptor
RXLSD = 0x00000400 ; last descriptor
ErrorSummary = 0x80 ; error summary
RUNT = 0x40 ; runt packet received
LONG = 0x20 ; long packet received
FAE = 0x10 ; frame align error
CRC = 0x08 ; crc error
RXER = 0x04 ; receive error
; rx_desc_control_bits
RXIC equ 0x00800000 ; interrupt control
RBSShift equ 0
RXIC = 0x00800000 ; interrupt control
RBSShift = 0
; tx_desc_status_bits
TXOWN equ 0x80000000 ; own bit
JABTO equ 0x00004000 ; jabber timeout
CSL equ 0x00002000 ; carrier sense lost
LC equ 0x00001000 ; late collision
EC equ 0x00000800 ; excessive collision
UDF equ 0x00000400 ; fifo underflow
DFR equ 0x00000200 ; deferred
HF equ 0x00000100 ; heartbeat fail
NCRMask equ 0x000000ff ; collision retry count
NCRShift equ 0
TXOWN = 0x80000000 ; own bit
JABTO = 0x00004000 ; jabber timeout
CSL = 0x00002000 ; carrier sense lost
LC = 0x00001000 ; late collision
EC = 0x00000800 ; excessive collision
UDF = 0x00000400 ; fifo underflow
DFR = 0x00000200 ; deferred
HF = 0x00000100 ; heartbeat fail
NCRMask = 0x000000ff ; collision retry count
NCRShift = 0
; tx_desc_control_bits
TXIC equ 0x80000000 ; interrupt control
ETIControl equ 0x40000000 ; early transmit interrupt
TXLD equ 0x20000000 ; last descriptor
TXFD equ 0x10000000 ; first descriptor
CRCEnable equ 0x08000000 ; crc control
PADEnable equ 0x04000000 ; padding control
RetryTxLC equ 0x02000000 ; retry late collision
PKTSMask equ 0x3ff800 ; packet size bit21-11
PKTSShift equ 11
TBSMask equ 0x000007ff ; transmit buffer bit 10-0
TBSShift equ 0
TXIC = 0x80000000 ; interrupt control
ETIControl = 0x40000000 ; early transmit interrupt
TXLD = 0x20000000 ; last descriptor
TXFD = 0x10000000 ; first descriptor
CRCEnable = 0x08000000 ; crc control
PADEnable = 0x04000000 ; padding control
RetryTxLC = 0x02000000 ; retry late collision
PKTSMask = 0x3ff800 ; packet size bit21-11
PKTSShift = 11
TBSMask = 0x000007ff ; transmit buffer bit 10-0
TBSShift = 0
; BootROM/EEPROM/MII Management Register
MASK_MIIR_MII_READ equ 0x00000000
MASK_MIIR_MII_WRITE equ 0x00000008
MASK_MIIR_MII_MDO equ 0x00000004
MASK_MIIR_MII_MDI equ 0x00000002
MASK_MIIR_MII_MDC equ 0x00000001
MASK_MIIR_MII_READ = 0x00000000
MASK_MIIR_MII_WRITE = 0x00000008
MASK_MIIR_MII_MDO = 0x00000004
MASK_MIIR_MII_MDI = 0x00000002
MASK_MIIR_MII_MDC = 0x00000001
; ST+OP+PHYAD+REGAD+TA
OP_READ equ 0x6000 ; ST:01+OP:10+PHYAD+REGAD+TA:Z0
OP_WRITE equ 0x5002 ; ST:01+OP:01+PHYAD+REGAD+TA:10
OP_READ = 0x6000 ; ST:01+OP:10+PHYAD+REGAD+TA:Z0
OP_WRITE = 0x5002 ; ST:01+OP:01+PHYAD+REGAD+TA:10
; -------------------------------------------------------------------------
; Constants for Myson PHY
; -------------------------------------------------------------------------
MysonPHYID equ 0xd0000302
MysonPHYID0 equ 0x0302
StatusRegister equ 18
SPEED100 equ 0x0400 ; bit10
FULLMODE equ 0x0800 ; bit11
MysonPHYID = 0xd0000302
MysonPHYID0 = 0x0302
StatusRegister = 18
SPEED100 = 0x0400 ; bit10
FULLMODE = 0x0800 ; bit11
; -------------------------------------------------------------------------
; Constants for Seeq 80225 PHY
; -------------------------------------------------------------------------
SeeqPHYID0 equ 0x0016
MIIRegister18 equ 18
SPD_DET_100 equ 0x80
DPLX_DET_FULL equ 0x40
SeeqPHYID0 = 0x0016
MIIRegister18 = 18
SPD_DET_100 = 0x80
DPLX_DET_FULL = 0x40
; -------------------------------------------------------------------------
; Constants for Ahdoc 101 PHY
; -------------------------------------------------------------------------
AhdocPHYID0 equ 0x0022
DiagnosticReg equ 18
DPLX_FULL equ 0x0800
Speed_100 equ 0x0400
AhdocPHYID0 = 0x0022
DiagnosticReg = 18
DPLX_FULL = 0x0800
Speed_100 = 0x0400
; --------------------------------------------------------------------------
; Constants
; --------------------------------------------------------------------------
MarvellPHYID0 equ 0x0141
LevelOnePHYID0 equ 0x0013
MarvellPHYID0 = 0x0141
LevelOnePHYID0 = 0x0013
MII1000BaseTControlReg equ 9
MII1000BaseTStatusReg equ 10
SpecificReg equ 17
MII1000BaseTControlReg = 9
MII1000BaseTStatusReg = 10
SpecificReg = 17
; for 1000BaseT Control Register
PHYAbletoPerform1000FullDuplex equ 0x0200
PHYAbletoPerform1000HalfDuplex equ 0x0100
PHY1000AbilityMask equ 0x300
PHYAbletoPerform1000FullDuplex = 0x0200
PHYAbletoPerform1000HalfDuplex = 0x0100
PHY1000AbilityMask = 0x300
; for phy specific status register, marvell phy.
SpeedMask equ 0x0c000
Speed_1000M equ 0x08000
Speed_100M equ 0x4000
Speed_10M equ 0
Full_Duplex equ 0x2000
SpeedMask = 0x0c000
Speed_1000M = 0x08000
Speed_100M = 0x4000
Speed_10M = 0
Full_Duplex = 0x2000
; for phy specific status register, levelone phy
LXT1000_100M equ 0x08000
LXT1000_1000M equ 0x0c000
LXT1000_Full equ 0x200
LXT1000_100M = 0x08000
LXT1000_1000M = 0x0c000
LXT1000_Full = 0x200
; for PHY
LinkIsUp equ 0x0004
LinkIsUp2 equ 0x00040000
LinkIsUp = 0x0004
LinkIsUp2 = 0x00040000
@ -564,13 +564,13 @@ probe:
cmp [device.dev_id], 0x0803
je .is_803
; int phy, phy_idx equ 0;
; int phy, phy_idx = 0;
;
; for (phy equ 1; phy < 32 && phy_idx < 1; phy++) {
; int mii_status equ mdio_read(nic, phy, 1);
; for (phy = 1; phy < 32 && phy_idx < 1; phy++) {
; int mii_status = mdio_read(nic, phy, 1);
;
; if (mii_status !equ 0xffff && mii_status !equ 0x0000) {
; mtdx.phys[phy_idx] equ phy;
; if (mii_status != 0xffff && mii_status != 0x0000) {
; mtdx.phys[phy_idx] = phy;
;
; DBG ( "%s: MII PHY found at address %d, status "
; "0x%4.4x.\n", mtdx.nic_name, phy, mii_status );
@ -578,26 +578,26 @@ probe:
; {
; unsigned int data;
;
; data equ mdio_read(nic, mtdx.phys[phy_idx], 2);
; if (data equequ SeeqPHYID0)
; mtdx.PHYType equ SeeqPHY;
; else if (data equequ AhdocPHYID0)
; mtdx.PHYType equ AhdocPHY;
; else if (data equequ MarvellPHYID0)
; mtdx.PHYType equ MarvellPHY;
; else if (data equequ MysonPHYID0)
; mtdx.PHYType equ Myson981;
; else if (data equequ LevelOnePHYID0)
; mtdx.PHYType equ LevelOnePHY;
; data = mdio_read(nic, mtdx.phys[phy_idx], 2);
; if (data equ= SeeqPHYID0)
; mtdx.PHYType = SeeqPHY;
; else if (data equ= AhdocPHYID0)
; mtdx.PHYType = AhdocPHY;
; else if (data equ= MarvellPHYID0)
; mtdx.PHYType = MarvellPHY;
; else if (data equ= MysonPHYID0)
; mtdx.PHYType = Myson981;
; else if (data equ= LevelOnePHYID0)
; mtdx.PHYType = LevelOnePHY;
; else
; mtdx.PHYType equ OtherPHY;
; mtdx.PHYType = OtherPHY;
; }
; phy_idx++;
; }
; }
;
; mtdx.mii_cnt equ phy_idx;
; if (phy_idx equequ 0) {
; mtdx.mii_cnt = phy_idx;
; if (phy_idx equ= 0) {
; printf("%s: MII PHY not found -- this device may "
; "not operate correctly.\n", mtdx.nic_name);
; }
@ -847,9 +847,9 @@ getlinkstatus:
.no_myson_phy:
; for (i equ 0; i < DelayTime; ++i) {
; for (i = 0; i < DelayTime; ++i) {
; if (mdio_read(nic, mtdx.phys[0], MII_BMSR) & BMSR_LSTATUS) {
; mtdx.linkok equ 1;
; mtdx.linkok = 1;
; return;
; }
; m80x_delay(100);
@ -878,18 +878,18 @@ getlinktype:
set_io TCRRCR
in eax, dx
mov [device.duplexmode], 1 ; 1 equ half duplex
mov [device.duplexmode], 1 ; 1 = half duplex
test eax, FD
jne @f
DEBUGF 1,"full duplex\n"
inc [device.duplexmode] ; 2 equ full duplex
inc [device.duplexmode] ; 2 = full duplex
@@:
mov [device.line_speed], 1 ; 1 equ 10M
mov [device.line_speed], 1 ; 1 = 10M
test eax, PS10
jne @f
DEBUGF 1,"100mbit\n"
inc [device.line_speed] ; 2 equ 100M
inc [device.line_speed] ; 2 = 100M
@@:
ret
@ -898,88 +898,88 @@ getlinktype:
DEBUGF 1,"no myson phy\n"
; if (mtdx.PHYType equequ SeeqPHY) { /* this PHY is SEEQ 80225 */
; if (mtdx.PHYType equ= SeeqPHY) { /* this PHY is SEEQ 80225 */
; unsigned int data;
;
; data equ mdio_read(dev, mtdx.phys[0], MIIRegister18);
; data = mdio_read(dev, mtdx.phys[0], MIIRegister18);
; if (data & SPD_DET_100)
; mtdx.line_speed equ 2; /* 100M */
; mtdx.line_speed = 2; /* 100M */
; else
; mtdx.line_speed equ 1; /* 10M */
; mtdx.line_speed = 1; /* 10M */
; if (data & DPLX_DET_FULL)
; mtdx.duplexmode equ 2; /* full duplex mode */
; mtdx.duplexmode = 2; /* full duplex mode */
; else
; mtdx.duplexmode equ 1; /* half duplex mode */
; } else if (mtdx.PHYType equequ AhdocPHY) {
; mtdx.duplexmode = 1; /* half duplex mode */
; } else if (mtdx.PHYType equ= AhdocPHY) {
; unsigned int data;
;
; data equ mdio_read(dev, mtdx.phys[0], DiagnosticReg);
; data = mdio_read(dev, mtdx.phys[0], DiagnosticReg);
; if (data & Speed_100)
; mtdx.line_speed equ 2; /* 100M */
; mtdx.line_speed = 2; /* 100M */
; else
; mtdx.line_speed equ 1; /* 10M */
; mtdx.line_speed = 1; /* 10M */
; if (data & DPLX_FULL)
; mtdx.duplexmode equ 2; /* full duplex mode */
; mtdx.duplexmode = 2; /* full duplex mode */
; else
; mtdx.duplexmode equ 1; /* half duplex mode */
; mtdx.duplexmode = 1; /* half duplex mode */
; }
; else if (mtdx.PHYType equequ MarvellPHY) {
; else if (mtdx.PHYType equ= MarvellPHY) {
; unsigned int data;
;
; data equ mdio_read(dev, mtdx.phys[0], SpecificReg);
; data = mdio_read(dev, mtdx.phys[0], SpecificReg);
; if (data & Full_Duplex)
; mtdx.duplexmode equ 2; /* full duplex mode */
; mtdx.duplexmode = 2; /* full duplex mode */
; else
; mtdx.duplexmode equ 1; /* half duplex mode */
; data &equ SpeedMask;
; if (data equequ Speed_1000M)
; mtdx.line_speed equ 3; /* 1000M */
; else if (data equequ Speed_100M)
; mtdx.line_speed equ 2; /* 100M */
; mtdx.duplexmode = 1; /* half duplex mode */
; data &= SpeedMask;
; if (data equ= Speed_1000M)
; mtdx.line_speed = 3; /* 1000M */
; else if (data equ= Speed_100M)
; mtdx.line_speed = 2; /* 100M */
; else
; mtdx.line_speed equ 1; /* 10M */
; mtdx.line_speed = 1; /* 10M */
; }
; else if (mtdx.PHYType equequ Myson981) {
; else if (mtdx.PHYType equ= Myson981) {
; unsigned int data;
;
; data equ mdio_read(dev, mtdx.phys[0], StatusRegister);
; data = mdio_read(dev, mtdx.phys[0], StatusRegister);
;
; if (data & SPEED100)
; mtdx.line_speed equ 2;
; mtdx.line_speed = 2;
; else
; mtdx.line_speed equ 1;
; mtdx.line_speed = 1;
;
; if (data & FULLMODE)
; mtdx.duplexmode equ 2;
; mtdx.duplexmode = 2;
; else
; mtdx.duplexmode equ 1;
; mtdx.duplexmode = 1;
; }
; else if (mtdx.PHYType equequ LevelOnePHY) {
; else if (mtdx.PHYType equ= LevelOnePHY) {
; unsigned int data;
;
; data equ mdio_read(dev, mtdx.phys[0], SpecificReg);
; data = mdio_read(dev, mtdx.phys[0], SpecificReg);
; if (data & LXT1000_Full)
; mtdx.duplexmode equ 2; /* full duplex mode */
; mtdx.duplexmode = 2; /* full duplex mode */
; else
; mtdx.duplexmode equ 1; /* half duplex mode */
; data &equ SpeedMask;
; if (data equequ LXT1000_1000M)
; mtdx.line_speed equ 3; /* 1000M */
; else if (data equequ LXT1000_100M)
; mtdx.line_speed equ 2; /* 100M */
; mtdx.duplexmode = 1; /* half duplex mode */
; data &= SpeedMask;
; if (data equ= LXT1000_1000M)
; mtdx.line_speed = 3; /* 1000M */
; else if (data equ= LXT1000_100M)
; mtdx.line_speed = 2; /* 100M */
; else
; mtdx.line_speed equ 1; /* 10M */
; mtdx.line_speed = 1; /* 10M */
; }
; // chage crvalue
; // mtdx.crvalue&equ(~PS10)&(~FD);
; mtdx.crvalue &equ (~PS10) & (~FD) & (~PS1000);
; if (mtdx.line_speed equequ 1)
; mtdx.crvalue |equ PS10;
; else if (mtdx.line_speed equequ 3)
; mtdx.crvalue |equ PS1000;
; if (mtdx.duplexmode equequ 2)
; mtdx.crvalue |equ FD;
; mtdx.crvalue &= (~PS10) & (~FD) & (~PS1000);
; if (mtdx.line_speed equ= 1)
; mtdx.crvalue |= PS10;
; else if (mtdx.line_speed equ= 3)
; mtdx.crvalue |= PS1000;
; if (mtdx.duplexmode equ= 2)
; mtdx.crvalue |= FD;
;
ret

410
kernel/branches/net/drivers/pcnet32.asm
View File

@ -18,14 +18,14 @@
format MS COFF
API_VERSION equ 0x01000100
API_VERSION = 0x01000100
DEBUG equ 1
__DEBUG__ equ 1
__DEBUG_LEVEL__ equ 1
DEBUG = 1
__DEBUG__ = 1
__DEBUG_LEVEL__ = 1
MAX_DEVICES equ 4
MAX_ETH_FRAME_SIZE equ 1514
MAX_DEVICES = 4
MAX_ETH_FRAME_SIZE = 1514
include 'proc32.inc'
include 'imports.inc'
@ -105,246 +105,246 @@ virtual at 0
buf_head buf_head
end virtual
PCNET_PORT_AUI equ 0x00
PCNET_PORT_10BT equ 0x01
PCNET_PORT_GPSI equ 0x02
PCNET_PORT_MII equ 0x03
PCNET_PORT_PORTSEL equ 0x03
PCNET_PORT_ASEL equ 0x04
PCNET_PORT_100 equ 0x40
PCNET_PORT_FD equ 0x80
PCNET_PORT_AUI = 0x00
PCNET_PORT_10BT = 0x01
PCNET_PORT_GPSI = 0x02
PCNET_PORT_MII = 0x03
PCNET_PORT_PORTSEL = 0x03
PCNET_PORT_ASEL = 0x04
PCNET_PORT_100 = 0x40
PCNET_PORT_FD = 0x80
PCNET_DMA_MASK equ 0xffffffff
PCNET_DMA_MASK = 0xffffffff
PCNET_LOG_TX_BUFFERS equ 2
PCNET_LOG_RX_BUFFERS equ 2
PCNET_LOG_TX_BUFFERS = 2
PCNET_LOG_RX_BUFFERS = 2
PCNET_TX_RING_SIZE equ 4
PCNET_TX_RING_MOD_MASK equ (PCNET_TX_RING_SIZE-1)
PCNET_TX_RING_LEN_BITS equ (PCNET_LOG_TX_BUFFERS shl 12)
PCNET_TX_RING_SIZE = 4
PCNET_TX_RING_MOD_MASK = (PCNET_TX_RING_SIZE-1)
PCNET_TX_RING_LEN_BITS = (PCNET_LOG_TX_BUFFERS shl 12)
PCNET_RX_RING_SIZE equ 4
PCNET_RX_RING_MOD_MASK equ (PCNET_RX_RING_SIZE-1)
PCNET_RX_RING_LEN_BITS equ (PCNET_LOG_RX_BUFFERS shl 4)
PCNET_RX_RING_SIZE = 4
PCNET_RX_RING_MOD_MASK = (PCNET_RX_RING_SIZE-1)
PCNET_RX_RING_LEN_BITS = (PCNET_LOG_RX_BUFFERS shl 4)
PCNET_PKT_BUF_SZ equ 1544
PCNET_PKT_BUF_SZ_NEG equ 0xf9f8
PCNET_PKT_BUF_SZ = 1544
PCNET_PKT_BUF_SZ_NEG = 0xf9f8
PCNET_WIO_RDP equ 0x10
PCNET_WIO_RAP equ 0x12
PCNET_WIO_RESET equ 0x14
PCNET_WIO_BDP equ 0x16
PCNET_DWIO_RDP equ 0x10
PCNET_DWIO_RAP equ 0x14
PCNET_DWIO_RESET equ 0x18
PCNET_DWIO_BDP equ 0x1C
PCNET_TOTAL_SIZE equ 0x20
PCNET_WIO_RDP = 0x10
PCNET_WIO_RAP = 0x12
PCNET_WIO_RESET = 0x14
PCNET_WIO_BDP = 0x16
PCNET_DWIO_RDP = 0x10
PCNET_DWIO_RAP = 0x14
PCNET_DWIO_RESET = 0x18
PCNET_DWIO_BDP = 0x1C
PCNET_TOTAL_SIZE = 0x20
; CSR registers
PCNET_CSR_CSR equ 0x00
PCNET_CSR_IAB0 equ 0x01
PCNET_CSR_IAB1 equ 0x02
PCNET_CSR_IMR equ 0x03
PCNET_CSR_TFEAT equ 0x04
PCNET_CSR_EXTCTL1 equ 0x05
PCNET_CSR_DTBLLEN equ 0x06
PCNET_CSR_EXTCTL2 equ 0x07
PCNET_CSR_MAR0 equ 0x08
PCNET_CSR_MAR1 equ 0x09
PCNET_CSR_MAR2 equ 0x0A
PCNET_CSR_MAR3 equ 0x0B
PCNET_CSR_PAR0 equ 0x0C
PCNET_CSR_PAR1 equ 0x0D
PCNET_CSR_PAR2 equ 0x0E
PCNET_CSR_MODE equ 0x0F
PCNET_CSR_RXADDR0 equ 0x18
PCNET_CSR_RXADDR1 equ 0x19
PCNET_CSR_TXADDR0 equ 0x1E
PCNET_CSR_TXADDR1 equ 0x1F
PCNET_CSR_TXPOLL equ 0x2F
PCNET_CSR_RXPOLL equ 0x31
PCNET_CSR_RXRINGLEN equ 0x4C
PCNET_CSR_TXRINGLEN equ 0x4E
PCNET_CSR_DMACTL equ 0x50
PCNET_CSR_BUSTIMER equ 0x52
PCNET_CSR_MEMERRTIMEO equ 0x64
PCNET_CSR_ONNOWMISC equ 0x74
PCNET_CSR_ADVFEAT equ 0x7A
PCNET_CSR_MACCFG equ 0x7D
PCNET_CSR_CHIPID0 equ 0x58
PCNET_CSR_CHIPID1 equ 0x59
PCNET_CSR_CSR = 0x00
PCNET_CSR_IAB0 = 0x01
PCNET_CSR_IAB1 = 0x02
PCNET_CSR_IMR = 0x03
PCNET_CSR_TFEAT = 0x04
PCNET_CSR_EXTCTL1 = 0x05
PCNET_CSR_DTBLLEN = 0x06
PCNET_CSR_EXTCTL2 = 0x07
PCNET_CSR_MAR0 = 0x08
PCNET_CSR_MAR1 = 0x09
PCNET_CSR_MAR2 = 0x0A
PCNET_CSR_MAR3 = 0x0B
PCNET_CSR_PAR0 = 0x0C
PCNET_CSR_PAR1 = 0x0D
PCNET_CSR_PAR2 = 0x0E
PCNET_CSR_MODE = 0x0F
PCNET_CSR_RXADDR0 = 0x18
PCNET_CSR_RXADDR1 = 0x19
PCNET_CSR_TXADDR0 = 0x1E
PCNET_CSR_TXADDR1 = 0x1F
PCNET_CSR_TXPOLL = 0x2F
PCNET_CSR_RXPOLL = 0x31
PCNET_CSR_RXRINGLEN = 0x4C
PCNET_CSR_TXRINGLEN = 0x4E
PCNET_CSR_DMACTL = 0x50
PCNET_CSR_BUSTIMER = 0x52
PCNET_CSR_MEMERRTIMEO = 0x64
PCNET_CSR_ONNOWMISC = 0x74
PCNET_CSR_ADVFEAT = 0x7A
PCNET_CSR_MACCFG = 0x7D
PCNET_CSR_CHIPID0 = 0x58
PCNET_CSR_CHIPID1 = 0x59
; Control and Status Register (CSR0)
PCNET_CSR_INIT equ 1 shl 0
PCNET_CSR_START equ 1 shl 1
PCNET_CSR_STOP equ 1 shl 2
PCNET_CSR_TX equ 1 shl 3
PCNET_CSR_TXON equ 1 shl 4
PCNET_CSR_RXON equ 1 shl 5
PCNET_CSR_INTEN equ 1 shl 6
PCNET_CSR_INTR equ 1 shl 7
PCNET_CSR_IDONE equ 1 shl 8
PCNET_CSR_TINT equ 1 shl 9
PCNET_CSR_RINT equ 1 shl 10
PCNET_CSR_MERR equ 1 shl 11
PCNET_CSR_MISS equ 1 shl 12
PCNET_CSR_CERR equ 1 shl 13
PCNET_CSR_INIT = 1 shl 0
PCNET_CSR_START = 1 shl 1
PCNET_CSR_STOP = 1 shl 2
PCNET_CSR_TX = 1 shl 3
PCNET_CSR_TXON = 1 shl 4
PCNET_CSR_RXON = 1 shl 5
PCNET_CSR_INTEN = 1 shl 6
PCNET_CSR_INTR = 1 shl 7
PCNET_CSR_IDONE = 1 shl 8
PCNET_CSR_TINT = 1 shl 9
PCNET_CSR_RINT = 1 shl 10
PCNET_CSR_MERR = 1 shl 11
PCNET_CSR_MISS = 1 shl 12
PCNET_CSR_CERR = 1 shl 13
; Interrupt masks and deferral control (CSR3)
PCNET_IMR_BSWAP equ 0x0004
PCNET_IMR_ENMBA equ 0x0008 ; enable modified backoff alg
PCNET_IMR_DXMT2PD equ 0x0010
PCNET_IMR_LAPPEN equ 0x0020 ; lookahead packet processing enb
PCNET_IMR_DXSUFLO equ 0x0040 ; disable TX stop on underflow
PCNET_IMR_IDONE equ 0x0100
PCNET_IMR_TINT equ 0x0200
PCNET_IMR_RINT equ 0x0400
PCNET_IMR_MERR equ 0x0800
PCNET_IMR_MISS equ 0x1000
PCNET_IMR_BSWAP = 0x0004
PCNET_IMR_ENMBA = 0x0008 ; enable modified backoff alg
PCNET_IMR_DXMT2PD = 0x0010
PCNET_IMR_LAPPEN = 0x0020 ; lookahead packet processing enb
PCNET_IMR_DXSUFLO = 0x0040 ; disable TX stop on underflow
PCNET_IMR_IDONE = 0x0100
PCNET_IMR_TINT = 0x0200
PCNET_IMR_RINT = 0x0400
PCNET_IMR_MERR = 0x0800
PCNET_IMR_MISS = 0x1000
PCNET_IMR equ PCNET_IMR_TINT+PCNET_IMR_RINT+PCNET_IMR_IDONE+PCNET_IMR_MERR+PCNET_IMR_MISS
PCNET_IMR = PCNET_IMR_TINT+PCNET_IMR_RINT+PCNET_IMR_IDONE+PCNET_IMR_MERR+PCNET_IMR_MISS
; Test and features control (CSR4)
PCNET_TFEAT_TXSTRTMASK equ 0x0004
PCNET_TFEAT_TXSTRT equ 0x0008
PCNET_TFEAT_RXCCOFLOWM equ 0x0010 ; Rx collision counter oflow
PCNET_TFEAT_RXCCOFLOW equ 0x0020
PCNET_TFEAT_UINT equ 0x0040
PCNET_TFEAT_UINTREQ equ 0x0080
PCNET_TFEAT_MISSOFLOWM equ 0x0100
PCNET_TFEAT_MISSOFLOW equ 0x0200
PCNET_TFEAT_STRIP_FCS equ 0x0400
PCNET_TFEAT_PAD_TX equ 0x0800
PCNET_TFEAT_TXDPOLL equ 0x1000
PCNET_TFEAT_DMAPLUS equ 0x4000
PCNET_TFEAT_TXSTRTMASK = 0x0004
PCNET_TFEAT_TXSTRT = 0x0008
PCNET_TFEAT_RXCCOFLOWM = 0x0010 ; Rx collision counter oflow
PCNET_TFEAT_RXCCOFLOW = 0x0020
PCNET_TFEAT_UINT = 0x0040
PCNET_TFEAT_UINTREQ = 0x0080
PCNET_TFEAT_MISSOFLOWM = 0x0100
PCNET_TFEAT_MISSOFLOW = 0x0200
PCNET_TFEAT_STRIP_FCS = 0x0400
PCNET_TFEAT_PAD_TX = 0x0800
PCNET_TFEAT_TXDPOLL = 0x1000
PCNET_TFEAT_DMAPLUS = 0x4000
; Extended control and interrupt 1 (CSR5)
PCNET_EXTCTL1_SPND equ 0x0001 ; suspend
PCNET_EXTCTL1_MPMODE equ 0x0002 ; magic packet mode
PCNET_EXTCTL1_MPENB equ 0x0004 ; magic packet enable
PCNET_EXTCTL1_MPINTEN equ 0x0008 ; magic packet interrupt enable
PCNET_EXTCTL1_MPINT equ 0x0010 ; magic packet interrupt
PCNET_EXTCTL1_MPPLBA equ 0x0020 ; magic packet phys. logical bcast
PCNET_EXTCTL1_EXDEFEN equ 0x0040 ; excessive deferral interrupt enb.
PCNET_EXTCTL1_EXDEF equ 0x0080 ; excessive deferral interrupt
PCNET_EXTCTL1_SINTEN equ 0x0400 ; system interrupt enable
PCNET_EXTCTL1_SINT equ 0x0800 ; system interrupt
PCNET_EXTCTL1_LTINTEN equ 0x4000 ; last TX interrupt enb
PCNET_EXTCTL1_TXOKINTD equ 0x8000 ; TX OK interrupt disable
PCNET_EXTCTL1_SPND = 0x0001 ; suspend
PCNET_EXTCTL1_MPMODE = 0x0002 ; magic packet mode
PCNET_EXTCTL1_MPENB = 0x0004 ; magic packet enable
PCNET_EXTCTL1_MPINTEN = 0x0008 ; magic packet interrupt enable
PCNET_EXTCTL1_MPINT = 0x0010 ; magic packet interrupt
PCNET_EXTCTL1_MPPLBA = 0x0020 ; magic packet phys. logical bcast
PCNET_EXTCTL1_EXDEFEN = 0x0040 ; excessive deferral interrupt enb.
PCNET_EXTCTL1_EXDEF = 0x0080 ; excessive deferral interrupt
PCNET_EXTCTL1_SINTEN = 0x0400 ; system interrupt enable
PCNET_EXTCTL1_SINT = 0x0800 ; system interrupt
PCNET_EXTCTL1_LTINTEN = 0x4000 ; last TX interrupt enb
PCNET_EXTCTL1_TXOKINTD = 0x8000 ; TX OK interrupt disable
; RX/TX descriptor len (CSR6)
PCNET_DTBLLEN_RLEN equ 0x0F00
PCNET_DTBLLEN_TLEN equ 0xF000
PCNET_DTBLLEN_RLEN = 0x0F00
PCNET_DTBLLEN_TLEN = 0xF000
; Extended control and interrupt 2 (CSR7)
PCNET_EXTCTL2_MIIPDTINTE equ 0x0001
PCNET_EXTCTL2_MIIPDTINT equ 0x0002
PCNET_EXTCTL2_MCCIINTE equ 0x0004
PCNET_EXTCTL2_MCCIINT equ 0x0008
PCNET_EXTCTL2_MCCINTE equ 0x0010
PCNET_EXTCTL2_MCCINT equ 0x0020
PCNET_EXTCTL2_MAPINTE equ 0x0040
PCNET_EXTCTL2_MAPINT equ 0x0080
PCNET_EXTCTL2_MREINTE equ 0x0100
PCNET_EXTCTL2_MREINT equ 0x0200
PCNET_EXTCTL2_STINTE equ 0x0400
PCNET_EXTCTL2_STINT equ 0x0800
PCNET_EXTCTL2_RXDPOLL equ 0x1000
PCNET_EXTCTL2_RDMD equ 0x2000
PCNET_EXTCTL2_RXFRTG equ 0x4000
PCNET_EXTCTL2_FASTSPNDE equ 0x8000
PCNET_EXTCTL2_MIIPDTINTE = 0x0001
PCNET_EXTCTL2_MIIPDTINT = 0x0002
PCNET_EXTCTL2_MCCIINTE = 0x0004
PCNET_EXTCTL2_MCCIINT = 0x0008
PCNET_EXTCTL2_MCCINTE = 0x0010
PCNET_EXTCTL2_MCCINT = 0x0020
PCNET_EXTCTL2_MAPINTE = 0x0040
PCNET_EXTCTL2_MAPINT = 0x0080
PCNET_EXTCTL2_MREINTE = 0x0100
PCNET_EXTCTL2_MREINT = 0x0200
PCNET_EXTCTL2_STINTE = 0x0400
PCNET_EXTCTL2_STINT = 0x0800
PCNET_EXTCTL2_RXDPOLL = 0x1000
PCNET_EXTCTL2_RDMD = 0x2000
PCNET_EXTCTL2_RXFRTG = 0x4000
PCNET_EXTCTL2_FASTSPNDE = 0x8000
; Mode (CSR15)
PCNET_MODE_RXD equ 0x0001 ; RX disable
PCNET_MODE_TXD equ 0x0002 ; TX disable
PCNET_MODE_LOOP equ 0x0004 ; loopback enable
PCNET_MODE_TXCRCD equ 0x0008
PCNET_MODE_FORCECOLL equ 0x0010
PCNET_MODE_RETRYD equ 0x0020
PCNET_MODE_INTLOOP equ 0x0040
PCNET_MODE_PORTSEL equ 0x0180
PCNET_MODE_RXVPAD equ 0x2000
PCNET_MODE_RXNOBROAD equ 0x4000
PCNET_MODE_PROMISC equ 0x8000
PCNET_MODE_RXD = 0x0001 ; RX disable
PCNET_MODE_TXD = 0x0002 ; TX disable
PCNET_MODE_LOOP = 0x0004 ; loopback enable
PCNET_MODE_TXCRCD = 0x0008
PCNET_MODE_FORCECOLL = 0x0010
PCNET_MODE_RETRYD = 0x0020
PCNET_MODE_INTLOOP = 0x0040
PCNET_MODE_PORTSEL = 0x0180
PCNET_MODE_RXVPAD = 0x2000
PCNET_MODE_RXNOBROAD = 0x4000
PCNET_MODE_PROMISC = 0x8000
; BCR (Bus Control Registers)
PCNET_BCR_MMRA equ 0x00 ; Master Mode Read Active
PCNET_BCR_MMW equ 0x01 ; Master Mode Write Active
PCNET_BCR_MISCCFG equ 0x02
PCNET_BCR_LED0 equ 0x04
PCNET_BCR_LED1 equ 0x05
PCNET_BCR_LED2 equ 0x06
PCNET_BCR_LED3 equ 0x07
PCNET_BCR_DUPLEX equ 0x09
PCNET_BCR_BUSCTL equ 0x12
PCNET_BCR_EECTL equ 0x13
PCNET_BCR_SSTYLE equ 0x14
PCNET_BCR_PCILAT equ 0x16
PCNET_BCR_PCISUBVENID equ 0x17
PCNET_BCR_PCISUBSYSID equ 0x18
PCNET_BCR_SRAMSIZE equ 0x19
PCNET_BCR_SRAMBOUND equ 0x1A
PCNET_BCR_SRAMCTL equ 0x1B
PCNET_BCR_MIICTL equ 0x20
PCNET_BCR_MIIADDR equ 0x21
PCNET_BCR_MIIDATA equ 0x22
PCNET_BCR_PCIVENID equ 0x23
PCNET_BCR_PCIPCAP equ 0x24
PCNET_BCR_DATA0 equ 0x25
PCNET_BCR_DATA1 equ 0x26
PCNET_BCR_DATA2 equ 0x27
PCNET_BCR_DATA3 equ 0x28
PCNET_BCR_DATA4 equ 0x29
PCNET_BCR_DATA5 equ 0x2A
PCNET_BCR_DATA6 equ 0x2B
PCNET_BCR_DATA7 equ 0x2C
PCNET_BCR_ONNOWPAT0 equ 0x2D
PCNET_BCR_ONNOWPAT1 equ 0x2E
PCNET_BCR_ONNOWPAT2 equ 0x2F
PCNET_BCR_PHYSEL equ 0x31
PCNET_BCR_MMRA = 0x00 ; Master Mode Read Active
PCNET_BCR_MMW = 0x01 ; Master Mode Write Active
PCNET_BCR_MISCCFG = 0x02
PCNET_BCR_LED0 = 0x04
PCNET_BCR_LED1 = 0x05
PCNET_BCR_LED2 = 0x06
PCNET_BCR_LED3 = 0x07
PCNET_BCR_DUPLEX = 0x09
PCNET_BCR_BUSCTL = 0x12
PCNET_BCR_EECTL = 0x13
PCNET_BCR_SSTYLE = 0x14
PCNET_BCR_PCILAT = 0x16
PCNET_BCR_PCISUBVENID = 0x17
PCNET_BCR_PCISUBSYSID = 0x18
PCNET_BCR_SRAMSIZE = 0x19
PCNET_BCR_SRAMBOUND = 0x1A
PCNET_BCR_SRAMCTL = 0x1B
PCNET_BCR_MIICTL = 0x20
PCNET_BCR_MIIADDR = 0x21
PCNET_BCR_MIIDATA = 0x22
PCNET_BCR_PCIVENID = 0x23
PCNET_BCR_PCIPCAP = 0x24
PCNET_BCR_DATA0 = 0x25
PCNET_BCR_DATA1 = 0x26
PCNET_BCR_DATA2 = 0x27
PCNET_BCR_DATA3 = 0x28
PCNET_BCR_DATA4 = 0x29
PCNET_BCR_DATA5 = 0x2A
PCNET_BCR_DATA6 = 0x2B
PCNET_BCR_DATA7 = 0x2C
PCNET_BCR_ONNOWPAT0 = 0x2D
PCNET_BCR_ONNOWPAT1 = 0x2E
PCNET_BCR_ONNOWPAT2 = 0x2F
PCNET_BCR_PHYSEL = 0x31
; RX status register
PCNET_RXSTAT_BPE equ 0x0080 ; bus parity error
PCNET_RXSTAT_ENP equ 0x0100 ; end of packet
PCNET_RXSTAT_STP equ 0x0200 ; start of packet
PCNET_RXSTAT_BUFF equ 0x0400 ; buffer error
PCNET_RXSTAT_CRC equ 0x0800 ; CRC error
PCNET_RXSTAT_OFLOW equ 0x1000 ; rx overrun
PCNET_RXSTAT_FRAM equ 0x2000 ; framing error
PCNET_RXSTAT_ERR equ 0x4000 ; error summary
PCNET_RXSTAT_OWN equ 0x8000
PCNET_RXSTAT_BPE = 0x0080 ; bus parity error
PCNET_RXSTAT_ENP = 0x0100 ; end of packet
PCNET_RXSTAT_STP = 0x0200 ; start of packet
PCNET_RXSTAT_BUFF = 0x0400 ; buffer error
PCNET_RXSTAT_CRC = 0x0800 ; CRC error
PCNET_RXSTAT_OFLOW = 0x1000 ; rx overrun
PCNET_RXSTAT_FRAM = 0x2000 ; framing error
PCNET_RXSTAT_ERR = 0x4000 ; error summary
PCNET_RXSTAT_OWN = 0x8000
; TX status register
PCNET_TXSTAT_TRC equ 0x0000000F ; transmit retries
PCNET_TXSTAT_RTRY equ 0x04000000 ; retry
PCNET_TXSTAT_LCAR equ 0x08000000 ; lost carrier
PCNET_TXSTAT_LCOL equ 0x10000000 ; late collision
PCNET_TXSTAT_EXDEF equ 0x20000000 ; excessive deferrals
PCNET_TXSTAT_UFLOW equ 0x40000000 ; transmit underrun
PCNET_TXSTAT_BUFF equ 0x80000000 ; buffer error
PCNET_TXSTAT_TRC = 0x0000000F ; transmit retries
PCNET_TXSTAT_RTRY = 0x04000000 ; retry
PCNET_TXSTAT_LCAR = 0x08000000 ; lost carrier
PCNET_TXSTAT_LCOL = 0x10000000 ; late collision
PCNET_TXSTAT_EXDEF = 0x20000000 ; excessive deferrals
PCNET_TXSTAT_UFLOW = 0x40000000 ; transmit underrun
PCNET_TXSTAT_BUFF = 0x80000000 ; buffer error
PCNET_TXCTL_OWN equ 0x80000000
PCNET_TXCTL_ERR equ 0x40000000 ; error summary
PCNET_TXCTL_ADD_FCS equ 0x20000000 ; add FCS to pkt
PCNET_TXCTL_MORE_LTINT equ 0x10000000
PCNET_TXCTL_ONE equ 0x08000000
PCNET_TXCTL_DEF equ 0x04000000
PCNET_TXCTL_STP equ 0x02000000
PCNET_TXCTL_ENP equ 0x01000000
PCNET_TXCTL_BPE equ 0x00800000
PCNET_TXCTL_MBO equ 0x0000F000
PCNET_TXCTL_BUFSZ equ 0x00000FFF
PCNET_TXCTL_OWN = 0x80000000
PCNET_TXCTL_ERR = 0x40000000 ; error summary
PCNET_TXCTL_ADD_FCS = 0x20000000 ; add FCS to pkt
PCNET_TXCTL_MORE_LTINT = 0x10000000
PCNET_TXCTL_ONE = 0x08000000
PCNET_TXCTL_DEF = 0x04000000
PCNET_TXCTL_STP = 0x02000000
PCNET_TXCTL_ENP = 0x01000000
PCNET_TXCTL_BPE = 0x00800000
PCNET_TXCTL_MBO = 0x0000F000
PCNET_TXCTL_BUFSZ = 0x00000FFF

254
kernel/branches/net/drivers/sis900.asm
View File

@ -25,14 +25,14 @@
format MS COFF
API_VERSION equ 0x01000100
DRIVER_VERSION equ 5
API_VERSION = 0x01000100
DRIVER_VERSION = 5
MAX_DEVICES equ 16
MAX_DEVICES = 16
DEBUG equ 1
__DEBUG__ equ 1
__DEBUG_LEVEL__ equ 1
DEBUG = 1
__DEBUG__ = 1
__DEBUG_LEVEL__ = 1
include 'proc32.inc'
include 'imports.inc'
@ -42,11 +42,11 @@ include 'netdrv.inc'
public START
public version
NUM_RX_DESC equ 4 ;* Number of RX descriptors *
NUM_TX_DESC equ 1 ;* Number of TX descriptors *
RX_BUFF_SZ equ 1520 ;* Buffer size for each Rx buffer *
TX_BUFF_SZ equ 1516 ;* Buffer size for each Tx buffer *
MAX_ETH_FRAME_SIZE equ 1516
NUM_RX_DESC = 4 ;* Number of RX descriptors *
NUM_TX_DESC = 1 ;* Number of TX descriptors *
RX_BUFF_SZ = 1520 ;* Buffer size for each Rx buffer *
TX_BUFF_SZ = 1516 ;* Buffer size for each Tx buffer *
MAX_ETH_FRAME_SIZE = 1516
virtual at ebx
device:
@ -271,150 +271,150 @@ ret
;
;********************************************************************
ETH_ALEN equ 6 ; Size of Ethernet address
ETH_HLEN equ 14 ; Size of ethernet header
ETH_ZLEN equ 60 ; Minimum packet length
DSIZE equ 0x00000fff
CRC_SIZE equ 4
RFADDR_shift equ 16
ETH_ALEN = 6 ; Size of Ethernet address
ETH_HLEN = 14 ; Size of ethernet header
ETH_ZLEN = 60 ; Minimum packet length
DSIZE = 0x00000fff
CRC_SIZE = 4
RFADDR_shift = 16
; Symbolic offsets to registers.
cr equ 0x0 ; Command Register
cfg equ 0x4 ; Configuration Register
mear equ 0x8 ; EEPROM Access Register
ptscr equ 0xc ; PCI Test Control Register
isr equ 0x10 ; Interrupt Status Register
imr equ 0x14 ; Interrupt Mask Register
ier equ 0x18 ; Interrupt Enable Register
epar equ 0x18 ; Enhanced PHY Access Register
txdp equ 0x20 ; Transmit Descriptor Pointer Register
txcfg equ 0x24 ; Transmit Configuration Register
rxdp equ 0x30 ; Receive Descriptor Pointer Register
rxcfg equ 0x34 ; Receive Configuration Register
flctrl equ 0x38 ; Flow Control Register
rxlen equ 0x3c ; Receive Packet Length Register
rfcr equ 0x48 ; Receive Filter Control Register
rfdr equ 0x4C ; Receive Filter Data Register
pmctrl equ 0xB0 ; Power Management Control Register
pmer equ 0xB4 ; Power Management Wake-up Event Register
cr = 0x0 ; Command Register
cfg = 0x4 ; Configuration Register
mear = 0x8 ; EEPROM Access Register
ptscr = 0xc ; PCI Test Control Register
isr = 0x10 ; Interrupt Status Register
imr = 0x14 ; Interrupt Mask Register
ier = 0x18 ; Interrupt Enable Register
epar = 0x18 ; Enhanced PHY Access Register
txdp = 0x20 ; Transmit Descriptor Pointer Register
txcfg = 0x24 ; Transmit Configuration Register
rxdp = 0x30 ; Receive Descriptor Pointer Register
rxcfg = 0x34 ; Receive Configuration Register
flctrl = 0x38 ; Flow Control Register
rxlen = 0x3c ; Receive Packet Length Register
rfcr = 0x48 ; Receive Filter Control Register
rfdr = 0x4C ; Receive Filter Data Register
pmctrl = 0xB0 ; Power Management Control Register
pmer = 0xB4 ; Power Management Wake-up Event Register
; Command Register Bits
RELOAD equ 0x00000400
ACCESSMODE equ 0x00000200
RESET equ 0x00000100
SWI equ 0x00000080
RxRESET equ 0x00000020
TxRESET equ 0x00000010
RxDIS equ 0x00000008
RxENA equ 0x00000004
TxDIS equ 0x00000002
TxENA equ 0x00000001
RELOAD = 0x00000400
ACCESSMODE = 0x00000200
RESET = 0x00000100
SWI = 0x00000080
RxRESET = 0x00000020
TxRESET = 0x00000010
RxDIS = 0x00000008
RxENA = 0x00000004
TxDIS = 0x00000002
TxENA = 0x00000001
; Configuration Register Bits
DESCRFMT equ 0x00000100 ; 7016 specific
REQALG equ 0x00000080
SB equ 0x00000040
POW equ 0x00000020
EXD equ 0x00000010
PESEL equ 0x00000008
LPM equ 0x00000004
BEM equ 0x00000001
RND_CNT equ 0x00000400
FAIR_BACKOFF equ 0x00000200
EDB_MASTER_EN equ 0x00002000
DESCRFMT = 0x00000100 ; 7016 specific
REQALG = 0x00000080
SB = 0x00000040
POW = 0x00000020
EXD = 0x00000010
PESEL = 0x00000008
LPM = 0x00000004
BEM = 0x00000001
RND_CNT = 0x00000400
FAIR_BACKOFF = 0x00000200
EDB_MASTER_EN = 0x00002000
; Eeprom Access Reigster Bits
MDC equ 0x00000040
MDDIR equ 0x00000020
MDIO equ 0x00000010 ; 7016 specific
EECS equ 0x00000008
EECLK equ 0x00000004
EEDO equ 0x00000002
EEDI equ 0x00000001
MDC = 0x00000040
MDDIR = 0x00000020
MDIO = 0x00000010 ; 7016 specific
EECS = 0x00000008
EECLK = 0x00000004
EEDO = 0x00000002
EEDI = 0x00000001
; TX Configuration Register Bits
ATP equ 0x10000000 ;Automatic Transmit Padding
MLB equ 0x20000000 ;Mac Loopback Enable
HBI equ 0x40000000 ;HeartBeat Ignore (Req for full-dup)
CSI equ 0x80000000 ;CarrierSenseIgnore (Req for full-du
ATP = 0x10000000 ;Automatic Transmit Padding
MLB = 0x20000000 ;Mac Loopback Enable
HBI = 0x40000000 ;HeartBeat Ignore (Req for full-dup)
CSI = 0x80000000 ;CarrierSenseIgnore (Req for full-du
; RX Configuration Register Bits
AJAB equ 0x08000000 ;
ATX equ 0x10000000 ;Accept Transmit Packets
ARP equ 0x40000000 ;accept runt packets (<64bytes)
AEP equ 0x80000000 ;accept error packets
AJAB = 0x08000000 ;
ATX = 0x10000000 ;Accept Transmit Packets
ARP = 0x40000000 ;accept runt packets (<64bytes)
AEP = 0x80000000 ;accept error packets
; Interrupt Reigster Bits
WKEVT equ 0x10000000
TxPAUSEEND equ 0x08000000
TxPAUSE equ 0x04000000
TxRCMP equ 0x02000000
RxRCMP equ 0x01000000
DPERR equ 0x00800000
SSERR equ 0x00400000
RMABT equ 0x00200000
RTABT equ 0x00100000
RxSOVR equ 0x00010000
HIBERR equ 0x00008000
SWINT equ 0x00001000
MIBINT equ 0x00000800
TxURN equ 0x00000400
TxIDLE equ 0x00000200
TxERR equ 0x00000100
TxDESC equ 0x00000080
TxOK equ 0x00000040
RxORN equ 0x00000020
RxIDLE equ 0x00000010
RxEARLY equ 0x00000008
RxERR equ 0x00000004
RxDESC equ 0x00000002
RxOK equ 0x00000001
WKEVT = 0x10000000
TxPAUSEEND = 0x08000000
TxPAUSE = 0x04000000
TxRCMP = 0x02000000
RxRCMP = 0x01000000
DPERR = 0x00800000
SSERR = 0x00400000
RMABT = 0x00200000
RTABT = 0x00100000
RxSOVR = 0x00010000
HIBERR = 0x00008000
SWINT = 0x00001000
MIBINT = 0x00000800
TxURN = 0x00000400
TxIDLE = 0x00000200
TxERR = 0x00000100
TxDESC = 0x00000080
TxOK = 0x00000040
RxORN = 0x00000020
RxIDLE = 0x00000010
RxEARLY = 0x00000008
RxERR = 0x00000004
RxDESC = 0x00000002
RxOK = 0x00000001
; Interrupt Enable Register Bits
IE equ RxOK + TxOK
IE = RxOK + TxOK
; Revision ID
SIS900B_900_REV equ 0x03
SIS630A_900_REV equ 0x80
SIS630E_900_REV equ 0x81
SIS630S_900_REV equ 0x82
SIS630EA1_900_REV equ 0x83
SIS630ET_900_REV equ 0x84
SIS635A_900_REV equ 0x90
SIS900_960_REV equ 0x91
SIS900B_900_REV = 0x03
SIS630A_900_REV = 0x80
SIS630E_900_REV = 0x81
SIS630S_900_REV = 0x82
SIS630EA1_900_REV = 0x83
SIS630ET_900_REV = 0x84
SIS635A_900_REV = 0x90
SIS900_960_REV = 0x91
; Receive Filter Control Register Bits
RFEN equ 0x80000000
RFAAB equ 0x40000000
RFAAM equ 0x20000000
RFAAP equ 0x10000000
RFPromiscuous equ 0x70000000
RFEN = 0x80000000
RFAAB = 0x40000000
RFAAM = 0x20000000
RFAAP = 0x10000000
RFPromiscuous = 0x70000000
; Reveive Filter Data Mask
RFDAT equ 0x0000FFFF
RFDAT = 0x0000FFFF
; Eeprom Address
EEPROMSignature equ 0x00
EEPROMVendorID equ 0x02
EEPROMDeviceID equ 0x03
EEPROMMACAddr equ 0x08
EEPROMChecksum equ 0x0b
EEPROMSignature = 0x00
EEPROMVendorID = 0x02
EEPROMDeviceID = 0x03
EEPROMMACAddr = 0x08
EEPROMChecksum = 0x0b
;The EEPROM commands include the alway-set leading bit.
EEread equ 0x0180
EEwrite equ 0x0140
EEerase equ 0x01C0
EEwriteEnable equ 0x0130
EEwriteDisable equ 0x0100
EEeraseAll equ 0x0120
EEwriteAll equ 0x0110
EEaddrMask equ 0x013F
EEcmdShift equ 16
EEread = 0x0180
EEwrite = 0x0140
EEerase = 0x01C0
EEwriteEnable = 0x0130
EEwriteDisable = 0x0100
EEeraseAll = 0x0120
EEwriteAll = 0x0110
EEaddrMask = 0x013F
EEcmdShift = 16
;For SiS962 or SiS963, request the eeprom software access
EEREQ equ 0x00000400
EEDONE equ 0x00000200
EEGNT equ 0x00000100
EEREQ = 0x00000400
EEDONE = 0x00000200
EEGNT = 0x00000100
;***************************************************************************