453 lines
12 KiB
C
453 lines
12 KiB
C
/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <assert.h>
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#include "intel_batchbuffer.h"
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#include "intel_driver.h"
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#include "i965_defines.h"
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#include "i965_structs.h"
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#include "i965_drv_video.h"
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#include "i965_post_processing.h"
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#include "i965_render.h"
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#include "intel_media.h"
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#include "gen8_post_processing.h"
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static const uint32_t pp_null_gen9[][4] = {
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};
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static const uint32_t pp_nv12_load_save_nv12_gen9[][4] = {
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#include "shaders/post_processing/gen9/pl2_to_pl2.g9b"
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};
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static const uint32_t pp_nv12_load_save_pl3_gen9[][4] = {
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#include "shaders/post_processing/gen9/pl2_to_pl3.g9b"
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};
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static const uint32_t pp_pl3_load_save_nv12_gen9[][4] = {
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#include "shaders/post_processing/gen9/pl3_to_pl2.g9b"
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};
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static const uint32_t pp_pl3_load_save_pl3_gen9[][4] = {
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#include "shaders/post_processing/gen9/pl3_to_pl3.g9b"
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};
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static const uint32_t pp_nv12_scaling_gen9[][4] = {
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#include "shaders/post_processing/gen9/pl2_to_pl2.g9b"
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};
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static const uint32_t pp_nv12_avs_gen9[][4] = {
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#include "shaders/post_processing/gen9/pl2_to_pl2.g9b"
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};
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static const uint32_t pp_nv12_dndi_gen9[][4] = {
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};
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static const uint32_t pp_nv12_dn_gen9[][4] = {
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};
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static const uint32_t pp_nv12_load_save_pa_gen9[][4] = {
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#include "shaders/post_processing/gen9/pl2_to_pa.g9b"
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};
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static const uint32_t pp_pl3_load_save_pa_gen9[][4] = {
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#include "shaders/post_processing/gen9/pl3_to_pa.g9b"
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};
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static const uint32_t pp_pa_load_save_nv12_gen9[][4] = {
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#include "shaders/post_processing/gen9/pa_to_pl2.g9b"
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};
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static const uint32_t pp_pa_load_save_pl3_gen9[][4] = {
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#include "shaders/post_processing/gen9/pa_to_pl3.g9b"
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};
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static const uint32_t pp_pa_load_save_pa_gen9[][4] = {
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#include "shaders/post_processing/gen9/pa_to_pa.g9b"
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};
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static const uint32_t pp_rgbx_load_save_nv12_gen9[][4] = {
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#include "shaders/post_processing/gen9/rgbx_to_nv12.g9b"
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};
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static const uint32_t pp_nv12_load_save_rgbx_gen9[][4] = {
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#include "shaders/post_processing/gen9/pl2_to_rgbx.g9b"
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};
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static const uint32_t pp_nv12_blending_gen9[][4] = {
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};
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static struct pp_module pp_modules_gen9[] = {
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{
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{
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"NULL module (for testing)",
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PP_NULL,
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pp_null_gen9,
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sizeof(pp_null_gen9),
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NULL,
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},
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pp_null_initialize,
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},
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{
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{
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"NV12_NV12",
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PP_NV12_LOAD_SAVE_N12,
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pp_nv12_load_save_nv12_gen9,
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sizeof(pp_nv12_load_save_nv12_gen9),
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NULL,
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},
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gen8_pp_plx_avs_initialize,
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},
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{
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{
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"NV12_PL3",
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PP_NV12_LOAD_SAVE_PL3,
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pp_nv12_load_save_pl3_gen9,
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sizeof(pp_nv12_load_save_pl3_gen9),
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NULL,
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},
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gen8_pp_plx_avs_initialize,
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},
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{
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{
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"PL3_NV12",
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PP_PL3_LOAD_SAVE_N12,
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pp_pl3_load_save_nv12_gen9,
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sizeof(pp_pl3_load_save_nv12_gen9),
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NULL,
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},
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gen8_pp_plx_avs_initialize,
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},
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{
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{
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"PL3_PL3",
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PP_PL3_LOAD_SAVE_PL3,
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pp_pl3_load_save_pl3_gen9,
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sizeof(pp_pl3_load_save_pl3_gen9),
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NULL,
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},
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gen8_pp_plx_avs_initialize,
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},
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{
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{
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"NV12 Scaling module",
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PP_NV12_SCALING,
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pp_nv12_scaling_gen9,
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sizeof(pp_nv12_scaling_gen9),
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NULL,
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},
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gen8_pp_plx_avs_initialize,
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},
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{
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{
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"NV12 AVS module",
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PP_NV12_AVS,
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pp_nv12_avs_gen9,
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sizeof(pp_nv12_avs_gen9),
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NULL,
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},
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gen8_pp_plx_avs_initialize,
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},
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{
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{
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"NV12 DNDI module",
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PP_NV12_DNDI,
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pp_nv12_dndi_gen9,
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sizeof(pp_nv12_dndi_gen9),
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NULL,
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},
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pp_null_initialize,
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},
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{
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{
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"NV12 DN module",
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PP_NV12_DN,
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pp_nv12_dn_gen9,
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sizeof(pp_nv12_dn_gen9),
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NULL,
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},
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pp_null_initialize,
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},
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{
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{
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"NV12_PA module",
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PP_NV12_LOAD_SAVE_PA,
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pp_nv12_load_save_pa_gen9,
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sizeof(pp_nv12_load_save_pa_gen9),
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NULL,
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},
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gen8_pp_plx_avs_initialize,
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},
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{
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{
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"PL3_PA module",
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PP_PL3_LOAD_SAVE_PA,
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pp_pl3_load_save_pa_gen9,
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sizeof(pp_pl3_load_save_pa_gen9),
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NULL,
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},
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gen8_pp_plx_avs_initialize,
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},
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{
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{
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"PA_NV12 module",
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PP_PA_LOAD_SAVE_NV12,
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pp_pa_load_save_nv12_gen9,
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sizeof(pp_pa_load_save_nv12_gen9),
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NULL,
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},
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gen8_pp_plx_avs_initialize,
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},
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{
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{
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"PA_PL3 module",
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PP_PA_LOAD_SAVE_PL3,
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pp_pa_load_save_pl3_gen9,
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sizeof(pp_pa_load_save_pl3_gen9),
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NULL,
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},
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gen8_pp_plx_avs_initialize,
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},
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{
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{
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"PA_PA module",
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PP_PA_LOAD_SAVE_PA,
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pp_pa_load_save_pa_gen9,
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sizeof(pp_pa_load_save_pa_gen9),
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NULL,
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},
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gen8_pp_plx_avs_initialize,
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},
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{
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{
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"RGBX_NV12 module",
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PP_RGBX_LOAD_SAVE_NV12,
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pp_rgbx_load_save_nv12_gen9,
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sizeof(pp_rgbx_load_save_nv12_gen9),
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NULL,
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},
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gen8_pp_plx_avs_initialize,
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},
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{
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{
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"NV12_RGBX module",
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PP_NV12_LOAD_SAVE_RGBX,
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pp_nv12_load_save_rgbx_gen9,
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sizeof(pp_nv12_load_save_rgbx_gen9),
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NULL,
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},
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gen8_pp_plx_avs_initialize,
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},
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};
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static const AVSConfig gen9_avs_config = {
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.coeff_frac_bits = 6,
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.coeff_epsilon = 1.0f / (1U << 6),
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.num_phases = 31,
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.num_luma_coeffs = 8,
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.num_chroma_coeffs = 4,
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.coeff_range = {
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.lower_bound = {
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.y_k_h = { -2, -2, -2, -2, -2, -2, -2, -2 },
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.y_k_v = { -2, -2, -2, -2, -2, -2, -2, -2 },
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.uv_k_h = { -2, -2, -2, -2 },
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.uv_k_v = { -2, -2, -2, -2 },
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},
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.upper_bound = {
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.y_k_h = { 2, 2, 2, 2, 2, 2, 2, 2 },
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.y_k_v = { 2, 2, 2, 2, 2, 2, 2, 2 },
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.uv_k_h = { 2, 2, 2, 2 },
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.uv_k_v = { 2, 2, 2, 2 },
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},
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},
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};
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static void
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gen9_pp_pipeline_select(VADriverContextP ctx,
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struct i965_post_processing_context *pp_context)
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{
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struct intel_batchbuffer *batch = pp_context->batch;
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BEGIN_BATCH(batch, 1);
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OUT_BATCH(batch,
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CMD_PIPELINE_SELECT |
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PIPELINE_SELECT_MEDIA |
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GEN9_FORCE_MEDIA_AWAKE_ON |
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GEN9_MEDIA_DOP_GATE_OFF |
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GEN9_PIPELINE_SELECTION_MASK |
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GEN9_MEDIA_DOP_GATE_MASK |
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GEN9_FORCE_MEDIA_AWAKE_MASK);
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ADVANCE_BATCH(batch);
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}
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static void
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gen9_pp_state_base_address(VADriverContextP ctx,
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struct i965_post_processing_context *pp_context)
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{
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struct intel_batchbuffer *batch = pp_context->batch;
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BEGIN_BATCH(batch, 19);
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OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | (19 - 2));
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/* DW1 Generate state address */
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OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
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OUT_BATCH(batch, 0);
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OUT_BATCH(batch, 0);
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/* DW4-5 Surface state address */
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OUT_RELOC64(batch, pp_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
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/* DW6-7 Dynamic state address */
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OUT_RELOC64(batch, pp_context->dynamic_state.bo, I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_SAMPLER,
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0, 0 | BASE_ADDRESS_MODIFY);
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/* DW8. Indirect object address */
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OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
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OUT_BATCH(batch, 0);
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/* DW10-11 Instruction base address */
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OUT_RELOC64(batch, pp_context->instruction_state.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
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OUT_BATCH(batch, 0xFFFF0000 | BASE_ADDRESS_MODIFY);
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OUT_BATCH(batch, 0xFFFF0000 | BASE_ADDRESS_MODIFY);
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OUT_BATCH(batch, 0xFFFF0000 | BASE_ADDRESS_MODIFY);
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OUT_BATCH(batch, 0xFFFF0000 | BASE_ADDRESS_MODIFY);
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/* Bindless surface state base address */
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OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
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OUT_BATCH(batch, 0);
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OUT_BATCH(batch, 0xfffff000);
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ADVANCE_BATCH(batch);
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}
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static void
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gen9_pp_end_pipeline(VADriverContextP ctx,
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struct i965_post_processing_context *pp_context)
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{
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struct intel_batchbuffer *batch = pp_context->batch;
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BEGIN_BATCH(batch, 1);
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OUT_BATCH(batch,
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CMD_PIPELINE_SELECT |
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PIPELINE_SELECT_MEDIA |
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GEN9_FORCE_MEDIA_AWAKE_OFF |
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GEN9_MEDIA_DOP_GATE_ON |
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GEN9_PIPELINE_SELECTION_MASK |
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GEN9_MEDIA_DOP_GATE_MASK |
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GEN9_FORCE_MEDIA_AWAKE_MASK);
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ADVANCE_BATCH(batch);
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}
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static void
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gen9_pp_pipeline_setup(VADriverContextP ctx,
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struct i965_post_processing_context *pp_context)
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{
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struct intel_batchbuffer *batch = pp_context->batch;
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intel_batchbuffer_start_atomic(batch, 0x1000);
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intel_batchbuffer_emit_mi_flush(batch);
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gen9_pp_pipeline_select(ctx, pp_context);
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gen9_pp_state_base_address(ctx, pp_context);
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gen8_pp_vfe_state(ctx, pp_context);
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gen8_pp_curbe_load(ctx, pp_context);
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gen8_interface_descriptor_load(ctx, pp_context);
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gen8_pp_object_walker(ctx, pp_context);
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gen9_pp_end_pipeline(ctx, pp_context);
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intel_batchbuffer_end_atomic(batch);
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}
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static VAStatus
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gen9_post_processing(VADriverContextP ctx,
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struct i965_post_processing_context *pp_context,
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const struct i965_surface *src_surface,
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const VARectangle *src_rect,
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struct i965_surface *dst_surface,
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const VARectangle *dst_rect,
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int pp_index,
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void * filter_param)
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{
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VAStatus va_status;
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va_status = gen8_pp_initialize(ctx, pp_context,
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src_surface,
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src_rect,
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dst_surface,
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dst_rect,
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pp_index,
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filter_param);
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if (va_status == VA_STATUS_SUCCESS) {
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gen8_pp_states_setup(ctx, pp_context);
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gen9_pp_pipeline_setup(ctx, pp_context);
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}
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return va_status;
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}
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void
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gen9_post_processing_context_init(VADriverContextP ctx,
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void *data,
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struct intel_batchbuffer *batch)
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{
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struct i965_post_processing_context *pp_context = data;
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gen8_post_processing_context_common_init(ctx, data, pp_modules_gen9, ARRAY_ELEMS(pp_modules_gen9), batch);
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avs_init_state(&pp_context->pp_avs_context.state, &gen9_avs_config);
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pp_context->intel_post_processing = gen9_post_processing;
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}
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