626 lines
14 KiB
PHP
626 lines
14 KiB
PHP
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; ;;
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;; Copyright (C) KolibriOS team 2004-2007. All rights reserved. ;;
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;; Distributed under terms of the GNU General Public License ;;
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;; ;;
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;; ;;
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;; PCI32.INC ;;
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;; ;;
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;; 32 bit PCI driver code ;;
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;; ;;
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;; Version 0.3 April 9, 2007 ;;
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;; Version 0.2 December 21st, 2002 ;;
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;; ;;
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;; Author: Victor Prodan, victorprodan@yahoo.com ;;
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;; Mihailov Ilia, ghost.nsk@gmail.com ;;
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;; Credits: ;;
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;; Ralf Brown ;;
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;; Mike Hibbett, mikeh@oceanfree.net ;;
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;; ;;
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;; See file COPYING for details ;;
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;; ;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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$Revision$
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;***************************************************************************
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; Function
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; pci_api:
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;
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; Description
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; entry point for system PCI calls
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;***************************************************************************
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;mmio_pci_addr equ 0x400 ; set actual PCI address here to activate user-MMIO
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align 4
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pci_api:
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cmp [pci_access_enabled],1
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jne no_pci_access_for_applications
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or al,al
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jnz pci_fn_1
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; PCI function 0: get pci version (AH.AL)
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movzx eax,word [BOOT_VAR+0x9022]
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ret
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pci_fn_1:
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cmp al,1
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jnz pci_fn_2
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; PCI function 1: get last bus in AL
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mov al,[BOOT_VAR+0x9021]
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ret
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pci_fn_2:
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cmp al,2
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jne pci_fn_3
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; PCI function 2: get pci access mechanism
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mov al,[BOOT_VAR+0x9020]
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ret
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pci_fn_3:
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cmp al,4
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jz pci_read_reg ;byte
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cmp al,5
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jz pci_read_reg ;word
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cmp al,6
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jz pci_read_reg ;dword
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cmp al,8
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jz pci_write_reg ;byte
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cmp al,9
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jz pci_write_reg ;word
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cmp al,10
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jz pci_write_reg ;dword
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if defined mmio_pci_addr
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cmp al,11 ; user-level MMIO functions
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jz pci_mmio_init
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cmp al,12
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jz pci_mmio_map
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cmp al,13
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jz pci_mmio_unmap
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end if
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no_pci_access_for_applications:
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or eax,-1
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ret
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;***************************************************************************
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; Function
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; pci_make_config_cmd
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;
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; Description
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; creates a command dword for use with the PCI bus
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; bus # in ah
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; device+func in bh (dddddfff)
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; register in bl
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;
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; command dword returned in eax ( 10000000 bbbbbbbb dddddfff rrrrrr00 )
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;***************************************************************************
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align 4
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pci_make_config_cmd:
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shl eax,8 ; move bus to bits 16-23
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mov ax,bx ; combine all
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and eax,0xffffff
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or eax,0x80000000
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ret
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;***************************************************************************
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; Function
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; pci_read_reg:
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;
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; Description
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; read a register from the PCI config space into EAX/AX/AL
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; IN: ah=bus,device+func=bh,register address=bl
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; number of bytes to read (1,2,4) coded into AL, bits 0-1
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; (0 - byte, 1 - word, 2 - dword)
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;***************************************************************************
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align 4
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pci_read_reg:
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cmp byte [BOOT_VAR+0x9020],2 ;what mechanism will we use?
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je pci_read_reg_2
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; mechanism 1
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push esi ; save register size into ESI
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mov esi,eax
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and esi,3
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call pci_make_config_cmd
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mov ebx,eax
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; get current state
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mov dx,0xcf8
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in eax, dx
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push eax
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; set up addressing to config data
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mov eax,ebx
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and al,0xfc ; make address dword-aligned
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out dx,eax
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; get requested DWORD of config data
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mov dl,0xfc
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and bl,3
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or dl,bl ; add to port address first 2 bits of register address
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or esi,esi
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jz pci_read_byte1
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cmp esi,1
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jz pci_read_word1
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cmp esi,2
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jz pci_read_dword1
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jmp pci_fin_read1
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pci_read_byte1:
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in al,dx
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jmp pci_fin_read1
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pci_read_word1:
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in ax,dx
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jmp pci_fin_read1
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pci_read_dword1:
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in eax,dx
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jmp pci_fin_read1
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pci_fin_read1:
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; restore configuration control
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xchg eax,[esp]
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mov dx,0xcf8
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out dx,eax
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pop eax
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pop esi
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ret
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pci_read_reg_2:
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test bh,128 ;mech#2 only supports 16 devices per bus
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jnz pci_read_reg_err
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push esi ; save register size into ESI
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mov esi,eax
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and esi,3
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push eax
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;store current state of config space
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mov dx,0xcf8
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in al,dx
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mov ah,al
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mov dl,0xfa
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in al,dx
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xchg eax,[esp]
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; out 0xcfa,bus
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mov al,ah
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out dx,al
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; out 0xcf8,0x80
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mov dl,0xf8
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mov al,0x80
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out dx,al
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; compute addr
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shr bh,3 ; func is ignored in mechanism 2
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or bh,0xc0
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mov dx,bx
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or esi,esi
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jz pci_read_byte2
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cmp esi,1
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jz pci_read_word2
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cmp esi,2
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jz pci_read_dword2
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jmp pci_fin_read2
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pci_read_byte2:
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in al,dx
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jmp pci_fin_read2
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pci_read_word2:
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in ax,dx
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jmp pci_fin_read2
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pci_read_dword2:
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in eax,dx
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; jmp pci_fin_read2
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pci_fin_read2:
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; restore configuration space
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xchg eax,[esp]
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mov dx,0xcfa
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out dx,al
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mov dl,0xf8
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mov al,ah
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out dx,al
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pop eax
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pop esi
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ret
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pci_read_reg_err:
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xor eax,eax
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dec eax
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ret
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;***************************************************************************
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; Function
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; pci_write_reg:
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;
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; Description
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; write a register from ECX/CX/CL into the PCI config space
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; IN: ah=bus,device+func=bh,register address (dword aligned)=bl,
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; value to write in ecx
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; number of bytes to write (1,2,4) coded into AL, bits 0-1
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; (0 - byte, 1 - word, 2 - dword)
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;***************************************************************************
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align 4
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pci_write_reg:
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cmp byte [BOOT_VAR+0x9020],2 ;what mechanism will we use?
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je pci_write_reg_2
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; mechanism 1
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push esi ; save register size into ESI
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mov esi,eax
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and esi,3
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call pci_make_config_cmd
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mov ebx,eax
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; get current state into ecx
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mov dx,0xcf8
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in eax, dx
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push eax
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; set up addressing to config data
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mov eax,ebx
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and al,0xfc ; make address dword-aligned
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out dx,eax
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; write DWORD of config data
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mov dl,0xfc
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and bl,3
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or dl,bl
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mov eax,ecx
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or esi,esi
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jz pci_write_byte1
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cmp esi,1
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jz pci_write_word1
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cmp esi,2
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jz pci_write_dword1
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jmp pci_fin_write1
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pci_write_byte1:
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out dx,al
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jmp pci_fin_write1
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pci_write_word1:
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out dx,ax
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jmp pci_fin_write1
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pci_write_dword1:
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out dx,eax
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jmp pci_fin_write1
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pci_fin_write1:
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; restore configuration control
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pop eax
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mov dl,0xf8
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out dx,eax
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xor eax,eax
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pop esi
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ret
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pci_write_reg_2:
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test bh,128 ;mech#2 only supports 16 devices per bus
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jnz pci_write_reg_err
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push esi ; save register size into ESI
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mov esi,eax
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and esi,3
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push eax
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;store current state of config space
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mov dx,0xcf8
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in al,dx
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mov ah,al
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mov dl,0xfa
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in al,dx
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xchg eax,[esp]
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; out 0xcfa,bus
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mov al,ah
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out dx,al
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; out 0xcf8,0x80
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mov dl,0xf8
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mov al,0x80
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out dx,al
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; compute addr
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shr bh,3 ; func is ignored in mechanism 2
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or bh,0xc0
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mov dx,bx
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; write register
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mov eax,ecx
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or esi,esi
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jz pci_write_byte2
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cmp esi,1
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jz pci_write_word2
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cmp esi,2
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jz pci_write_dword2
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jmp pci_fin_write2
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pci_write_byte2:
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out dx,al
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jmp pci_fin_write2
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pci_write_word2:
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out dx,ax
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jmp pci_fin_write2
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pci_write_dword2:
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out dx,eax
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jmp pci_fin_write2
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pci_fin_write2:
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; restore configuration space
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pop eax
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mov dx,0xcfa
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out dx,al
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mov dl,0xf8
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mov al,ah
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out dx,al
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xor eax,eax
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pop esi
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ret
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pci_write_reg_err:
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xor eax,eax
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dec eax
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ret
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if defined mmio_pci_addr ; must be set above
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;***************************************************************************
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; Function
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; pci_mmio_init
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;
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; Description
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; IN: bx = device's PCI bus address (bbbbbbbbdddddfff)
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; Returns eax = user heap space available (bytes)
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; Error codes
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; eax = -1 : PCI user access blocked,
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; eax = -2 : device not registered for uMMIO service
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; eax = -3 : user heap initialization failure
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;***************************************************************************
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pci_mmio_init:
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cmp bx, mmio_pci_addr
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jz @f
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mov eax,-2
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ret
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@@:
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call init_heap ; (if not initialized yet)
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or eax,eax
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jz @f
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ret
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@@:
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mov eax,-3
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ret
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;***************************************************************************
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; Function
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; pci_mmio_map
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;
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; Description
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; maps a block of PCI memory to user-accessible linear address
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;
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; WARNING! This VERY EXPERIMENTAL service is for one chosen PCI device only!
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; The target device address should be set in kernel var mmio_pci_addr
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;
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; IN: ah = BAR#;
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; IN: ebx = block size (bytes);
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; IN: ecx = offset in MMIO block (in 4K-pages, to avoid misaligned pages);
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;
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; Returns eax = MMIO block's linear address in the userspace (if no error)
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;
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;
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; Error codes
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; eax = -1 : user access to PCI blocked,
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; eax = -2 : an invalid BAR register referred
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; eax = -3 : no i/o space on that BAR
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; eax = -4 : a port i/o BAR register referred
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; eax = -5 : dynamic userspace allocation problem
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;***************************************************************************
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pci_mmio_map:
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and edx,0x0ffff
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cmp ah,6
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jc .bar_0_5
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jz .bar_rom
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mov eax,-2
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ret
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.bar_rom:
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mov ah, 8 ; bar6 = Expansion ROM base address
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.bar_0_5:
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push ecx
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add ebx, 4095
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and ebx,-4096
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push ebx
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mov bl, ah ; bl = BAR# (0..5), however bl=8 for BAR6
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shl bl, 1
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shl bl, 1
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add bl, 0x10 ; now bl = BAR offset in PCI config. space
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mov ax, mmio_pci_addr
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mov bh, al ; bh = dddddfff
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mov al, 2 ; al : DW to read
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call pci_read_reg
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or eax, eax
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jnz @f
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mov eax,-3 ; empty I/O space
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jmp mmio_ret_fail
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@@:
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test eax, 1
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jz @f
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mov eax,-4 ; damned ports (not MMIO space)
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jmp mmio_ret_fail
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@@:
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pop ecx ; ecx = block size, bytes (expanded to whole page)
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mov ebx, ecx ; user_alloc destroys eax, ecx, edx, but saves ebx
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push eax ; store MMIO physical address + keep 2DWords in the stack
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stdcall user_alloc, ecx
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or eax, eax
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jnz mmio_map_over
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mov eax,-5 ; problem with page allocation
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mmio_ret_fail:
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pop ecx
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pop edx
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ret
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mmio_map_over:
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mov ecx, ebx ; ecx = size (bytes, expanded to whole page)
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shr ecx, 12 ; ecx = number of pages
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mov ebx, eax ; ebx = linear address
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pop eax ; eax = MMIO start
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pop edx ; edx = MMIO shift (pages)
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shl edx, 12 ; edx = MMIO shift (bytes)
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add eax, edx ; eax = uMMIO physical address
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or eax, PG_SHARED
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or eax, PG_UW
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or eax, PG_NOCACHE
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mov edi, ebx
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call commit_pages
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mov eax, edi
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ret
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;***************************************************************************
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; Function
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; pci_mmio_unmap_page
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;
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; Description
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; unmaps the linear space previously tied to a PCI memory block
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;
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; IN: ebx = linear address of space previously allocated by pci_mmio_map
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; returns eax = 1 if successfully unmapped
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;
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; Error codes
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; eax = -1 if no user PCI access allowed,
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; eax = 0 if unmapping failed
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;***************************************************************************
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pci_mmio_unmap:
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stdcall user_free, ebx
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ret
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end if
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;-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
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uglobal
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align 4
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; VendID (2), DevID (2), Revision = 0 (1), Class Code (3), FNum (1), Bus (1)
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pci_emu_dat: times 30*10 db 0
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endg
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;-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
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align 4
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sys_pcibios:
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cmp [pci_access_enabled], 1
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jne .unsupported_func
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cmp [pci_bios_entry], 0
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jz .emulate_bios
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push ds
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mov ax, pci_data_sel
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mov ds, ax
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mov eax, ebp
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mov ah, 0B1h
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call pword [cs:pci_bios_entry]
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pop ds
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jmp .return
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;-=-=-=-=-=-=-=-=
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.emulate_bios:
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cmp ebp, 1 ; PCI_FUNCTION_ID
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jnz .not_PCI_BIOS_PRESENT
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mov edx, 'PCI '
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mov al, [OS_BASE+0x2F0000 + 0x9020]
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mov bx, [OS_BASE+0x2F0000 + 0x9022]
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mov cl, [OS_BASE+0x2F0000 + 0x9021]
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xor ah, ah
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jmp .return_abcd
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.not_PCI_BIOS_PRESENT:
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cmp ebp, 2 ; FIND_PCI_DEVICE
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jne .not_FIND_PCI_DEVICE
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mov ebx, pci_emu_dat
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..nxt: cmp [ebx], dx
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jne ..no
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cmp [ebx + 2], cx
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jne ..no
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dec si
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jns ..no
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mov bx, [ebx + 4]
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xor ah, ah
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jmp .return_ab
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..no: cmp word[ebx], 0
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je ..dev_not_found
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add ebx, 10
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jmp ..nxt
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..dev_not_found:
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mov ah, 0x86 ; DEVICE_NOT_FOUND
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jmp .return_a
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.not_FIND_PCI_DEVICE:
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cmp ebp, 3 ; FIND_PCI_CLASS_CODE
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jne .not_FIND_PCI_CLASS_CODE
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mov esi, pci_emu_dat
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shl ecx, 8
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..nxt2: cmp [esi], ecx
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jne ..no2
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mov bx, [esi]
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xor ah, ah
|
|
jmp .return_ab
|
|
..no2: cmp dword[esi], 0
|
|
je ..dev_not_found
|
|
add esi, 10
|
|
jmp ..nxt2
|
|
|
|
.not_FIND_PCI_CLASS_CODE:
|
|
cmp ebp, 8 ; READ_CONFIG_*
|
|
jb .not_READ_CONFIG
|
|
cmp ebp, 0x0A
|
|
ja .not_READ_CONFIG
|
|
mov eax, ebp
|
|
mov ah, bh
|
|
mov edx, edi
|
|
mov bh, bl
|
|
mov bl, dl
|
|
call pci_read_reg
|
|
mov ecx, eax
|
|
xor ah, ah ; SUCCESSFUL
|
|
jmp .return_abc
|
|
.not_READ_CONFIG:
|
|
cmp ebp, 0x0B ; WRITE_CONFIG_*
|
|
jb .not_WRITE_CONFIG
|
|
cmp ebp, 0x0D
|
|
ja .not_WRITE_CONFIG
|
|
lea eax, [ebp+1]
|
|
mov ah, bh
|
|
mov edx, edi
|
|
mov bh, bl
|
|
mov bl, dl
|
|
call pci_write_reg
|
|
xor ah, ah ; SUCCESSFUL
|
|
jmp .return_abc
|
|
.not_WRITE_CONFIG:
|
|
.unsupported_func:
|
|
mov ah, 0x81 ; FUNC_NOT_SUPPORTED
|
|
.return:mov dword[esp + 4 ], edi
|
|
mov dword[esp + 8], esi
|
|
.return_abcd:
|
|
mov dword[esp + 24], edx
|
|
.return_abc:
|
|
mov dword[esp + 28], ecx
|
|
.return_ab:
|
|
mov dword[esp + 20], ebx
|
|
.return_a:
|
|
mov dword[esp + 32], eax
|
|
ret
|