605 lines
16 KiB
C
605 lines
16 KiB
C
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#include "types.h"
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#include "link.h"
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#include <stdio.h>
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#include <malloc.h>
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#include <memory.h>
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#include "pci.h"
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#include "agp.h"
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#include "syscall.h"
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agp_t *bridge;
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int __stdcall srv_agp(ioctl_t *io);
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u32_t __stdcall drvEntry(int action)
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{
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u32_t retval;
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int i;
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if(action != 1)
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return 0;
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if(!dbg_open("/rd/1/drivers/agp.log"))
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{
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printf("Can't open /rd/1/drivers/agp.log\nExit\n");
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return 0;
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}
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if( FindPciDevice() == 0)
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{
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dbgprintf("Device not found\n");
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return 0;
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};
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return 0;
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// retval = RegService("AGP", srv_2d);
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// dbgprintf("reg service %s as: %x\n", "HDRAW", retval);
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// return retval;
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};
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#include "pci.inc"
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#include "isoch.inc"
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static void intel_8xx_tlbflush(void *mem)
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{
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u32_t temp;
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temp = pciReadLong(bridge->PciTag, INTEL_AGPCTRL);
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pciWriteLong(bridge->PciTag, INTEL_AGPCTRL, temp & ~(1 << 7));
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temp = pciReadLong(bridge->PciTag, INTEL_AGPCTRL);
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pciWriteLong(bridge->PciTag, INTEL_AGPCTRL, temp | (1 << 7));
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}
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static aper_size_t intel_8xx_sizes[7] =
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{
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{ 256, 65536, 64, 0 },
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{ 128, 32768, 32, 32 },
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{ 64, 16384, 16, 48 },
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{ 32, 8192, 8, 56 },
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{ 16, 4096, 4, 60 },
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{ 8, 2048, 2, 62 },
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{ 4, 1024, 1, 63 }
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};
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static int intel_845_configure()
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{
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u32_t temp;
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u8_t temp2;
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aper_size_t *current_size;
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current_size = bridge->current_size;
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/* aperture size */
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pciWriteByte(bridge->PciTag, INTEL_APSIZE, current_size->size_value);
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dbgprintf("INTEL_APSIZE %d\n", current_size->size_value );
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if (bridge->apbase_config != 0)
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{
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pciWriteLong(bridge->PciTag, AGP_APBASE, bridge->apbase_config);
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}
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else
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{
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/* address to map to */
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temp = pciReadLong(bridge->PciTag, AGP_APBASE);
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bridge->gart_addr = (temp & PCI_MAP_MEMORY_ADDRESS_MASK);
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bridge->apbase_config = temp;
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}
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dbgprintf("AGP_APBASE %x\n", temp );
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/* attbase - aperture base */
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pciWriteLong(bridge->PciTag, INTEL_ATTBASE, bridge->gatt_dma);
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/* agpctrl */
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pciWriteLong(bridge->PciTag, INTEL_AGPCTRL, 0x0000);
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/* agpm */
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temp2 = pciReadByte(bridge->PciTag, INTEL_I845_AGPM);
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pciWriteByte(bridge->PciTag, INTEL_I845_AGPM, temp2 | (1 << 1));
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/* clear any possible error conditions */
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pciWriteWord(bridge->PciTag, INTEL_I845_ERRSTS, 0x001c);
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return 0;
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}
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int agp_generic_create_gatt_table()
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{
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count_t pages;
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pages = bridge->current_size->pages_count;
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if( bridge->gatt_dma = AllocPages(pages))
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{
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if(bridge->gatt_table =
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(u32_t*)MapIoMem((void*)bridge->gatt_dma,
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pages<<12, PG_SW+PG_NOCACHE))
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{
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dbgprintf("gatt map %x at %x %d pages\n",bridge->gatt_dma ,
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bridge->gatt_table, pages);
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/* AK: bogus, should encode addresses > 4GB */
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u32_t volatile *table = bridge->gatt_table;
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count_t count = bridge->current_size->num_entries;
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while(count--) { /* FIXME memset */
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addr_t tmp;
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*table = 0;
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table++;
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}
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return 1;
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};
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};
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dbgprintf("unable to get memory for "
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"graphics translation table.\n");
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return 0;
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}
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static int __intel_8xx_fetch_size(u8_t temp)
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{
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int i;
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aper_size_t *values;
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values = bridge->aperture_sizes;
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values = intel_8xx_sizes;
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for (i = 0; i < 7; i++)
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{
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if (temp == values[i].size_value)
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{
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bridge->previous_size =
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bridge->current_size = (void *) (values + i);
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bridge->aperture_size_idx = i;
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return values[i].size;
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}
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}
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return 0;
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}
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static int intel_8xx_fetch_size(void)
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{
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u8_t temp;
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temp = pciReadByte(bridge->PciTag, INTEL_APSIZE);
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return __intel_8xx_fetch_size(temp);
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}
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int agp_bind_memory(addr_t agp_addr, addr_t dma_addr, size_t size)
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{
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int ret_val;
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count_t count;
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// if (curr == NULL)
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// return -EINVAL;
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// if (curr->is_bound == TRUE) {
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// printk(KERN_INFO PFX "memory %p is already bound!\n", curr);
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// return -EINVAL;
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// }
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// if (curr->is_flushed == FALSE) {
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// curr->bridge->driver->cache_flush();
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// curr->is_flushed = TRUE;
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// }
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// ret_val = curr->bridge->driver->insert_memory(curr, pg_start, curr->type);
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u32_t volatile *table = &bridge->gatt_table[agp_addr>>12];
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count = size >> 12;
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dma_addr |= 0x00000017;
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while(count--)
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{
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*table = dma_addr;
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table++;
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dma_addr+=4096;
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}
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bridge->tlb_flush(NULL);
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// if (ret_val != 0)
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// return ret_val;
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// curr->is_bound = TRUE;
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// curr->pg_start = pg_start;
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return 0;
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}
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void get_agp_version(agp_t *bridge)
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{
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u32_t ncapid;
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/* Exit early if already set by errata workarounds. */
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if (bridge->major_version != 0)
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return;
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ncapid = pciReadLong(bridge->PciTag, bridge->capndx);
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bridge->major_version = (ncapid >> AGP_MAJOR_VERSION_SHIFT) & 0xf;
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bridge->minor_version = (ncapid >> AGP_MINOR_VERSION_SHIFT) & 0xf;
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}
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static void agp_v2_parse_one(u32_t *requested_mode, u32_t *bridge_agpstat, u32_t *vga_agpstat)
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{
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u32_t tmp;
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if (*requested_mode & AGP2_RESERVED_MASK) {
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dbgprintf("reserved bits set (%x) in mode 0x%x. Fixed.\n",
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*requested_mode & AGP2_RESERVED_MASK, *requested_mode);
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*requested_mode &= ~AGP2_RESERVED_MASK;
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}
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/* Check the speed bits make sense. Only one should be set. */
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tmp = *requested_mode & 7;
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switch (tmp) {
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case 0:
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dbgprintf("Setting to x1 mode.\n");
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*requested_mode |= AGPSTAT2_1X;
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break;
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case 1:
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case 2:
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break;
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case 3:
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*requested_mode &= ~(AGPSTAT2_1X); /* rate=2 */
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break;
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case 4:
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break;
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case 5:
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case 6:
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case 7:
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*requested_mode &= ~(AGPSTAT2_1X|AGPSTAT2_2X); /* rate=4*/
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break;
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}
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/* disable SBA if it's not supported */
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if (!((*bridge_agpstat & AGPSTAT_SBA) && (*vga_agpstat & AGPSTAT_SBA) && (*requested_mode & AGPSTAT_SBA)))
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*bridge_agpstat &= ~AGPSTAT_SBA;
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/* Set rate */
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if (!((*bridge_agpstat & AGPSTAT2_4X) && (*vga_agpstat & AGPSTAT2_4X) && (*requested_mode & AGPSTAT2_4X)))
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*bridge_agpstat &= ~AGPSTAT2_4X;
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if (!((*bridge_agpstat & AGPSTAT2_2X) && (*vga_agpstat & AGPSTAT2_2X) && (*requested_mode & AGPSTAT2_2X)))
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*bridge_agpstat &= ~AGPSTAT2_2X;
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if (!((*bridge_agpstat & AGPSTAT2_1X) && (*vga_agpstat & AGPSTAT2_1X) && (*requested_mode & AGPSTAT2_1X)))
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*bridge_agpstat &= ~AGPSTAT2_1X;
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/* Now we know what mode it should be, clear out the unwanted bits. */
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if (*bridge_agpstat & AGPSTAT2_4X)
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*bridge_agpstat &= ~(AGPSTAT2_1X | AGPSTAT2_2X); /* 4X */
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if (*bridge_agpstat & AGPSTAT2_2X)
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*bridge_agpstat &= ~(AGPSTAT2_1X | AGPSTAT2_4X); /* 2X */
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if (*bridge_agpstat & AGPSTAT2_1X)
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*bridge_agpstat &= ~(AGPSTAT2_2X | AGPSTAT2_4X); /* 1X */
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/* Apply any errata. */
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if (bridge->flags & AGP_ERRATA_FASTWRITES)
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*bridge_agpstat &= ~AGPSTAT_FW;
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if (bridge->flags & AGP_ERRATA_SBA)
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*bridge_agpstat &= ~AGPSTAT_SBA;
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if (bridge->flags & AGP_ERRATA_1X) {
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*bridge_agpstat &= ~(AGPSTAT2_2X | AGPSTAT2_4X);
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*bridge_agpstat |= AGPSTAT2_1X;
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}
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/* If we've dropped down to 1X, disable fast writes. */
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if (*bridge_agpstat & AGPSTAT2_1X)
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*bridge_agpstat &= ~AGPSTAT_FW;
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}
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static void agp_v3_parse_one(u32_t *requested_mode,
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u32_t *bridge_agpstat,
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u32_t *vga_agpstat)
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{
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u32_t origbridge = *bridge_agpstat, origvga = *vga_agpstat;
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u32_t tmp;
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if (*requested_mode & AGP3_RESERVED_MASK)
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{
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dbgprintf("reserved bits set (%x) in mode 0x%x. Fixed.\n",
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*requested_mode & AGP3_RESERVED_MASK, *requested_mode);
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*requested_mode &= ~AGP3_RESERVED_MASK;
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}
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/* Check the speed bits make sense. */
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tmp = *requested_mode & 7;
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if (tmp == 0) {
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dbgprintf("Setting to AGP3 x4 mode.\n");
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*requested_mode |= AGPSTAT3_4X;
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}
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if (tmp >= 3) {
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dbgprintf("Setting to AGP3 x8 mode.\n");
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*requested_mode = (*requested_mode & ~7) | AGPSTAT3_8X;
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}
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/* ARQSZ - Set the value to the maximum one.
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* Don't allow the mode register to override values. */
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*bridge_agpstat = ((*bridge_agpstat & ~AGPSTAT_ARQSZ) |
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max_t(u32_t,(*bridge_agpstat & AGPSTAT_ARQSZ),(*vga_agpstat & AGPSTAT_ARQSZ)));
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/* Calibration cycle.
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* Don't allow the mode register to override values. */
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*bridge_agpstat = ((*bridge_agpstat & ~AGPSTAT_CAL_MASK) |
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min_t(u32_t,(*bridge_agpstat & AGPSTAT_CAL_MASK),(*vga_agpstat & AGPSTAT_CAL_MASK)));
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/* SBA *must* be supported for AGP v3 */
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*bridge_agpstat |= AGPSTAT_SBA;
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/*
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* Set speed.
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* Check for invalid speeds. This can happen when applications
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* written before the AGP 3.0 standard pass AGP2.x modes to AGP3 hardware
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*/
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if (*requested_mode & AGPSTAT_MODE_3_0) {
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/*
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* Caller hasn't a clue what it is doing. Bridge is in 3.0 mode,
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* have been passed a 3.0 mode, but with 2.x speed bits set.
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* AGP2.x 4x -> AGP3.0 4x.
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*/
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if (*requested_mode & AGPSTAT2_4X) {
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dbgprintf("broken AGP3 flags (%x). Fixed.\n", *requested_mode);
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*requested_mode &= ~AGPSTAT2_4X;
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*requested_mode |= AGPSTAT3_4X;
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}
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} else {
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/*
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* The caller doesn't know what they are doing. We are in 3.0 mode,
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* but have been passed an AGP 2.x mode.
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* Convert AGP 1x,2x,4x -> AGP 3.0 4x.
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*/
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dbgprintf("broken AGP2 flags (%x) in AGP3 mode. Fixed.\n",*requested_mode);
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*requested_mode &= ~(AGPSTAT2_4X | AGPSTAT2_2X | AGPSTAT2_1X);
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*requested_mode |= AGPSTAT3_4X;
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}
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if (*requested_mode & AGPSTAT3_8X) {
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if (!(*bridge_agpstat & AGPSTAT3_8X)) {
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*bridge_agpstat &= ~(AGPSTAT3_8X | AGPSTAT3_RSVD);
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*bridge_agpstat |= AGPSTAT3_4X;
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dbgprintf("requested AGPx8 but bridge not capable.\n");
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return;
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}
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if (!(*vga_agpstat & AGPSTAT3_8X)) {
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*bridge_agpstat &= ~(AGPSTAT3_8X | AGPSTAT3_RSVD);
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*bridge_agpstat |= AGPSTAT3_4X;
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dbgprintf("requested AGPx8 but graphic card not capable.\n");
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return;
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}
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/* All set, bridge & device can do AGP x8*/
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*bridge_agpstat &= ~(AGPSTAT3_4X | AGPSTAT3_RSVD);
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goto done;
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} else {
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/*
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* If we didn't specify AGPx8, we can only do x4.
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* If the hardware can't do x4, we're up shit creek, and never
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* should have got this far.
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*/
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*bridge_agpstat &= ~(AGPSTAT3_8X | AGPSTAT3_RSVD);
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if ((*bridge_agpstat & AGPSTAT3_4X) && (*vga_agpstat & AGPSTAT3_4X))
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*bridge_agpstat |= AGPSTAT3_4X;
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else {
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dbgprintf("Badness. Don't know which AGP mode to set. "
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"[bridge_agpstat:%x vga_agpstat:%x fell back to:- bridge_agpstat:%x vga_agpstat:%x]\n",
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origbridge, origvga, *bridge_agpstat, *vga_agpstat);
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if (!(*bridge_agpstat & AGPSTAT3_4X))
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dbgprintf("Bridge couldn't do AGP x4.\n");
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if (!(*vga_agpstat & AGPSTAT3_4X))
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dbgprintf("Graphic card couldn't do AGP x4.\n");
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return;
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}
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}
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done:
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/* Apply any errata. */
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if (bridge->flags & AGP_ERRATA_FASTWRITES)
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*bridge_agpstat &= ~AGPSTAT_FW;
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if (bridge->flags & AGP_ERRATA_SBA)
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*bridge_agpstat &= ~AGPSTAT_SBA;
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if (bridge->flags & AGP_ERRATA_1X) {
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*bridge_agpstat &= ~(AGPSTAT2_2X | AGPSTAT2_4X);
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*bridge_agpstat |= AGPSTAT2_1X;
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}
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}
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u32_t agp_collect_device_status(agp_t *bridge, u32_t requested_mode,
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u32_t bridge_agpstat)
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{
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PCITAG vgaTag;
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u32_t vga_agpstat;
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int cap_ptr;
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for (;;)
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{
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vgaTag = pci_find_class(PCI_CLASS_DISPLAY_VGA);
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if (vgaTag == -1)
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{
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dbgprintf("Couldn't find an AGP VGA controller.\n");
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return 0;
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}
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cap_ptr = pci_find_capability(vgaTag, PCI_CAP_ID_AGP);
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if (cap_ptr)
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break;
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}
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/*
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* Ok, here we have a AGP device. Disable impossible
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* settings, and adjust the readqueue to the minimum.
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*/
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vga_agpstat = pciReadLong(vgaTag, cap_ptr+PCI_AGP_STATUS);
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/* adjust RQ depth */
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bridge_agpstat = ((bridge_agpstat & ~AGPSTAT_RQ_DEPTH) |
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min_t(u32_t, (requested_mode & AGPSTAT_RQ_DEPTH),
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min_t(u32_t, (bridge_agpstat & AGPSTAT_RQ_DEPTH), (vga_agpstat & AGPSTAT_RQ_DEPTH))));
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/* disable FW if it's not supported */
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if (!((bridge_agpstat & AGPSTAT_FW) &&
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(vga_agpstat & AGPSTAT_FW) &&
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(requested_mode & AGPSTAT_FW)))
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bridge_agpstat &= ~AGPSTAT_FW;
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/* Check to see if we are operating in 3.0 mode */
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if (bridge->mode & AGPSTAT_MODE_3_0)
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agp_v3_parse_one(&requested_mode, &bridge_agpstat, &vga_agpstat);
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else
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agp_v2_parse_one(&requested_mode, &bridge_agpstat, &vga_agpstat);
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return bridge_agpstat;
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}
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void agp_device_command(u32_t bridge_agpstat, int agp_v3)
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{
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PCITAG device = 0;
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int mode;
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mode = bridge_agpstat & 0x7;
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if (agp_v3)
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mode *= 4;
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for_each_pci_dev(device)
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{
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int agp = pci_find_capability(device, PCI_CAP_ID_AGP);
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if (!agp)
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continue;
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dbgprintf("Putting AGP V%d device at into %dx mode\n",
|
|
agp_v3 ? 3 : 2, mode);
|
|
pciWriteLong(device, agp + PCI_AGP_COMMAND, bridge_agpstat);
|
|
}
|
|
}
|
|
|
|
|
|
|
|
|
|
void agp_generic_enable(u32_t requested_mode)
|
|
{
|
|
u32_t bridge_agpstat, temp;
|
|
|
|
get_agp_version(bridge);
|
|
|
|
dbgprintf("Found an AGP %d.%d compliant device.\n",
|
|
bridge->major_version, bridge->minor_version);
|
|
|
|
bridge_agpstat = pciReadLong(bridge->PciTag,
|
|
bridge->capndx + PCI_AGP_STATUS);
|
|
|
|
bridge_agpstat = agp_collect_device_status(bridge, requested_mode, bridge_agpstat);
|
|
if (bridge_agpstat == 0)
|
|
/* Something bad happened. FIXME: Return error code? */
|
|
return;
|
|
|
|
bridge_agpstat |= AGPSTAT_AGP_ENABLE;
|
|
|
|
/* Do AGP version specific frobbing. */
|
|
if (bridge->major_version >= 3)
|
|
{
|
|
if (bridge->mode & AGPSTAT_MODE_3_0)
|
|
{
|
|
/* If we have 3.5, we can do the isoch stuff. */
|
|
if (bridge->minor_version >= 5)
|
|
agp_3_5_enable(bridge);
|
|
agp_device_command(bridge_agpstat, TRUE);
|
|
return;
|
|
}
|
|
else
|
|
{
|
|
/* Disable calibration cycle in RX91<1> when not in AGP3.0 mode of operation.*/
|
|
bridge_agpstat &= ~(7<<10) ;
|
|
temp = pciReadLong(bridge->PciTag, bridge->capndx+AGPCTRL);
|
|
temp |= (1<<9);
|
|
pciWriteLong(bridge->PciTag, bridge->capndx+AGPCTRL, temp);
|
|
|
|
dbgprintf("Device is in legacy mode,"
|
|
" falling back to 2.x\n");
|
|
}
|
|
}
|
|
|
|
/* AGP v<3 */
|
|
agp_device_command(bridge_agpstat, FALSE);
|
|
}
|
|
|
|
|
|
static agp_t intel_845_driver =
|
|
{
|
|
.aperture_sizes = intel_8xx_sizes,
|
|
// .size_type = U8_APER_SIZE,
|
|
// .num_aperture_sizes = 7,
|
|
.configure = intel_845_configure,
|
|
.fetch_size = intel_8xx_fetch_size,
|
|
// .cleanup = intel_8xx_cleanup,
|
|
.tlb_flush = intel_8xx_tlbflush,
|
|
// .mask_memory = agp_generic_mask_memory,
|
|
// .masks = intel_generic_masks,
|
|
// .agp_enable = agp_generic_enable,
|
|
// .cache_flush = global_cache_flush,
|
|
.create_gatt_table = agp_generic_create_gatt_table,
|
|
// .free_gatt_table = agp_generic_free_gatt_table,
|
|
// .insert_memory = agp_generic_insert_memory,
|
|
// .remove_memory = agp_generic_remove_memory,
|
|
// .alloc_by_type = agp_generic_alloc_by_type,
|
|
// .free_by_type = agp_generic_free_by_type,
|
|
// .agp_alloc_page = agp_generic_alloc_page,
|
|
// .agp_destroy_page = agp_generic_destroy_page,
|
|
};
|
|
|
|
int init_bridge(PCITAG pciTag)
|
|
{
|
|
size_t size_value;
|
|
|
|
bridge = &intel_845_driver;
|
|
|
|
bridge->PciTag = pciTag;
|
|
|
|
bridge->capndx = pci_find_capability(pciTag, PCI_CAP_ID_AGP);
|
|
|
|
size_value = bridge->fetch_size();
|
|
|
|
if (size_value == 0) {
|
|
dbgprintf("unable to determine aperture size.\n");
|
|
return 0;
|
|
};
|
|
|
|
dbgprintf("fetch size = %x\n", size_value);
|
|
|
|
if( bridge->create_gatt_table() )
|
|
{
|
|
bridge->configure();
|
|
return 1;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
|
|
#include "detect.inc"
|