872 lines
24 KiB
C
872 lines
24 KiB
C
/**
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* \file drm.h
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* Header for the Direct Rendering Manager
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*
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* \author Rickard E. (Rik) Faith <faith@valinux.com>
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*
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* \par Acknowledgments:
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* Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg.
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*/
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/*
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* Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
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* Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
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* All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _DRM_H_
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#define _DRM_H_
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#include <stdint.h>
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typedef int8_t __s8;
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typedef uint8_t __u8;
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typedef int16_t __s16;
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typedef uint16_t __u16;
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typedef int32_t __s32;
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typedef uint32_t __u32;
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typedef int64_t __s64;
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typedef uint64_t __u64;
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typedef unsigned long drm_handle_t;
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#define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */
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#define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */
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#define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */
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#define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */
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#define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */
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#define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */
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#define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)
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#define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)
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#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
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typedef unsigned int drm_context_t;
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typedef unsigned int drm_drawable_t;
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typedef unsigned int drm_magic_t;
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/**
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* Cliprect.
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*
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* \warning: If you change this structure, make sure you change
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* XF86DRIClipRectRec in the server as well
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*
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* \note KW: Actually it's illegal to change either for
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* backwards-compatibility reasons.
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*/
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struct drm_clip_rect {
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unsigned short x1;
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unsigned short y1;
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unsigned short x2;
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unsigned short y2;
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};
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/**
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* Drawable information.
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*/
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struct drm_drawable_info {
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unsigned int num_rects;
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struct drm_clip_rect *rects;
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};
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/**
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* Texture region,
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*/
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struct drm_tex_region {
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unsigned char next;
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unsigned char prev;
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unsigned char in_use;
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unsigned char padding;
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unsigned int age;
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};
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/**
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* Hardware lock.
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*
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* The lock structure is a simple cache-line aligned integer. To avoid
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* processor bus contention on a multiprocessor system, there should not be any
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* other data stored in the same cache line.
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*/
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struct drm_hw_lock {
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__volatile__ unsigned int lock; /**< lock variable */
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char padding[60]; /**< Pad to cache line */
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};
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/**
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* DRM_IOCTL_VERSION ioctl argument type.
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*
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* \sa drmGetVersion().
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*/
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struct drm_version {
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int version_major; /**< Major version */
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int version_minor; /**< Minor version */
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int version_patchlevel; /**< Patch level */
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size_t name_len; /**< Length of name buffer */
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char *name; /**< Name of driver */
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size_t date_len; /**< Length of date buffer */
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char *date; /**< User-space buffer to hold date */
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size_t desc_len; /**< Length of desc buffer */
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char *desc; /**< User-space buffer to hold desc */
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};
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/**
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* DRM_IOCTL_GET_UNIQUE ioctl argument type.
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*
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* \sa drmGetBusid() and drmSetBusId().
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*/
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struct drm_unique {
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size_t unique_len; /**< Length of unique */
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char *unique; /**< Unique name for driver instantiation */
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};
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struct drm_list {
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int count; /**< Length of user-space structures */
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struct drm_version *version;
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};
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struct drm_block {
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int unused;
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};
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/**
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* DRM_IOCTL_CONTROL ioctl argument type.
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*
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* \sa drmCtlInstHandler() and drmCtlUninstHandler().
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*/
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struct drm_control {
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enum {
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DRM_ADD_COMMAND,
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DRM_RM_COMMAND,
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DRM_INST_HANDLER,
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DRM_UNINST_HANDLER
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} func;
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int irq;
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};
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/**
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* Type of memory to map.
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*/
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enum drm_map_type {
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_DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */
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_DRM_REGISTERS = 1, /**< no caching, no core dump */
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_DRM_SHM = 2, /**< shared, cached */
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_DRM_AGP = 3, /**< AGP/GART */
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_DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */
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_DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */
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_DRM_GEM = 6 /**< GEM object */
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};
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/**
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* Memory mapping flags.
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*/
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enum drm_map_flags {
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_DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */
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_DRM_READ_ONLY = 0x02,
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_DRM_LOCKED = 0x04, /**< shared, cached, locked */
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_DRM_KERNEL = 0x08, /**< kernel requires access */
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_DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */
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_DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */
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_DRM_REMOVABLE = 0x40, /**< Removable mapping */
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_DRM_DRIVER = 0x80 /**< Managed by driver */
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};
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struct drm_ctx_priv_map {
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unsigned int ctx_id; /**< Context requesting private mapping */
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void *handle; /**< Handle of map */
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};
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/**
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* DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
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* argument type.
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*
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* \sa drmAddMap().
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*/
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struct drm_map {
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unsigned long offset; /**< Requested physical address (0 for SAREA)*/
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unsigned long size; /**< Requested physical size (bytes) */
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enum drm_map_type type; /**< Type of memory to map */
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enum drm_map_flags flags; /**< Flags */
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void *handle; /**< User-space: "Handle" to pass to mmap() */
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/**< Kernel-space: kernel-virtual address */
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int mtrr; /**< MTRR slot used */
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/* Private data */
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};
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/**
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* DRM_IOCTL_GET_CLIENT ioctl argument type.
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*/
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struct drm_client {
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int idx; /**< Which client desired? */
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int auth; /**< Is client authenticated? */
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unsigned long pid; /**< Process ID */
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unsigned long uid; /**< User ID */
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unsigned long magic; /**< Magic */
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unsigned long iocs; /**< Ioctl count */
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};
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enum drm_stat_type {
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_DRM_STAT_LOCK,
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_DRM_STAT_OPENS,
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_DRM_STAT_CLOSES,
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_DRM_STAT_IOCTLS,
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_DRM_STAT_LOCKS,
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_DRM_STAT_UNLOCKS,
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_DRM_STAT_VALUE, /**< Generic value */
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_DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */
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_DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */
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_DRM_STAT_IRQ, /**< IRQ */
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_DRM_STAT_PRIMARY, /**< Primary DMA bytes */
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_DRM_STAT_SECONDARY, /**< Secondary DMA bytes */
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_DRM_STAT_DMA, /**< DMA */
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_DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */
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_DRM_STAT_MISSED /**< Missed DMA opportunity */
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/* Add to the *END* of the list */
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};
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/**
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* DRM_IOCTL_GET_STATS ioctl argument type.
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*/
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struct drm_stats {
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unsigned long count;
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struct {
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unsigned long value;
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enum drm_stat_type type;
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} data[15];
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};
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/**
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* Hardware locking flags.
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*/
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enum drm_lock_flags {
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_DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */
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_DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */
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_DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */
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_DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */
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/* These *HALT* flags aren't supported yet
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-- they will be used to support the
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full-screen DGA-like mode. */
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_DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */
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_DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */
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};
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/**
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* DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
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*
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* \sa drmGetLock() and drmUnlock().
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*/
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struct drm_lock {
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int context;
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enum drm_lock_flags flags;
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};
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/**
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* DMA flags
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*
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* \warning
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* These values \e must match xf86drm.h.
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*
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* \sa drm_dma.
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*/
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enum drm_dma_flags {
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/* Flags for DMA buffer dispatch */
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_DRM_DMA_BLOCK = 0x01, /**<
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* Block until buffer dispatched.
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*
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* \note The buffer may not yet have
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* been processed by the hardware --
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* getting a hardware lock with the
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* hardware quiescent will ensure
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* that the buffer has been
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* processed.
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*/
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_DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */
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_DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */
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/* Flags for DMA buffer request */
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_DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */
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_DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */
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_DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */
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};
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/**
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* DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
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*
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* \sa drmAddBufs().
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*/
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struct drm_buf_desc {
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int count; /**< Number of buffers of this size */
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int size; /**< Size in bytes */
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int low_mark; /**< Low water mark */
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int high_mark; /**< High water mark */
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enum {
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_DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */
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_DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */
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_DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */
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_DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */
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_DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */
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} flags;
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unsigned long agp_start; /**<
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* Start address of where the AGP buffers are
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* in the AGP aperture
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*/
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};
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/**
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* DRM_IOCTL_INFO_BUFS ioctl argument type.
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*/
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struct drm_buf_info {
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int count; /**< Entries in list */
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struct drm_buf_desc *list;
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};
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/**
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* DRM_IOCTL_FREE_BUFS ioctl argument type.
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*/
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struct drm_buf_free {
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int count;
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int *list;
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};
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/**
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* Buffer information
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*
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* \sa drm_buf_map.
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*/
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struct drm_buf_pub {
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int idx; /**< Index into the master buffer list */
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int total; /**< Buffer size */
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int used; /**< Amount of buffer in use (for DMA) */
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void *address; /**< Address of buffer */
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};
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/**
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* DRM_IOCTL_MAP_BUFS ioctl argument type.
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*/
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struct drm_buf_map {
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int count; /**< Length of the buffer list */
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#ifdef __cplusplus
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void *virt;
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#else
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void *virtual; /**< Mmap'd area in user-virtual */
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#endif
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struct drm_buf_pub *list; /**< Buffer information */
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};
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/**
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* DRM_IOCTL_DMA ioctl argument type.
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*
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* Indices here refer to the offset into the buffer list in drm_buf_get.
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*
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* \sa drmDMA().
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*/
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struct drm_dma {
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int context; /**< Context handle */
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int send_count; /**< Number of buffers to send */
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int *send_indices; /**< List of handles to buffers */
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int *send_sizes; /**< Lengths of data to send */
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enum drm_dma_flags flags; /**< Flags */
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int request_count; /**< Number of buffers requested */
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int request_size; /**< Desired size for buffers */
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int *request_indices; /**< Buffer information */
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int *request_sizes;
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int granted_count; /**< Number of buffers granted */
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};
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enum drm_ctx_flags {
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_DRM_CONTEXT_PRESERVED = 0x01,
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_DRM_CONTEXT_2DONLY = 0x02
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};
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/**
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* DRM_IOCTL_ADD_CTX ioctl argument type.
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*
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* \sa drmCreateContext() and drmDestroyContext().
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*/
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struct drm_ctx {
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drm_context_t handle;
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enum drm_ctx_flags flags;
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};
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/**
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* DRM_IOCTL_RES_CTX ioctl argument type.
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*/
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struct drm_ctx_res {
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int count;
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struct drm_ctx *contexts;
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};
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/**
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* DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
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*/
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struct drm_draw {
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drm_drawable_t handle;
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};
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/**
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* DRM_IOCTL_UPDATE_DRAW ioctl argument type.
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*/
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typedef enum {
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DRM_DRAWABLE_CLIPRECTS
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} drm_drawable_info_type_t;
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struct drm_update_draw {
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drm_drawable_t handle;
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unsigned int type;
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unsigned int num;
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unsigned long long data;
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};
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/**
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* DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
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*/
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struct drm_auth {
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drm_magic_t magic;
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};
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/**
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* DRM_IOCTL_IRQ_BUSID ioctl argument type.
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*
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* \sa drmGetInterruptFromBusID().
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*/
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struct drm_irq_busid {
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int irq; /**< IRQ number */
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int busnum; /**< bus number */
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int devnum; /**< device number */
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int funcnum; /**< function number */
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};
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enum drm_vblank_seq_type {
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_DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */
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_DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */
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_DRM_VBLANK_EVENT = 0x4000000, /**< Send event instead of blocking */
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_DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */
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_DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */
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_DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */
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_DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking, unsupported */
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};
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#define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE)
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#define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | \
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_DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS)
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struct drm_wait_vblank_request {
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enum drm_vblank_seq_type type;
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unsigned int sequence;
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unsigned long signal;
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};
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struct drm_wait_vblank_reply {
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enum drm_vblank_seq_type type;
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unsigned int sequence;
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long tval_sec;
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long tval_usec;
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};
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/**
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* DRM_IOCTL_WAIT_VBLANK ioctl argument type.
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*
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* \sa drmWaitVBlank().
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*/
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union drm_wait_vblank {
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struct drm_wait_vblank_request request;
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struct drm_wait_vblank_reply reply;
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};
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#define _DRM_PRE_MODESET 1
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#define _DRM_POST_MODESET 2
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/**
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* DRM_IOCTL_MODESET_CTL ioctl argument type
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*
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* \sa drmModesetCtl().
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*/
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struct drm_modeset_ctl {
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__u32 crtc;
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__u32 cmd;
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};
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/**
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* DRM_IOCTL_AGP_ENABLE ioctl argument type.
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*
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* \sa drmAgpEnable().
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*/
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struct drm_agp_mode {
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unsigned long mode; /**< AGP mode */
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};
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/**
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* DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
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*
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* \sa drmAgpAlloc() and drmAgpFree().
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*/
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struct drm_agp_buffer {
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unsigned long size; /**< In bytes -- will round to page boundary */
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unsigned long handle; /**< Used for binding / unbinding */
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unsigned long type; /**< Type of memory to allocate */
|
|
unsigned long physical; /**< Physical used by i810 */
|
|
};
|
|
|
|
/**
|
|
* DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
|
|
*
|
|
* \sa drmAgpBind() and drmAgpUnbind().
|
|
*/
|
|
struct drm_agp_binding {
|
|
unsigned long handle; /**< From drm_agp_buffer */
|
|
unsigned long offset; /**< In bytes -- will round to page boundary */
|
|
};
|
|
|
|
/**
|
|
* DRM_IOCTL_AGP_INFO ioctl argument type.
|
|
*
|
|
* \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),
|
|
* drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),
|
|
* drmAgpVendorId() and drmAgpDeviceId().
|
|
*/
|
|
struct drm_agp_info {
|
|
int agp_version_major;
|
|
int agp_version_minor;
|
|
unsigned long mode;
|
|
unsigned long aperture_base; /* physical address */
|
|
unsigned long aperture_size; /* bytes */
|
|
unsigned long memory_allowed; /* bytes */
|
|
unsigned long memory_used;
|
|
|
|
/* PCI information */
|
|
unsigned short id_vendor;
|
|
unsigned short id_device;
|
|
};
|
|
|
|
/**
|
|
* DRM_IOCTL_SG_ALLOC ioctl argument type.
|
|
*/
|
|
struct drm_scatter_gather {
|
|
unsigned long size; /**< In bytes -- will round to page boundary */
|
|
unsigned long handle; /**< Used for mapping / unmapping */
|
|
};
|
|
|
|
/**
|
|
* DRM_IOCTL_SET_VERSION ioctl argument type.
|
|
*/
|
|
struct drm_set_version {
|
|
int drm_di_major;
|
|
int drm_di_minor;
|
|
int drm_dd_major;
|
|
int drm_dd_minor;
|
|
};
|
|
|
|
/** DRM_IOCTL_GEM_CLOSE ioctl argument type */
|
|
struct drm_gem_close {
|
|
/** Handle of the object to be closed. */
|
|
__u32 handle;
|
|
__u32 pad;
|
|
};
|
|
|
|
/** DRM_IOCTL_GEM_FLINK ioctl argument type */
|
|
struct drm_gem_flink {
|
|
/** Handle for the object being named */
|
|
__u32 handle;
|
|
|
|
/** Returned global name */
|
|
__u32 name;
|
|
};
|
|
|
|
/** DRM_IOCTL_GEM_OPEN ioctl argument type */
|
|
struct drm_gem_open {
|
|
/** Name of object being opened */
|
|
__u32 name;
|
|
|
|
/** Returned handle for the object */
|
|
__u32 handle;
|
|
|
|
/** Returned size of the object */
|
|
__u64 size;
|
|
};
|
|
|
|
/** DRM_IOCTL_GET_CAP ioctl argument type */
|
|
struct drm_get_cap {
|
|
__u64 capability;
|
|
__u64 value;
|
|
};
|
|
|
|
/**
|
|
* DRM_CLIENT_CAP_STEREO_3D
|
|
*
|
|
* if set to 1, the DRM core will expose the stereo 3D capabilities of the
|
|
* monitor by advertising the supported 3D layouts in the flags of struct
|
|
* drm_mode_modeinfo.
|
|
*/
|
|
#define DRM_CLIENT_CAP_STEREO_3D 1
|
|
|
|
/** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */
|
|
struct drm_set_client_cap {
|
|
__u64 capability;
|
|
__u64 value;
|
|
};
|
|
|
|
#define DRM_CLOEXEC O_CLOEXEC
|
|
struct drm_prime_handle {
|
|
__u32 handle;
|
|
|
|
/** Flags.. only applicable for handle->fd */
|
|
__u32 flags;
|
|
|
|
/** Returned dmabuf file descriptor */
|
|
__s32 fd;
|
|
};
|
|
|
|
#define SRV_GET_PCI_INFO 20
|
|
#define SRV_I915_GET_PARAM 21
|
|
#define SRV_I915_GEM_CREATE 22
|
|
#define SRV_DRM_GEM_CLOSE 23
|
|
#define SRV_DRM_GEM_FLINK 24
|
|
#define SRV_DRM_GEM_OPEN 25
|
|
#define SRV_I915_GEM_PIN 26
|
|
#define SRV_I915_GEM_UNPIN 27
|
|
#define SRV_I915_GEM_SET_CACHING 28
|
|
#define SRV_I915_GEM_PWRITE 29
|
|
#define SRV_I915_GEM_BUSY 30
|
|
#define SRV_I915_GEM_SET_DOMAIN 31
|
|
#define SRV_I915_GEM_MMAP 32
|
|
#define SRV_I915_GEM_SET_TILING 33
|
|
#define SRV_I915_GEM_GET_TILING 34
|
|
#define SRV_I915_GEM_GET_APERTURE 35
|
|
#define SRV_I915_GEM_MMAP_GTT 36
|
|
#define SRV_I915_GEM_THROTTLE 37
|
|
#define SRV_I915_GEM_EXECBUFFER2 38
|
|
#define SRV_I915_GEM_WAIT 39
|
|
#define SRV_I915_GEM_CONTEXT_CREATE 40
|
|
#define SRV_I915_GEM_CONTEXT_DESTROY 41
|
|
#define SRV_I915_REG_READ 42
|
|
|
|
#define SRV_FBINFO 43
|
|
#define SRV_MASK_UPDATE 44
|
|
|
|
|
|
|
|
#include "drm_mode.h"
|
|
|
|
#define DRM_IOCTL_BASE 'd'
|
|
#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
|
|
#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)
|
|
#define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)
|
|
#define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)
|
|
|
|
#define DRM_IOCTL_VERSION
|
|
#define DRM_IOCTL_GET_UNIQUE
|
|
#define DRM_IOCTL_GET_MAGIC
|
|
#define DRM_IOCTL_IRQ_BUSID
|
|
#define DRM_IOCTL_GET_MAP
|
|
#define DRM_IOCTL_GET_CLIENT
|
|
#define DRM_IOCTL_GET_STATS
|
|
#define DRM_IOCTL_SET_VERSION
|
|
#define DRM_IOCTL_MODESET_CTL
|
|
#define DRM_IOCTL_GEM_CLOSE SRV_DRM_GEM_CLOSE
|
|
#define DRM_IOCTL_GEM_FLINK SRV_DRM_GEM_FLINK
|
|
#define DRM_IOCTL_GEM_OPEN SRV_DRM_GEM_OPEN
|
|
#define DRM_IOCTL_GET_CAP
|
|
#define DRM_IOCTL_SET_CLIENT_CAP
|
|
|
|
#define DRM_IOCTL_SET_UNIQUE
|
|
#define DRM_IOCTL_AUTH_MAGIC
|
|
#define DRM_IOCTL_BLOCK
|
|
#define DRM_IOCTL_UNBLOCK
|
|
#define DRM_IOCTL_CONTROL
|
|
#define DRM_IOCTL_ADD_MAP
|
|
#define DRM_IOCTL_ADD_BUFS
|
|
#define DRM_IOCTL_MARK_BUFS
|
|
#define DRM_IOCTL_INFO_BUFS
|
|
#define DRM_IOCTL_MAP_BUFS
|
|
#define DRM_IOCTL_FREE_BUFS
|
|
|
|
#define DRM_IOCTL_RM_MAP
|
|
|
|
#define DRM_IOCTL_SET_SAREA_CTX
|
|
#define DRM_IOCTL_GET_SAREA_CTX
|
|
|
|
#define DRM_IOCTL_SET_MASTER
|
|
#define DRM_IOCTL_DROP_MASTER
|
|
|
|
#define DRM_IOCTL_ADD_CTX
|
|
#define DRM_IOCTL_RM_CTX
|
|
#define DRM_IOCTL_MOD_CTX
|
|
#define DRM_IOCTL_GET_CTX
|
|
#define DRM_IOCTL_SWITCH_CTX
|
|
#define DRM_IOCTL_NEW_CTX
|
|
#define DRM_IOCTL_RES_CTX
|
|
#define DRM_IOCTL_ADD_DRAW
|
|
#define DRM_IOCTL_RM_DRAW
|
|
#define DRM_IOCTL_DMA
|
|
#define DRM_IOCTL_LOCK
|
|
#define DRM_IOCTL_UNLOCK
|
|
#define DRM_IOCTL_FINISH
|
|
|
|
#define DRM_IOCTL_PRIME_HANDLE_TO_FD
|
|
#define DRM_IOCTL_PRIME_FD_TO_HANDLE
|
|
|
|
#define DRM_IOCTL_AGP_ACQUIRE
|
|
#define DRM_IOCTL_AGP_RELEASE
|
|
#define DRM_IOCTL_AGP_ENABLE
|
|
#define DRM_IOCTL_AGP_INFO
|
|
#define DRM_IOCTL_AGP_ALLOC
|
|
#define DRM_IOCTL_AGP_FREE
|
|
#define DRM_IOCTL_AGP_BIND
|
|
#define DRM_IOCTL_AGP_UNBIND
|
|
|
|
#define DRM_IOCTL_SG_ALLOC
|
|
#define DRM_IOCTL_SG_FREE
|
|
|
|
#define DRM_IOCTL_WAIT_VBLANK
|
|
|
|
#define DRM_IOCTL_UPDATE_DRAW
|
|
|
|
#define DRM_IOCTL_MODE_GETRESOURCES
|
|
#define DRM_IOCTL_MODE_GETCRTC
|
|
#define DRM_IOCTL_MODE_SETCRTC
|
|
#define DRM_IOCTL_MODE_CURSOR
|
|
#define DRM_IOCTL_MODE_GETGAMMA
|
|
#define DRM_IOCTL_MODE_SETGAMMA
|
|
#define DRM_IOCTL_MODE_GETENCODER
|
|
#define DRM_IOCTL_MODE_GETCONNECTOR
|
|
#define DRM_IOCTL_MODE_ATTACHMODE
|
|
#define DRM_IOCTL_MODE_DETACHMODE
|
|
|
|
#define DRM_IOCTL_MODE_GETPROPERTY
|
|
#define DRM_IOCTL_MODE_SETPROPERTY
|
|
#define DRM_IOCTL_MODE_GETPROPBLOB
|
|
#define DRM_IOCTL_MODE_GETFB
|
|
#define DRM_IOCTL_MODE_ADDFB
|
|
#define DRM_IOCTL_MODE_RMFB
|
|
#define DRM_IOCTL_MODE_PAGE_FLIP
|
|
#define DRM_IOCTL_MODE_DIRTYFB
|
|
|
|
#define DRM_IOCTL_MODE_CREATE_DUMB
|
|
#define DRM_IOCTL_MODE_MAP_DUMB
|
|
#define DRM_IOCTL_MODE_DESTROY_DUMB
|
|
#define DRM_IOCTL_MODE_GETPLANERESOURCES
|
|
#define DRM_IOCTL_MODE_GETPLANE
|
|
#define DRM_IOCTL_MODE_SETPLANE
|
|
#define DRM_IOCTL_MODE_ADDFB2
|
|
#define DRM_IOCTL_MODE_OBJ_GETPROPERTIES
|
|
#define DRM_IOCTL_MODE_OBJ_SETPROPERTY
|
|
#define DRM_IOCTL_MODE_CURSOR2
|
|
|
|
/**
|
|
* Device specific ioctls should only be in their respective headers
|
|
* The device specific ioctl range is from 0x40 to 0x99.
|
|
* Generic IOCTLS restart at 0xA0.
|
|
*
|
|
* \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
|
|
* drmCommandReadWrite().
|
|
*/
|
|
#define DRM_COMMAND_BASE 0x40
|
|
#define DRM_COMMAND_END 0xA0
|
|
|
|
/**
|
|
* Header for events written back to userspace on the drm fd. The
|
|
* type defines the type of event, the length specifies the total
|
|
* length of the event (including the header), and user_data is
|
|
* typically a 64 bit value passed with the ioctl that triggered the
|
|
* event. A read on the drm fd will always only return complete
|
|
* events, that is, if for example the read buffer is 100 bytes, and
|
|
* there are two 64 byte events pending, only one will be returned.
|
|
*
|
|
* Event types 0 - 0x7fffffff are generic drm events, 0x80000000 and
|
|
* up are chipset specific.
|
|
*/
|
|
struct drm_event {
|
|
__u32 type;
|
|
__u32 length;
|
|
};
|
|
|
|
#define DRM_EVENT_VBLANK 0x01
|
|
#define DRM_EVENT_FLIP_COMPLETE 0x02
|
|
|
|
struct drm_event_vblank {
|
|
struct drm_event base;
|
|
__u64 user_data;
|
|
__u32 tv_sec;
|
|
__u32 tv_usec;
|
|
__u32 sequence;
|
|
__u32 reserved;
|
|
};
|
|
|
|
#define DRM_CAP_DUMB_BUFFER 0x1
|
|
#define DRM_CAP_VBLANK_HIGH_CRTC 0x2
|
|
#define DRM_CAP_DUMB_PREFERRED_DEPTH 0x3
|
|
#define DRM_CAP_DUMB_PREFER_SHADOW 0x4
|
|
#define DRM_CAP_PRIME 0x5
|
|
#define DRM_CAP_TIMESTAMP_MONOTONIC 0x6
|
|
#define DRM_CAP_ASYNC_PAGE_FLIP 0x7
|
|
|
|
#define DRM_PRIME_CAP_IMPORT 0x1
|
|
#define DRM_PRIME_CAP_EXPORT 0x2
|
|
|
|
/* typedef area */
|
|
typedef struct drm_clip_rect drm_clip_rect_t;
|
|
typedef struct drm_drawable_info drm_drawable_info_t;
|
|
typedef struct drm_tex_region drm_tex_region_t;
|
|
typedef struct drm_hw_lock drm_hw_lock_t;
|
|
typedef struct drm_version drm_version_t;
|
|
typedef struct drm_unique drm_unique_t;
|
|
typedef struct drm_list drm_list_t;
|
|
typedef struct drm_block drm_block_t;
|
|
typedef struct drm_control drm_control_t;
|
|
typedef enum drm_map_type drm_map_type_t;
|
|
typedef enum drm_map_flags drm_map_flags_t;
|
|
typedef struct drm_ctx_priv_map drm_ctx_priv_map_t;
|
|
typedef struct drm_map drm_map_t;
|
|
typedef struct drm_client drm_client_t;
|
|
typedef enum drm_stat_type drm_stat_type_t;
|
|
typedef struct drm_stats drm_stats_t;
|
|
typedef enum drm_lock_flags drm_lock_flags_t;
|
|
typedef struct drm_lock drm_lock_t;
|
|
typedef enum drm_dma_flags drm_dma_flags_t;
|
|
typedef struct drm_buf_desc drm_buf_desc_t;
|
|
typedef struct drm_buf_info drm_buf_info_t;
|
|
typedef struct drm_buf_free drm_buf_free_t;
|
|
typedef struct drm_buf_pub drm_buf_pub_t;
|
|
typedef struct drm_buf_map drm_buf_map_t;
|
|
typedef struct drm_dma drm_dma_t;
|
|
typedef union drm_wait_vblank drm_wait_vblank_t;
|
|
typedef struct drm_agp_mode drm_agp_mode_t;
|
|
typedef enum drm_ctx_flags drm_ctx_flags_t;
|
|
typedef struct drm_ctx drm_ctx_t;
|
|
typedef struct drm_ctx_res drm_ctx_res_t;
|
|
typedef struct drm_draw drm_draw_t;
|
|
typedef struct drm_update_draw drm_update_draw_t;
|
|
typedef struct drm_auth drm_auth_t;
|
|
typedef struct drm_irq_busid drm_irq_busid_t;
|
|
typedef enum drm_vblank_seq_type drm_vblank_seq_type_t;
|
|
|
|
typedef struct drm_agp_buffer drm_agp_buffer_t;
|
|
typedef struct drm_agp_binding drm_agp_binding_t;
|
|
typedef struct drm_agp_info drm_agp_info_t;
|
|
typedef struct drm_scatter_gather drm_scatter_gather_t;
|
|
typedef struct drm_set_version drm_set_version_t;
|
|
|
|
int drmIoctl(int fd, unsigned long request, void *arg);
|
|
|
|
#endif
|