251 lines
6.5 KiB
C
251 lines
6.5 KiB
C
/*
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* Copyright 2012 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __NI_DPM_H__
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#define __NI_DPM_H__
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#include "cypress_dpm.h"
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#include "btc_dpm.h"
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#include "nislands_smc.h"
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struct ni_clock_registers {
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u32 cg_spll_func_cntl;
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u32 cg_spll_func_cntl_2;
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u32 cg_spll_func_cntl_3;
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u32 cg_spll_func_cntl_4;
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u32 cg_spll_spread_spectrum;
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u32 cg_spll_spread_spectrum_2;
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u32 mclk_pwrmgt_cntl;
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u32 dll_cntl;
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u32 mpll_ad_func_cntl;
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u32 mpll_ad_func_cntl_2;
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u32 mpll_dq_func_cntl;
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u32 mpll_dq_func_cntl_2;
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u32 mpll_ss1;
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u32 mpll_ss2;
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};
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struct ni_mc_reg_entry {
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u32 mclk_max;
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u32 mc_data[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE];
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};
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struct ni_mc_reg_table {
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u8 last;
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u8 num_entries;
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u16 valid_flag;
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struct ni_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];
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SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE];
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};
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#define NISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT 2
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enum ni_dc_cac_level
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{
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NISLANDS_DCCAC_LEVEL_0 = 0,
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NISLANDS_DCCAC_LEVEL_1,
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NISLANDS_DCCAC_LEVEL_2,
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NISLANDS_DCCAC_LEVEL_3,
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NISLANDS_DCCAC_LEVEL_4,
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NISLANDS_DCCAC_LEVEL_5,
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NISLANDS_DCCAC_LEVEL_6,
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NISLANDS_DCCAC_LEVEL_7,
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NISLANDS_DCCAC_MAX_LEVELS
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};
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struct ni_leakage_coeffients
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{
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u32 at;
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u32 bt;
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u32 av;
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u32 bv;
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s32 t_slope;
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s32 t_intercept;
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u32 t_ref;
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};
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struct ni_cac_data
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{
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struct ni_leakage_coeffients leakage_coefficients;
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u32 i_leakage;
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s32 leakage_minimum_temperature;
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u32 pwr_const;
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u32 dc_cac_value;
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u32 bif_cac_value;
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u32 lkge_pwr;
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u8 mc_wr_weight;
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u8 mc_rd_weight;
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u8 allow_ovrflw;
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u8 num_win_tdp;
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u8 l2num_win_tdp;
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u8 lts_truncate_n;
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};
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struct ni_cac_weights
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{
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u32 weight_tcp_sig0;
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u32 weight_tcp_sig1;
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u32 weight_ta_sig;
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u32 weight_tcc_en0;
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u32 weight_tcc_en1;
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u32 weight_tcc_en2;
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u32 weight_cb_en0;
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u32 weight_cb_en1;
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u32 weight_cb_en2;
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u32 weight_cb_en3;
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u32 weight_db_sig0;
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u32 weight_db_sig1;
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u32 weight_db_sig2;
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u32 weight_db_sig3;
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u32 weight_sxm_sig0;
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u32 weight_sxm_sig1;
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u32 weight_sxm_sig2;
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u32 weight_sxs_sig0;
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u32 weight_sxs_sig1;
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u32 weight_xbr_0;
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u32 weight_xbr_1;
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u32 weight_xbr_2;
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u32 weight_spi_sig0;
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u32 weight_spi_sig1;
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u32 weight_spi_sig2;
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u32 weight_spi_sig3;
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u32 weight_spi_sig4;
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u32 weight_spi_sig5;
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u32 weight_lds_sig0;
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u32 weight_lds_sig1;
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u32 weight_sc;
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u32 weight_bif;
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u32 weight_cp;
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u32 weight_pa_sig0;
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u32 weight_pa_sig1;
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u32 weight_vgt_sig0;
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u32 weight_vgt_sig1;
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u32 weight_vgt_sig2;
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u32 weight_dc_sig0;
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u32 weight_dc_sig1;
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u32 weight_dc_sig2;
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u32 weight_dc_sig3;
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u32 weight_uvd_sig0;
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u32 weight_uvd_sig1;
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u32 weight_spare0;
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u32 weight_spare1;
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u32 weight_sq_vsp;
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u32 weight_sq_vsp0;
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u32 weight_sq_gpr;
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u32 ovr_mode_spare_0;
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u32 ovr_val_spare_0;
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u32 ovr_mode_spare_1;
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u32 ovr_val_spare_1;
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u32 vsp;
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u32 vsp0;
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u32 gpr;
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u8 mc_read_weight;
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u8 mc_write_weight;
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u32 tid_cnt;
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u32 tid_unit;
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u32 l2_lta_window_size;
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u32 lts_truncate;
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u32 dc_cac[NISLANDS_DCCAC_MAX_LEVELS];
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u32 pcie_cac[SMC_NISLANDS_BIF_LUT_NUM_OF_ENTRIES];
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bool enable_power_containment_by_default;
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};
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struct ni_ps {
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u16 performance_level_count;
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bool dc_compatible;
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struct rv7xx_pl performance_levels[NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE];
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};
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struct ni_power_info {
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/* must be first! */
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struct evergreen_power_info eg;
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struct ni_clock_registers clock_registers;
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struct ni_mc_reg_table mc_reg_table;
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u32 mclk_rtt_mode_threshold;
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/* flags */
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bool use_power_boost_limit;
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bool support_cac_long_term_average;
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bool cac_enabled;
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bool cac_configuration_required;
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bool driver_calculate_cac_leakage;
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bool pc_enabled;
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bool enable_power_containment;
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bool enable_cac;
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bool enable_sq_ramping;
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/* smc offsets */
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u16 arb_table_start;
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u16 fan_table_start;
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u16 cac_table_start;
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u16 spll_table_start;
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/* CAC stuff */
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struct ni_cac_data cac_data;
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u32 dc_cac_table[NISLANDS_DCCAC_MAX_LEVELS];
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const struct ni_cac_weights *cac_weights;
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u8 lta_window_size;
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u8 lts_truncate;
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struct ni_ps current_ps;
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struct ni_ps requested_ps;
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/* scratch structs */
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SMC_NIslands_MCRegisters smc_mc_reg_table;
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NISLANDS_SMC_STATETABLE smc_statetable;
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};
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#define NISLANDS_INITIAL_STATE_ARB_INDEX 0
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#define NISLANDS_ACPI_STATE_ARB_INDEX 1
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#define NISLANDS_ULV_STATE_ARB_INDEX 2
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#define NISLANDS_DRIVER_STATE_ARB_INDEX 3
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#define NISLANDS_DPM2_MAX_PULSE_SKIP 256
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#define NISLANDS_DPM2_NEAR_TDP_DEC 10
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#define NISLANDS_DPM2_ABOVE_SAFE_INC 5
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#define NISLANDS_DPM2_BELOW_SAFE_INC 20
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#define NISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT 80
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#define NISLANDS_DPM2_MAXPS_PERCENT_H 90
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#define NISLANDS_DPM2_MAXPS_PERCENT_M 0
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#define NISLANDS_DPM2_SQ_RAMP_MAX_POWER 0x3FFF
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#define NISLANDS_DPM2_SQ_RAMP_MIN_POWER 0x12
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#define NISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA 0x15
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#define NISLANDS_DPM2_SQ_RAMP_STI_SIZE 0x1E
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#define NISLANDS_DPM2_SQ_RAMP_LTI_RATIO 0xF
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int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,
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u32 arb_freq_src, u32 arb_freq_dest);
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void ni_update_current_ps(struct radeon_device *rdev,
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struct radeon_ps *rps);
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void ni_update_requested_ps(struct radeon_device *rdev,
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struct radeon_ps *rps);
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void ni_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
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struct radeon_ps *new_ps,
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struct radeon_ps *old_ps);
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void ni_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
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struct radeon_ps *new_ps,
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struct radeon_ps *old_ps);
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bool ni_dpm_vblank_too_short(struct radeon_device *rdev);
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#endif
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