139 lines
4.3 KiB
C
139 lines
4.3 KiB
C
/*
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* Copyright © 2010 Daniel Vetter
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "i915_drm.h"
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#include "i915_drv.h"
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//#include "i915_trace.h"
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#include "intel_drv.h"
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#define AGP_USER_TYPES (1 << 16)
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#define AGP_USER_MEMORY (AGP_USER_TYPES)
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#define AGP_USER_CACHED_MEMORY (AGP_USER_TYPES + 1)
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/* XXX kill agp_type! */
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static unsigned int cache_level_to_agp_type(struct drm_device *dev,
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enum i915_cache_level cache_level)
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{
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switch (cache_level) {
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case I915_CACHE_LLC_MLC:
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if (INTEL_INFO(dev)->gen >= 6)
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return AGP_USER_CACHED_MEMORY_LLC_MLC;
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/* Older chipsets do not have this extra level of CPU
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* cacheing, so fallthrough and request the PTE simply
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* as cached.
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*/
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case I915_CACHE_LLC:
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return AGP_USER_CACHED_MEMORY;
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default:
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case I915_CACHE_NONE:
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return AGP_USER_MEMORY;
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}
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}
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#if 0
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void i915_gem_restore_gtt_mappings(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_i915_gem_object *obj;
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/* First fill our portion of the GTT with scratch pages */
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intel_gtt_clear_range(dev_priv->mm.gtt_start / PAGE_SIZE,
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(dev_priv->mm.gtt_end - dev_priv->mm.gtt_start) / PAGE_SIZE);
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list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
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i915_gem_clflush_object(obj);
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i915_gem_gtt_rebind_object(obj, obj->cache_level);
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}
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intel_gtt_chipset_flush();
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}
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#endif
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int i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj)
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{
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struct drm_device *dev = obj->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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unsigned int agp_type = cache_level_to_agp_type(dev, obj->cache_level);
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int ret;
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ENTER();
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// if (dev_priv->mm.gtt->needs_dmar) {
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// ret = intel_gtt_map_memory(obj->pages,
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// obj->base.size >> PAGE_SHIFT,
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// &obj->sg_list,
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// &obj->num_sg);
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// if (ret != 0)
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// return ret;
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// intel_gtt_insert_sg_entries(obj->sg_list,
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// obj->num_sg,
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// obj->gtt_space->start >> PAGE_SHIFT,
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// agp_type);
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// } else
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intel_gtt_insert_pages(obj->gtt_space->start >> PAGE_SHIFT,
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obj->base.size >> PAGE_SHIFT,
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obj->pages,
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agp_type);
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LEAVE();
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return 0;
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}
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#if 0
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void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj,
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enum i915_cache_level cache_level)
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{
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struct drm_device *dev = obj->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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unsigned int agp_type = cache_level_to_agp_type(dev, cache_level);
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if (dev_priv->mm.gtt->needs_dmar) {
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BUG_ON(!obj->sg_list);
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intel_gtt_insert_sg_entries(obj->sg_list,
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obj->num_sg,
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obj->gtt_space->start >> PAGE_SHIFT,
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agp_type);
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} else
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intel_gtt_insert_pages(obj->gtt_space->start >> PAGE_SHIFT,
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obj->base.size >> PAGE_SHIFT,
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obj->pages,
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agp_type);
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}
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void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj)
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{
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intel_gtt_clear_range(obj->gtt_space->start >> PAGE_SHIFT,
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obj->base.size >> PAGE_SHIFT);
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if (obj->sg_list) {
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intel_gtt_unmap_memory(obj->sg_list, obj->num_sg);
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obj->sg_list = NULL;
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}
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}
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#endif
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