274 lines
7.5 KiB
C++
274 lines
7.5 KiB
C++
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#define R300_TEST
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#include "r5xx_regs.h"
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#define R5XX_LOOP_COUNT 2000000
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#define RADEON_CLOCK_CNTL_DATA 0x000c
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#define RADEON_CLOCK_CNTL_INDEX 0x0008
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# define RADEON_PLL_WR_EN (1 << 7)
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# define RADEON_PLL_DIV_SEL (3 << 8)
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# define RADEON_PLL2_DIV_SEL_MASK ~(3 << 8)
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#define RADEON_MCLK_CNTL 0x0012 /* PLL */
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# define RADEON_FORCEON_MCLKA (1 << 16)
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# define RADEON_FORCEON_MCLKB (1 << 17)
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# define RADEON_FORCEON_YCLKA (1 << 18)
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# define RADEON_FORCEON_YCLKB (1 << 19)
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# define RADEON_FORCEON_MC (1 << 20)
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# define RADEON_FORCEON_AIC (1 << 21)
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# define R300_DISABLE_MC_MCLKA (1 << 21)
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# define R300_DISABLE_MC_MCLKB (1 << 21)
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void radeon_engine_reset(RHDPtr info)
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{
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u32_t clock_cntl_index;
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u32_t mclk_cntl;
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u32_t rbbm_soft_reset;
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u32_t host_path_cntl;
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if (info->ChipFamily <= CHIP_FAMILY_RV410)
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{
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/* may need something similar for newer chips */
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clock_cntl_index = INREG(RADEON_CLOCK_CNTL_INDEX);
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mclk_cntl = INPLL( RADEON_MCLK_CNTL);
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OUTPLL(RADEON_MCLK_CNTL, (mclk_cntl |
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RADEON_FORCEON_MCLKA |
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RADEON_FORCEON_MCLKB |
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RADEON_FORCEON_YCLKA |
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RADEON_FORCEON_YCLKB |
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RADEON_FORCEON_MC |
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RADEON_FORCEON_AIC));
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}
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rbbm_soft_reset = INREG(RADEON_RBBM_SOFT_RESET);
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OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
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RADEON_SOFT_RESET_CP |
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RADEON_SOFT_RESET_HI |
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RADEON_SOFT_RESET_SE |
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RADEON_SOFT_RESET_RE |
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RADEON_SOFT_RESET_PP |
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RADEON_SOFT_RESET_E2 |
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RADEON_SOFT_RESET_RB));
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INREG(RADEON_RBBM_SOFT_RESET);
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OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
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~(RADEON_SOFT_RESET_CP |
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RADEON_SOFT_RESET_HI |
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RADEON_SOFT_RESET_SE |
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RADEON_SOFT_RESET_RE |
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RADEON_SOFT_RESET_PP |
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RADEON_SOFT_RESET_E2 |
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RADEON_SOFT_RESET_RB)));
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INREG(RADEON_RBBM_SOFT_RESET);
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if (info->ChipFamily <= CHIP_FAMILY_RV410) {
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OUTPLL(RADEON_MCLK_CNTL, mclk_cntl);
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OUTREG(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
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OUTREG(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
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}
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};
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static Bool R5xxFIFOWaitLocal(u32_t required) //R100-R500
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{
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int i;
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for (i = 0; i < RADEON_TIMEOUT; i++)
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if (required <= (INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK))
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return TRUE;
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dbgprintf("%s: Timeout 0x%08X.\n", __func__, (u32_t) INREG(RADEON_RBBM_STATUS));
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return FALSE;
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}
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void FIFOWait(u32_t required)
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{
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int i;
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for (i = 0; i < 200; i++)
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{
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if (required <= (INREG(RADEON_RBBM_STATUS) &
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RADEON_RBBM_FIFOCNT_MASK))
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return ;
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delay(2);
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};
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};
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/*
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* Flush all dirty data in the Pixel Cache to memory.
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*/
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static Bool
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R5xx2DFlush()
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{
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int i;
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MASKREG(R5XX_DSTCACHE_CTLSTAT,
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R5XX_DSTCACHE_FLUSH_ALL, R5XX_DSTCACHE_FLUSH_ALL);
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for (i = 0; i < R5XX_LOOP_COUNT; i++)
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if (!(INREG(R5XX_DSTCACHE_CTLSTAT) & R5XX_DSTCACHE_BUSY))
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return TRUE;
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dbgprintf("%s: Timeout 0x%08x.\n", __func__,
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(unsigned int)INREG(R5XX_DSTCACHE_CTLSTAT));
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return FALSE;
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}
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static Bool
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R5xx2DIdleLocal() //R100-R500
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{
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int i;
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/* wait for fifo to clear */
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for (i = 0; i < R5XX_LOOP_COUNT; i++)
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if (64 == (INREG(R5XX_RBBM_STATUS) & R5XX_RBBM_FIFOCNT_MASK))
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break;
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if (i == R5XX_LOOP_COUNT) {
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dbgprintf("%s: FIFO Timeout 0x%08X.\n", __func__,INREG(R5XX_RBBM_STATUS));
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return FALSE;
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}
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/* wait for engine to go idle */
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for (i = 0; i < R5XX_LOOP_COUNT; i++) {
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if (!(INREG(R5XX_RBBM_STATUS) & R5XX_RBBM_ACTIVE)) {
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R5xx2DFlush();
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return TRUE;
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}
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}
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dbgprintf("%s: Idle Timeout 0x%08X.\n", __func__,INREG(R5XX_RBBM_STATUS));
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return FALSE;
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}
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void
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R5xx2DSetup()
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{
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/* Setup engine location. This shouldn't be necessary since we
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* set them appropriately before any accel ops, but let's avoid
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* random bogus DMA in case we inadvertently trigger the engine
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* in the wrong place (happened). */
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R5xxFIFOWaitLocal(2);
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OUTREG(R5XX_DST_PITCH_OFFSET,rhd.dst_pitch_offset);
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OUTREG(R5XX_SRC_PITCH_OFFSET,rhd.dst_pitch_offset);
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R5xxFIFOWaitLocal(1);
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MASKREG(R5XX_DP_DATATYPE, 0, R5XX_HOST_BIG_ENDIAN_EN);
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OUTREG(R5XX_SURFACE_CNTL, rhd.surface_cntl);
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R5xxFIFOWaitLocal(3);
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OUTREG(R5XX_SC_TOP_LEFT, 0);
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OUTREG(R5XX_SC_BOTTOM_RIGHT,
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RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX);
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OUTREG(R5XX_DEFAULT_SC_BOTTOM_RIGHT,
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RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX);
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R5xxFIFOWaitLocal(1);
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// OUTREG(R5XX_DP_GUI_MASTER_CNTL, rhd.gui_control |
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// R5XX_GMC_BRUSH_SOLID_COLOR | R5XX_GMC_SRC_DATATYPE_COLOR);
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OUTREG(R5XX_DP_CNTL, R5XX_DST_X_LEFT_TO_RIGHT | R5XX_DST_Y_TOP_TO_BOTTOM);
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R5xxFIFOWaitLocal(5);
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OUTREG(R5XX_DP_BRUSH_FRGD_CLR, 0xFFFFFFFF);
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OUTREG(R5XX_DP_BRUSH_BKGD_CLR, 0x00000000);
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OUTREG(R5XX_DP_SRC_FRGD_CLR, 0xFFFFFFFF);
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OUTREG(R5XX_DP_SRC_BKGD_CLR, 0x00000000);
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OUTREG(R5XX_DP_WRITE_MASK, 0xFFFFFFFF);
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R5xx2DIdleLocal();
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}
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void R5xxFIFOWait(u32_t required)
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{
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if (!R5xxFIFOWaitLocal(required)) {
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radeon_engine_reset(&rhd);
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R5xx2DSetup();
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}
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}
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void R5xx2DIdle()
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{
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if (!R5xx2DIdleLocal()) {
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// R5xx2DReset();
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R5xx2DSetup();
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}
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}
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void R5xx2DInit()
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{
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u32_t base;
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int screensize;
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int screenpitch;
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screensize = GetScreenSize();
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screenpitch = GetScreenPitch();
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rhd.displayWidth = screensize >> 16;
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rhd.displayHeight = screensize & 0xFFFF;
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rhd.__xmin = 0;
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rhd.__ymin = 0;
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rhd.__xmax = rhd.displayWidth - 1;
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rhd.__ymax = rhd.displayHeight - 1;
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clip.xmin = 0;
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clip.ymin = 0;
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clip.xmax = rhd.displayWidth - 1;
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clip.ymax = rhd.displayHeight - 1;
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dbgprintf("screen width %d height %d\n",
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rhd.displayWidth, rhd.displayHeight);
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rhd.gui_control = ((6 << RADEON_GMC_DST_DATATYPE_SHIFT)
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| RADEON_GMC_CLR_CMP_CNTL_DIS
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| RADEON_GMC_DST_PITCH_OFFSET_CNTL);
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dbgprintf("gui_control %x \n", rhd.gui_control);
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rhd.surface_cntl = 0;
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rhd.dst_pitch_offset = (((rhd.displayWidth * 4 / 64)<< 22) |
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(rhd.fbLocation >> 10));
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dbgprintf("dst_pitch_offset %x \n", rhd.dst_pitch_offset);
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scr_pixmap.width = rhd.displayWidth;
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scr_pixmap.height = rhd.displayHeight;
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scr_pixmap.format = PICT_a8r8g8b8;
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scr_pixmap.flags = PX_MEM_LOCAL;
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scr_pixmap.pitch = rhd.displayWidth * 4 ;//screenpitch;
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scr_pixmap.local = rhd.fbLocation;
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scr_pixmap.pitch_offset = rhd.dst_pitch_offset;
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scr_pixmap.mapped = 0;
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R5xxFIFOWaitLocal(2);
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OUTREG(R5XX_DST_PITCH_OFFSET,rhd.dst_pitch_offset);
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OUTREG(R5XX_SRC_PITCH_OFFSET,rhd.dst_pitch_offset);
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R5xxFIFOWaitLocal(1);
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MASKREG(R5XX_DP_DATATYPE, 0, R5XX_HOST_BIG_ENDIAN_EN);
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OUTREG(R5XX_SURFACE_CNTL, rhd.surface_cntl);
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#if !R300_PIO
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init_cp(&rhd);
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#endif
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R5xx2DSetup();
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}
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