1147 lines
36 KiB
C
1147 lines
36 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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#ifndef __RADEON_H__
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#define __RADEON_H__
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//#include "radeon_object.h"
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/* TODO: Here are things that needs to be done :
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* - surface allocator & initializer : (bit like scratch reg) should
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* initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
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* related to surface
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* - WB : write back stuff (do it bit like scratch reg things)
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* - Vblank : look at Jesse's rework and what we should do
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* - r600/r700: gart & cp
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* - cs : clean cs ioctl use bitmap & things like that.
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* - power management stuff
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* - Barrier in gart code
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* - Unmappabled vram ?
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* - TESTING, TESTING, TESTING
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*/
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/* Initialization path:
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* We expect that acceleration initialization might fail for various
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* reasons even thought we work hard to make it works on most
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* configurations. In order to still have a working userspace in such
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* situation the init path must succeed up to the memory controller
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* initialization point. Failure before this point are considered as
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* fatal error. Here is the init callchain :
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* radeon_device_init perform common structure, mutex initialization
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* asic_init setup the GPU memory layout and perform all
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* one time initialization (failure in this
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* function are considered fatal)
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* asic_startup setup the GPU acceleration, in order to
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* follow guideline the first thing this
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* function should do is setting the GPU
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* memory controller (only MC setup failure
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* are considered as fatal)
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*/
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#include <types.h>
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#include <linux/list.h>
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#include <pci.h>
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#include <errno-base.h>
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#include "drm_edid.h"
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#include "radeon_family.h"
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#include "radeon_mode.h"
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#include "radeon_reg.h"
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#include <syscall.h>
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/*
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* Modules parameters.
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*/
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extern int radeon_no_wb;
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extern int radeon_modeset;
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extern int radeon_dynclks;
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extern int radeon_r4xx_atom;
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extern int radeon_agpmode;
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extern int radeon_vram_limit;
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extern int radeon_gart_size;
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extern int radeon_benchmarking;
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extern int radeon_testing;
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extern int radeon_connector_table;
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extern int radeon_tv;
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typedef struct
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{
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int width;
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int height;
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int bpp;
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int freq;
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}mode_t;
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static inline uint8_t __raw_readb(const volatile void __iomem *addr)
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{
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return *(const volatile uint8_t __force *) addr;
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}
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static inline uint16_t __raw_readw(const volatile void __iomem *addr)
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{
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return *(const volatile uint16_t __force *) addr;
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}
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static inline uint32_t __raw_readl(const volatile void __iomem *addr)
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{
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return *(const volatile uint32_t __force *) addr;
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}
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#define readb __raw_readb
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#define readw __raw_readw
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#define readl __raw_readl
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static inline void __raw_writeb(uint8_t b, volatile void __iomem *addr)
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{
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*(volatile uint8_t __force *) addr = b;
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}
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static inline void __raw_writew(uint16_t b, volatile void __iomem *addr)
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{
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*(volatile uint16_t __force *) addr = b;
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}
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static inline void __raw_writel(uint32_t b, volatile void __iomem *addr)
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{
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*(volatile uint32_t __force *) addr = b;
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}
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static inline void __raw_writeq(__u64 b, volatile void __iomem *addr)
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{
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*(volatile __u64 *)addr = b;
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}
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#define writeb __raw_writeb
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#define writew __raw_writew
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#define writel __raw_writel
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#define writeq __raw_writeq
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/*
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* Copy from radeon_drv.h so we don't have to include both and have conflicting
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* symbol;
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*/
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#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
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#define RADEON_IB_POOL_SIZE 16
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#define RADEON_DEBUGFS_MAX_NUM_FILES 32
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#define RADEONFB_CONN_LIMIT 4
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#define RADEON_BIOS_NUM_SCRATCH 8
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/*
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* Errata workarounds.
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*/
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enum radeon_pll_errata {
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CHIP_ERRATA_R300_CG = 0x00000001,
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CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
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CHIP_ERRATA_PLL_DELAY = 0x00000004
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};
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struct radeon_device;
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/*
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* BIOS.
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*/
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bool radeon_get_bios(struct radeon_device *rdev);
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/*
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* Dummy page
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*/
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struct radeon_dummy_page {
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struct page *page;
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dma_addr_t addr;
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};
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int radeon_dummy_page_init(struct radeon_device *rdev);
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void radeon_dummy_page_fini(struct radeon_device *rdev);
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/*
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* Clocks
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*/
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struct radeon_clock {
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struct radeon_pll p1pll;
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struct radeon_pll p2pll;
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struct radeon_pll spll;
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struct radeon_pll mpll;
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/* 10 Khz units */
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uint32_t default_mclk;
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uint32_t default_sclk;
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};
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/*
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* Fences.
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*/
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struct radeon_fence_driver {
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uint32_t scratch_reg;
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// atomic_t seq;
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uint32_t last_seq;
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unsigned long count_timeout;
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// wait_queue_head_t queue;
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// rwlock_t lock;
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struct list_head created;
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struct list_head emited;
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struct list_head signaled;
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};
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struct radeon_fence {
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struct radeon_device *rdev;
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// struct kref kref;
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struct list_head list;
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/* protected by radeon_fence.lock */
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uint32_t seq;
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unsigned long timeout;
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bool emited;
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bool signaled;
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};
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int radeon_fence_driver_init(struct radeon_device *rdev);
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void radeon_fence_driver_fini(struct radeon_device *rdev);
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int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
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int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
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void radeon_fence_process(struct radeon_device *rdev);
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bool radeon_fence_signaled(struct radeon_fence *fence);
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int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
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int radeon_fence_wait_next(struct radeon_device *rdev);
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int radeon_fence_wait_last(struct radeon_device *rdev);
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struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
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void radeon_fence_unref(struct radeon_fence **fence);
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/*
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* Tiling registers
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*/
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struct radeon_surface_reg {
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struct radeon_object *robj;
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};
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#define RADEON_GEM_MAX_SURFACES 8
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/*
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* Radeon buffer.
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*/
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struct radeon_object;
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struct radeon_object_list {
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struct list_head list;
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struct radeon_object *robj;
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uint64_t gpu_offset;
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unsigned rdomain;
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unsigned wdomain;
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uint32_t tiling_flags;
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};
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int radeon_object_init(struct radeon_device *rdev);
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void radeon_object_fini(struct radeon_device *rdev);
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int radeon_object_create(struct radeon_device *rdev,
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struct drm_gem_object *gobj,
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unsigned long size,
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bool kernel,
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uint32_t domain,
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bool interruptible,
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struct radeon_object **robj_ptr);
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/*
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* GEM objects.
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*/
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struct radeon_gem {
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struct list_head objects;
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};
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int radeon_gem_init(struct radeon_device *rdev);
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void radeon_gem_fini(struct radeon_device *rdev);
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int radeon_gem_object_create(struct radeon_device *rdev, int size,
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int alignment, int initial_domain,
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bool discardable, bool kernel,
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bool interruptible,
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struct drm_gem_object **obj);
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int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
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uint64_t *gpu_addr);
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void radeon_gem_object_unpin(struct drm_gem_object *obj);
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/*
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* GART structures, functions & helpers
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*/
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struct radeon_mc;
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struct radeon_gart_table_ram {
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volatile uint32_t *ptr;
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};
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struct radeon_gart_table_vram {
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struct radeon_object *robj;
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volatile uint32_t *ptr;
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};
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union radeon_gart_table {
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struct radeon_gart_table_ram ram;
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struct radeon_gart_table_vram vram;
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};
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struct radeon_gart {
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dma_addr_t table_addr;
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unsigned num_gpu_pages;
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unsigned num_cpu_pages;
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unsigned table_size;
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union radeon_gart_table table;
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struct page **pages;
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dma_addr_t *pages_addr;
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bool ready;
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};
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int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
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void radeon_gart_table_ram_free(struct radeon_device *rdev);
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int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
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void radeon_gart_table_vram_free(struct radeon_device *rdev);
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int radeon_gart_init(struct radeon_device *rdev);
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void radeon_gart_fini(struct radeon_device *rdev);
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void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
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int pages);
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int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
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int pages, u32_t *pagelist);
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/*
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* GPU MC structures, functions & helpers
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*/
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struct radeon_mc {
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resource_size_t aper_size;
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resource_size_t aper_base;
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resource_size_t agp_base;
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/* for some chips with <= 32MB we need to lie
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* about vram size near mc fb location */
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u64 mc_vram_size;
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u64 gtt_location;
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u64 gtt_size;
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u64 gtt_start;
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u64 gtt_end;
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u64 vram_location;
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u64 vram_start;
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u64 vram_end;
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unsigned vram_width;
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u64 real_vram_size;
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int vram_mtrr;
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bool vram_is_ddr;
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};
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int radeon_mc_setup(struct radeon_device *rdev);
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/*
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* GPU scratch registers structures, functions & helpers
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*/
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struct radeon_scratch {
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unsigned num_reg;
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bool free[32];
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uint32_t reg[32];
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};
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int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
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void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
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/*
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* IRQS.
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*/
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struct radeon_irq {
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bool installed;
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bool sw_int;
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/* FIXME: use a define max crtc rather than hardcode it */
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bool crtc_vblank_int[2];
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};
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int radeon_irq_kms_init(struct radeon_device *rdev);
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void radeon_irq_kms_fini(struct radeon_device *rdev);
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/*
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* CP & ring.
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*/
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struct radeon_ib {
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struct list_head list;
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unsigned long idx;
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uint64_t gpu_addr;
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struct radeon_fence *fence;
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uint32_t *ptr;
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uint32_t length_dw;
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};
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/*
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* locking -
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* mutex protects scheduled_ibs, ready, alloc_bm
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*/
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struct radeon_ib_pool {
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// struct mutex mutex;
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struct radeon_object *robj;
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struct list_head scheduled_ibs;
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struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
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bool ready;
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DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
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};
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struct radeon_cp {
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struct radeon_object *ring_obj;
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volatile uint32_t *ring;
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unsigned rptr;
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unsigned wptr;
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unsigned wptr_old;
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unsigned ring_size;
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unsigned ring_free_dw;
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int count_dw;
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uint64_t gpu_addr;
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uint32_t align_mask;
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uint32_t ptr_mask;
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// struct mutex mutex;
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bool ready;
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};
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struct r600_blit {
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struct radeon_object *shader_obj;
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u64 shader_gpu_addr;
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u32 vs_offset, ps_offset;
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u32 state_offset;
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u32 state_len;
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u32 vb_used, vb_total;
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struct radeon_ib *vb_ib;
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};
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int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
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void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
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int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
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int radeon_ib_pool_init(struct radeon_device *rdev);
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void radeon_ib_pool_fini(struct radeon_device *rdev);
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int radeon_ib_test(struct radeon_device *rdev);
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/* Ring access between begin & end cannot sleep */
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void radeon_ring_free_size(struct radeon_device *rdev);
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int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
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void radeon_ring_unlock_commit(struct radeon_device *rdev);
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void radeon_ring_unlock_undo(struct radeon_device *rdev);
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int radeon_ring_test(struct radeon_device *rdev);
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int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
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void radeon_ring_fini(struct radeon_device *rdev);
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/*
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* CS.
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*/
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struct radeon_cs_reloc {
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// struct drm_gem_object *gobj;
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struct radeon_object *robj;
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struct radeon_object_list lobj;
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uint32_t handle;
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uint32_t flags;
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};
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struct radeon_cs_chunk {
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uint32_t chunk_id;
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uint32_t length_dw;
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int kpage_idx[2];
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uint32_t *kpage[2];
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uint32_t *kdata;
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void __user *user_ptr;
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int last_copied_page;
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int last_page_index;
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};
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struct radeon_cs_parser {
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struct radeon_device *rdev;
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// struct drm_file *filp;
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/* chunks */
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unsigned nchunks;
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struct radeon_cs_chunk *chunks;
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uint64_t *chunks_array;
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/* IB */
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unsigned idx;
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/* relocations */
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unsigned nrelocs;
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struct radeon_cs_reloc *relocs;
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struct radeon_cs_reloc **relocs_ptr;
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struct list_head validated;
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/* indices of various chunks */
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int chunk_ib_idx;
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int chunk_relocs_idx;
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struct radeon_ib *ib;
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void *track;
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unsigned family;
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int parser_error;
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};
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extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
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extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
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static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
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{
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struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
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u32 pg_idx, pg_offset;
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u32 idx_value = 0;
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int new_page;
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pg_idx = (idx * 4) / PAGE_SIZE;
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pg_offset = (idx * 4) % PAGE_SIZE;
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if (ibc->kpage_idx[0] == pg_idx)
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return ibc->kpage[0][pg_offset/4];
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if (ibc->kpage_idx[1] == pg_idx)
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return ibc->kpage[1][pg_offset/4];
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new_page = radeon_cs_update_pages(p, pg_idx);
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if (new_page < 0) {
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p->parser_error = new_page;
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return 0;
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}
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idx_value = ibc->kpage[new_page][pg_offset/4];
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return idx_value;
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}
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struct radeon_cs_packet {
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unsigned idx;
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unsigned type;
|
|
unsigned reg;
|
|
unsigned opcode;
|
|
int count;
|
|
unsigned one_reg_wr;
|
|
};
|
|
|
|
typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
|
|
struct radeon_cs_packet *pkt,
|
|
unsigned idx, unsigned reg);
|
|
typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
|
|
struct radeon_cs_packet *pkt);
|
|
|
|
|
|
/*
|
|
* AGP
|
|
*/
|
|
int radeon_agp_init(struct radeon_device *rdev);
|
|
void radeon_agp_fini(struct radeon_device *rdev);
|
|
|
|
|
|
/*
|
|
* Writeback
|
|
*/
|
|
struct radeon_wb {
|
|
struct radeon_object *wb_obj;
|
|
volatile uint32_t *wb;
|
|
uint64_t gpu_addr;
|
|
};
|
|
|
|
/**
|
|
* struct radeon_pm - power management datas
|
|
* @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
|
|
* @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
|
|
* @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
|
|
* @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
|
|
* @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
|
|
* @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
|
|
* @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
|
|
* @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
|
|
* @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
|
|
* @sclk: GPU clock Mhz (core bandwith depends of this clock)
|
|
* @needed_bandwidth: current bandwidth needs
|
|
*
|
|
* It keeps track of various data needed to take powermanagement decision.
|
|
* Bandwith need is used to determine minimun clock of the GPU and memory.
|
|
* Equation between gpu/memory clock and available bandwidth is hw dependent
|
|
* (type of memory, bus size, efficiency, ...)
|
|
*/
|
|
struct radeon_pm {
|
|
fixed20_12 max_bandwidth;
|
|
fixed20_12 igp_sideport_mclk;
|
|
fixed20_12 igp_system_mclk;
|
|
fixed20_12 igp_ht_link_clk;
|
|
fixed20_12 igp_ht_link_width;
|
|
fixed20_12 k8_bandwidth;
|
|
fixed20_12 sideport_bandwidth;
|
|
fixed20_12 ht_bandwidth;
|
|
fixed20_12 core_bandwidth;
|
|
fixed20_12 sclk;
|
|
fixed20_12 needed_bandwidth;
|
|
};
|
|
|
|
/*
|
|
* ASIC specific functions.
|
|
*/
|
|
struct radeon_asic {
|
|
int (*init)(struct radeon_device *rdev);
|
|
void (*fini)(struct radeon_device *rdev);
|
|
int (*resume)(struct radeon_device *rdev);
|
|
int (*suspend)(struct radeon_device *rdev);
|
|
void (*vga_set_state)(struct radeon_device *rdev, bool state);
|
|
int (*gpu_reset)(struct radeon_device *rdev);
|
|
void (*gart_tlb_flush)(struct radeon_device *rdev);
|
|
int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
|
|
int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
|
|
void (*cp_fini)(struct radeon_device *rdev);
|
|
void (*cp_disable)(struct radeon_device *rdev);
|
|
void (*cp_commit)(struct radeon_device *rdev);
|
|
void (*ring_start)(struct radeon_device *rdev);
|
|
int (*ring_test)(struct radeon_device *rdev);
|
|
void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
|
|
int (*irq_set)(struct radeon_device *rdev);
|
|
int (*irq_process)(struct radeon_device *rdev);
|
|
u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
|
|
void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
|
|
int (*cs_parse)(struct radeon_cs_parser *p);
|
|
int (*copy_blit)(struct radeon_device *rdev,
|
|
uint64_t src_offset,
|
|
uint64_t dst_offset,
|
|
unsigned num_pages,
|
|
struct radeon_fence *fence);
|
|
int (*copy_dma)(struct radeon_device *rdev,
|
|
uint64_t src_offset,
|
|
uint64_t dst_offset,
|
|
unsigned num_pages,
|
|
struct radeon_fence *fence);
|
|
int (*copy)(struct radeon_device *rdev,
|
|
uint64_t src_offset,
|
|
uint64_t dst_offset,
|
|
unsigned num_pages,
|
|
struct radeon_fence *fence);
|
|
void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
|
|
void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
|
|
void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
|
|
void (*set_clock_gating)(struct radeon_device *rdev, int enable);
|
|
int (*set_surface_reg)(struct radeon_device *rdev, int reg,
|
|
uint32_t tiling_flags, uint32_t pitch,
|
|
uint32_t offset, uint32_t obj_size);
|
|
int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
|
|
void (*bandwidth_update)(struct radeon_device *rdev);
|
|
};
|
|
|
|
/*
|
|
* Asic structures
|
|
*/
|
|
struct r100_asic {
|
|
const unsigned *reg_safe_bm;
|
|
unsigned reg_safe_bm_size;
|
|
};
|
|
|
|
struct r300_asic {
|
|
const unsigned *reg_safe_bm;
|
|
unsigned reg_safe_bm_size;
|
|
};
|
|
|
|
struct r600_asic {
|
|
unsigned max_pipes;
|
|
unsigned max_tile_pipes;
|
|
unsigned max_simds;
|
|
unsigned max_backends;
|
|
unsigned max_gprs;
|
|
unsigned max_threads;
|
|
unsigned max_stack_entries;
|
|
unsigned max_hw_contexts;
|
|
unsigned max_gs_threads;
|
|
unsigned sx_max_export_size;
|
|
unsigned sx_max_export_pos_size;
|
|
unsigned sx_max_export_smx_size;
|
|
unsigned sq_num_cf_insts;
|
|
};
|
|
|
|
struct rv770_asic {
|
|
unsigned max_pipes;
|
|
unsigned max_tile_pipes;
|
|
unsigned max_simds;
|
|
unsigned max_backends;
|
|
unsigned max_gprs;
|
|
unsigned max_threads;
|
|
unsigned max_stack_entries;
|
|
unsigned max_hw_contexts;
|
|
unsigned max_gs_threads;
|
|
unsigned sx_max_export_size;
|
|
unsigned sx_max_export_pos_size;
|
|
unsigned sx_max_export_smx_size;
|
|
unsigned sq_num_cf_insts;
|
|
unsigned sx_num_of_sets;
|
|
unsigned sc_prim_fifo_size;
|
|
unsigned sc_hiz_tile_fifo_size;
|
|
unsigned sc_earlyz_tile_fifo_fize;
|
|
};
|
|
|
|
union radeon_asic_config {
|
|
struct r300_asic r300;
|
|
struct r100_asic r100;
|
|
struct r600_asic r600;
|
|
struct rv770_asic rv770;
|
|
};
|
|
|
|
|
|
/*
|
|
|
|
|
|
|
|
|
|
/*
|
|
* Core structure, functions and helpers.
|
|
*/
|
|
typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
|
|
typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
|
|
|
|
struct radeon_device {
|
|
void *dev;
|
|
struct drm_device *ddev;
|
|
struct pci_dev *pdev;
|
|
/* ASIC */
|
|
union radeon_asic_config config;
|
|
enum radeon_family family;
|
|
unsigned long flags;
|
|
int usec_timeout;
|
|
enum radeon_pll_errata pll_errata;
|
|
int num_gb_pipes;
|
|
int num_z_pipes;
|
|
int disp_priority;
|
|
/* BIOS */
|
|
uint8_t *bios;
|
|
bool is_atom_bios;
|
|
uint16_t bios_header_start;
|
|
|
|
// struct radeon_object *stollen_vga_memory;
|
|
struct fb_info *fbdev_info;
|
|
struct radeon_object *fbdev_robj;
|
|
struct radeon_framebuffer *fbdev_rfb;
|
|
/* Register mmio */
|
|
unsigned long rmmio_base;
|
|
unsigned long rmmio_size;
|
|
void *rmmio;
|
|
radeon_rreg_t mc_rreg;
|
|
radeon_wreg_t mc_wreg;
|
|
radeon_rreg_t pll_rreg;
|
|
radeon_wreg_t pll_wreg;
|
|
uint32_t pcie_reg_mask;
|
|
radeon_rreg_t pciep_rreg;
|
|
radeon_wreg_t pciep_wreg;
|
|
struct radeon_clock clock;
|
|
struct radeon_mc mc;
|
|
struct radeon_gart gart;
|
|
struct radeon_mode_info mode_info;
|
|
struct radeon_scratch scratch;
|
|
// struct radeon_mman mman;
|
|
struct radeon_fence_driver fence_drv;
|
|
struct radeon_cp cp;
|
|
struct radeon_ib_pool ib_pool;
|
|
// struct radeon_irq irq;
|
|
struct radeon_asic *asic;
|
|
struct radeon_gem gem;
|
|
struct radeon_pm pm;
|
|
uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
|
|
// struct mutex cs_mutex;
|
|
struct radeon_wb wb;
|
|
struct radeon_dummy_page dummy_page;
|
|
bool gpu_lockup;
|
|
bool shutdown;
|
|
bool suspend;
|
|
bool need_dma32;
|
|
bool accel_working;
|
|
struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
|
|
const struct firmware *me_fw; /* all family ME firmware */
|
|
const struct firmware *pfp_fw; /* r6/700 PFP firmware */
|
|
struct r600_blit r600_blit;
|
|
};
|
|
|
|
int radeon_device_init(struct radeon_device *rdev,
|
|
struct drm_device *ddev,
|
|
struct pci_dev *pdev,
|
|
uint32_t flags);
|
|
void radeon_device_fini(struct radeon_device *rdev);
|
|
int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
|
|
|
|
/* r600 blit */
|
|
int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
|
|
void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
|
|
void r600_kms_blit_copy(struct radeon_device *rdev,
|
|
u64 src_gpu_addr, u64 dst_gpu_addr,
|
|
int size_bytes);
|
|
|
|
static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
|
|
{
|
|
if (reg < 0x10000)
|
|
return readl(((void __iomem *)rdev->rmmio) + reg);
|
|
else {
|
|
writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
|
|
return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
|
|
}
|
|
}
|
|
|
|
static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
|
|
{
|
|
if (reg < 0x10000)
|
|
writel(v, ((void __iomem *)rdev->rmmio) + reg);
|
|
else {
|
|
writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
|
|
writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
|
|
}
|
|
}
|
|
|
|
|
|
/*
|
|
* Registers read & write functions.
|
|
*/
|
|
#define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
|
|
#define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
|
|
#define RREG32(reg) r100_mm_rreg(rdev, (reg))
|
|
#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
|
|
#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
|
|
#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
|
|
#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
|
|
#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
|
|
#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
|
|
#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
|
|
#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
|
|
#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
|
|
#define WREG32_P(reg, val, mask) \
|
|
do { \
|
|
uint32_t tmp_ = RREG32(reg); \
|
|
tmp_ &= (mask); \
|
|
tmp_ |= ((val) & ~(mask)); \
|
|
WREG32(reg, tmp_); \
|
|
} while (0)
|
|
#define WREG32_PLL_P(reg, val, mask) \
|
|
do { \
|
|
uint32_t tmp_ = RREG32_PLL(reg); \
|
|
tmp_ &= (mask); \
|
|
tmp_ |= ((val) & ~(mask)); \
|
|
WREG32_PLL(reg, tmp_); \
|
|
} while (0)
|
|
|
|
/*
|
|
* Indirect registers accessor
|
|
*/
|
|
static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
|
|
{
|
|
uint32_t r;
|
|
|
|
WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
|
|
r = RREG32(RADEON_PCIE_DATA);
|
|
return r;
|
|
}
|
|
|
|
static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
|
|
{
|
|
WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
|
|
WREG32(RADEON_PCIE_DATA, (v));
|
|
}
|
|
|
|
void r100_pll_errata_after_index(struct radeon_device *rdev);
|
|
|
|
|
|
|
|
enum chipset_type {
|
|
NOT_SUPPORTED,
|
|
SUPPORTED,
|
|
};
|
|
|
|
struct agp_version {
|
|
u16_t major;
|
|
u16_t minor;
|
|
};
|
|
|
|
struct agp_bridge_data;
|
|
|
|
struct agp_kern_info {
|
|
struct agp_version version;
|
|
struct pci_dev *device;
|
|
enum chipset_type chipset;
|
|
unsigned long mode;
|
|
unsigned long aper_base;
|
|
size_t aper_size;
|
|
int max_memory; /* In pages */
|
|
int current_memory;
|
|
bool cant_use_aperture;
|
|
unsigned long page_mask;
|
|
// struct vm_operations_struct *vm_ops;
|
|
};
|
|
|
|
|
|
/**
|
|
* AGP data.
|
|
*
|
|
* \sa drm_agp_init() and drm_device::agp.
|
|
*/
|
|
struct drm_agp_head {
|
|
struct agp_kern_info agp_info; /**< AGP device information */
|
|
// struct list_head memory;
|
|
unsigned long mode; /**< AGP mode */
|
|
struct agp_bridge_data *bridge;
|
|
int enabled; /**< whether the AGP bus as been enabled */
|
|
int acquired; /**< whether the AGP device has been acquired */
|
|
unsigned long base;
|
|
int agp_mtrr;
|
|
int cant_use_aperture;
|
|
unsigned long page_mask;
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
* ASICs helpers.
|
|
*/
|
|
#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
|
|
(rdev->pdev->device == 0x5969))
|
|
#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
|
|
(rdev->family == CHIP_RV200) || \
|
|
(rdev->family == CHIP_RS100) || \
|
|
(rdev->family == CHIP_RS200) || \
|
|
(rdev->family == CHIP_RV250) || \
|
|
(rdev->family == CHIP_RV280) || \
|
|
(rdev->family == CHIP_RS300))
|
|
#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
|
|
(rdev->family == CHIP_RV350) || \
|
|
(rdev->family == CHIP_R350) || \
|
|
(rdev->family == CHIP_RV380) || \
|
|
(rdev->family == CHIP_R420) || \
|
|
(rdev->family == CHIP_R423) || \
|
|
(rdev->family == CHIP_RV410) || \
|
|
(rdev->family == CHIP_RS400) || \
|
|
(rdev->family == CHIP_RS480))
|
|
#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
|
|
#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
|
|
#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
|
|
|
|
|
|
/*
|
|
* BIOS helpers.
|
|
*/
|
|
#define RBIOS8(i) (rdev->bios[i])
|
|
#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
|
|
#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
|
|
|
|
int radeon_combios_init(struct radeon_device *rdev);
|
|
void radeon_combios_fini(struct radeon_device *rdev);
|
|
int radeon_atombios_init(struct radeon_device *rdev);
|
|
void radeon_atombios_fini(struct radeon_device *rdev);
|
|
|
|
|
|
/*
|
|
* RING helpers.
|
|
*/
|
|
static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
|
|
{
|
|
#if DRM_DEBUG_CODE
|
|
if (rdev->cp.count_dw <= 0) {
|
|
DRM_ERROR("radeon: writting more dword to ring than expected !\n");
|
|
}
|
|
#endif
|
|
rdev->cp.ring[rdev->cp.wptr++] = v;
|
|
rdev->cp.wptr &= rdev->cp.ptr_mask;
|
|
rdev->cp.count_dw--;
|
|
rdev->cp.ring_free_dw--;
|
|
}
|
|
|
|
|
|
/*
|
|
* ASICs macro.
|
|
*/
|
|
#define radeon_init(rdev) (rdev)->asic->init((rdev))
|
|
#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
|
|
#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
|
|
#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
|
|
#define radeon_cs_parse(p) rdev->asic->cs_parse((p))
|
|
#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
|
|
#define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
|
|
#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
|
|
#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
|
|
#define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
|
|
#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
|
|
#define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
|
|
#define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
|
|
#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
|
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#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
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#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
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#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
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#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
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#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
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#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
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#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
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#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
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#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
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#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
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#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
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#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
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#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
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/* Common functions */
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extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
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extern int radeon_modeset_init(struct radeon_device *rdev);
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extern void radeon_modeset_fini(struct radeon_device *rdev);
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extern bool radeon_card_posted(struct radeon_device *rdev);
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extern int radeon_clocks_init(struct radeon_device *rdev);
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extern void radeon_clocks_fini(struct radeon_device *rdev);
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extern void radeon_scratch_init(struct radeon_device *rdev);
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extern void radeon_surface_init(struct radeon_device *rdev);
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extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
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extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
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extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
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/* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
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struct r100_mc_save {
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u32 GENMO_WT;
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u32 CRTC_EXT_CNTL;
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u32 CRTC_GEN_CNTL;
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u32 CRTC2_GEN_CNTL;
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u32 CUR_OFFSET;
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u32 CUR2_OFFSET;
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};
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extern void r100_cp_disable(struct radeon_device *rdev);
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extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
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extern void r100_cp_fini(struct radeon_device *rdev);
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extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
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extern int r100_pci_gart_init(struct radeon_device *rdev);
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extern void r100_pci_gart_fini(struct radeon_device *rdev);
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extern int r100_pci_gart_enable(struct radeon_device *rdev);
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extern void r100_pci_gart_disable(struct radeon_device *rdev);
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extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
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extern int r100_debugfs_mc_info_init(struct radeon_device *rdev);
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extern int r100_gui_wait_for_idle(struct radeon_device *rdev);
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extern void r100_ib_fini(struct radeon_device *rdev);
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extern int r100_ib_init(struct radeon_device *rdev);
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extern void r100_irq_disable(struct radeon_device *rdev);
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extern int r100_irq_set(struct radeon_device *rdev);
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extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
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extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
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extern void r100_vram_init_sizes(struct radeon_device *rdev);
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extern void r100_wb_disable(struct radeon_device *rdev);
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extern void r100_wb_fini(struct radeon_device *rdev);
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extern int r100_wb_init(struct radeon_device *rdev);
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extern void r100_hdp_reset(struct radeon_device *rdev);
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extern int r100_rb2d_reset(struct radeon_device *rdev);
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extern int r100_cp_reset(struct radeon_device *rdev);
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extern void r100_vga_render_disable(struct radeon_device *rdev);
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extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
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struct radeon_cs_packet *pkt,
|
|
struct radeon_object *robj);
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extern int r100_cs_parse_packet0(struct radeon_cs_parser *p,
|
|
struct radeon_cs_packet *pkt,
|
|
const unsigned *auth, unsigned n,
|
|
radeon_packet0_check_t check);
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extern int r100_cs_packet_parse(struct radeon_cs_parser *p,
|
|
struct radeon_cs_packet *pkt,
|
|
unsigned idx);
|
|
|
|
/* rv200,rv250,rv280 */
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extern void r200_set_safe_registers(struct radeon_device *rdev);
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|
|
|
/* r300,r350,rv350,rv370,rv380 */
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|
extern void r300_set_reg_safe(struct radeon_device *rdev);
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|
extern void r300_mc_program(struct radeon_device *rdev);
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|
extern void r300_vram_info(struct radeon_device *rdev);
|
|
extern void r300_clock_startup(struct radeon_device *rdev);
|
|
extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
|
|
extern int rv370_pcie_gart_init(struct radeon_device *rdev);
|
|
extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
|
|
extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
|
|
extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
|
|
|
|
/* r420,r423,rv410 */
|
|
extern int r420_mc_init(struct radeon_device *rdev);
|
|
extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
|
|
extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
|
|
extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
|
|
extern void r420_pipes_init(struct radeon_device *rdev);
|
|
|
|
/* rv515 */
|
|
struct rv515_mc_save {
|
|
u32 d1vga_control;
|
|
u32 d2vga_control;
|
|
u32 vga_render_control;
|
|
u32 vga_hdp_control;
|
|
u32 d1crtc_control;
|
|
u32 d2crtc_control;
|
|
};
|
|
extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
|
|
extern void rv515_vga_render_disable(struct radeon_device *rdev);
|
|
extern void rv515_set_safe_registers(struct radeon_device *rdev);
|
|
extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
|
|
extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
|
|
extern void rv515_clock_startup(struct radeon_device *rdev);
|
|
extern void rv515_debugfs(struct radeon_device *rdev);
|
|
extern int rv515_suspend(struct radeon_device *rdev);
|
|
|
|
/* rs400 */
|
|
extern int rs400_gart_init(struct radeon_device *rdev);
|
|
extern int rs400_gart_enable(struct radeon_device *rdev);
|
|
extern void rs400_gart_adjust_size(struct radeon_device *rdev);
|
|
extern void rs400_gart_disable(struct radeon_device *rdev);
|
|
extern void rs400_gart_fini(struct radeon_device *rdev);
|
|
|
|
/* rs600 */
|
|
extern void rs600_set_safe_registers(struct radeon_device *rdev);
|
|
extern int rs600_irq_set(struct radeon_device *rdev);
|
|
extern void rs600_irq_disable(struct radeon_device *rdev);
|
|
|
|
/* rs690, rs740 */
|
|
extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
|
|
struct drm_display_mode *mode1,
|
|
struct drm_display_mode *mode2);
|
|
|
|
/* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
|
|
extern bool r600_card_posted(struct radeon_device *rdev);
|
|
extern void r600_cp_stop(struct radeon_device *rdev);
|
|
extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
|
|
extern int r600_cp_resume(struct radeon_device *rdev);
|
|
extern int r600_count_pipe_bits(uint32_t val);
|
|
extern int r600_gart_clear_page(struct radeon_device *rdev, int i);
|
|
extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
|
|
extern int r600_pcie_gart_init(struct radeon_device *rdev);
|
|
extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
|
|
extern int r600_ib_test(struct radeon_device *rdev);
|
|
extern int r600_ring_test(struct radeon_device *rdev);
|
|
extern void r600_wb_fini(struct radeon_device *rdev);
|
|
extern int r600_wb_enable(struct radeon_device *rdev);
|
|
extern void r600_wb_disable(struct radeon_device *rdev);
|
|
extern void r600_scratch_init(struct radeon_device *rdev);
|
|
extern int r600_blit_init(struct radeon_device *rdev);
|
|
extern void r600_blit_fini(struct radeon_device *rdev);
|
|
extern int r600_cp_init_microcode(struct radeon_device *rdev);
|
|
extern int r600_gpu_reset(struct radeon_device *rdev);
|
|
|
|
|
|
|
|
#define DRM_UDELAY(d) udelay(d)
|
|
|
|
resource_size_t
|
|
drm_get_resource_start(struct drm_device *dev, unsigned int resource);
|
|
resource_size_t
|
|
drm_get_resource_len(struct drm_device *dev, unsigned int resource);
|
|
|
|
bool set_mode(struct drm_device *dev, struct drm_connector *connector,
|
|
mode_t *mode, bool strict);
|
|
|
|
|
|
#endif
|