589 lines
15 KiB
C
Executable File
589 lines
15 KiB
C
Executable File
#include "pxa255_UART.h"
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#include "mem.h"
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//TODO: signal handler for Ctl+C and send break to fifo :)
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//todo: recalc ints after eveyr write and every call to "process" from SoC
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#define UART_IER_DMAE 0x80 //DMA enable
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#define UART_IER_UUE 0x40 //Uart unit enable
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#define UART_IER_NRZE 0x20 //NRZI enable
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#define UART_IER_RTOIE 0x10 //transmit timeout interrupt enable
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#define UART_IER_MIE 0x08 //modem interrupt enable
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#define UART_IER_RLSE 0x04 //receiver line status interrupt enable
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#define UART_IER_TIE 0x02 //transmit data request interrupt enable
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#define UART_IER_RAVIE 0x01 //receiver data available interrupt enable
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#define UART_IIR_FIFOES 0xC0 //fifo enable status
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#define UART_IIR_TOD 0x08 //character timout interrupt pending
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#define UART_IIR_RECV_ERR 0x06 //receive error(overrun, parity, framing, break)
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#define UART_IIR_RECV_DATA 0x04 //receive data available
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#define UART_IIR_RCV_TIMEOUT 0x0C //receive data in buffer and been a while since we've seen more
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#define UART_IIR_SEND_DATA 0x02 //transmit fifo requests data
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#define UART_IIR_MODEM_STAT 0x00 //modem lines changed state(CTS, DSR, DI, DCD)
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#define UART_IIR_NOINT 0x01 //no interrupt pending
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#define UART_FCR_ITL_MASK 0xC0 //mask for ITL part of FCR
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#define UART_FCR_ITL_1 0x00 //interrupt when >=1 byte in recv fifo
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#define UART_FCR_ITL_8 0x40 //interrupt when >=8 byte in recv fifo
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#define UART_FCR_ITL_16 0x80 //interrupt when >=16 byte in recv fifo
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#define UART_FCR_ITL_32 0xC0 //interrupt when >=32 byte in recv fifo
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#define UART_FCR_RESETTF 0x04 //reset tranmitter fifo
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#define UART_FCR_RESETRF 0x02 //reset receiver fifo
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#define UART_FCR_TRFIFOE 0x01 //transmit and receive fifo enable
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#define UART_LCR_DLAB 0x80 //divisor latch access bit
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#define UART_LCR_SB 0x40 //send break
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#define UART_LCR_STKYP 0x20 //sticky parity (send parity bit but dont care what value)
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#define UART_LCR_EPS 0x10 //even parity select
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#define UART_LCR_PEN 0x08 //parity enable
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#define UART_LCR_STB 0x04 //stop bits (1 = 2, 0 = 1)
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#define UART_LCR_WLS_MASK 0x03 //mask for WLS values
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#define UART_LCR_WLS_8 0x03 //8 bit words
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#define UART_LCR_WLS_7 0x02 //7 bit words
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#define UART_LCR_WLS_6 0x01 //6 bit words
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#define UART_LCR_WLS_5 0x00 //5 bit words
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#define UART_LSR_FIFOE 0x80 //fifo contails an error (framing, parity, or break)
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#define UART_LSR_TEMT 0x40 //tranmitter empty (shift reg is empty and no more byte sin fifo/no byte in holding reg)
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#define UART_LSR_TDRQ 0x20 //transmitter data request (see docs)
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#define UART_LSR_BI 0x10 //send when char at front of fifo (or in holding reg) was a break char (chr reads as zero by itself)
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#define UART_LSR_FE 0x08 //same as above, but for framing errors
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#define UART_LSR_PE 0x04 //dame as above, but for parity errors
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#define UART_LSR_OE 0x02 //recv fifo overran
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#define UART_LSR_DR 0x01 //byte received
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#define UART_MCR_LOOP 0x10 //loop modem control lines (not full loopback)
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#define UART_MCR_OUT2 0x08 //when loop is 0 enables or disables UART interrupts
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#define UART_MCR_OUT1 0x04 //force RI to 1
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#define UART_MCR_RTS 0x02 //1 -> nRTS is 0
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#define UART_MCR_DTR 0x01 //0 -> nDTR is 0
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#define UART_MSR_DCD 0x80
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#define UART_MSR_RI 0x40
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#define UART_MSR_DSR 0x20
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#define UART_MSR_CTS 0x10
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#define UART_MSR_DDCD 0x08 //dcd changed since last read
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#define UART_MSR_TERI 0x04 //ri has changed from 0 to 1 since last read
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#define UART_MSR_DDSR 0x02 //dsr changed since last read
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#define UART_MSR_DCTS 0x01 //cts changed since last read
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static void pxa255uartPrvRecalc(Pxa255uart* uart);
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static void pxa255uartPrvIrq(Pxa255uart* uart, Boolean raise){
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pxa255icInt(uart->ic, uart->irq, !(uart->MCR & UART_MCR_LOOP) && (uart->MCR & UART_MCR_OUT2) && raise/* only raise if ints are enabled */);
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}
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static UInt16 pxa255uartPrvDefaultRead(_UNUSED_ void* userData){ //these are special funcs since they always get their own userData - the uart pointer :)
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return UART_CHAR_NONE; //we read nothing..as always
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}
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static void pxa255uartPrvDefaultWrite(_UNUSED_ UInt16 chr, _UNUSED_ void* userData){ //these are special funcs since they always get their own userData - the uart pointer :)
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//nothing to do here
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}
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static UInt16 pxa255uartPrvGetchar(Pxa255uart* uart){
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Pxa255UartReadF func = uart->readF;
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void* data = (func == pxa255uartPrvDefaultRead) ? uart : uart->accessFuncsData;
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return func(data);
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}
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static void pxa255uartPrvPutchar(Pxa255uart* uart, UInt16 chr){
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Pxa255UartWriteF func = uart->writeF;
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void* data = (func == pxa255uartPrvDefaultWrite) ? uart : uart->accessFuncsData;
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func(chr, data);
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}
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UInt8 pxa255uartPrvFifoUsed(UartFifo* fifo){ //return num spots used
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UInt8 v;
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if(fifo->read == UART_FIFO_EMPTY) return 0;
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v = fifo->write + UART_FIFO_DEPTH - fifo->read;
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if(v > UART_FIFO_DEPTH) v -=UART_FIFO_DEPTH;
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return v;
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}
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void pxa255uartPrvFifoFlush(UartFifo* fifo){
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fifo->read = UART_FIFO_EMPTY;
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fifo->write = UART_FIFO_EMPTY;
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}
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Boolean pxa255uartPrvFifoPut(UartFifo* fifo, UInt16 val){ //return success
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if(fifo->read == UART_FIFO_EMPTY){
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fifo->read = 0;
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fifo->write = 1;
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fifo->buf[0] = val;
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}
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else if(fifo->read != fifo->write){ //only if not full
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fifo->buf[fifo->write++] = val;
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if(fifo->write == UART_FIFO_DEPTH) fifo->write = 0;
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}
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else return false;
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return true;
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}
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UInt16 pxa255uartPrvFifoGet(UartFifo* fifo){
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UInt16 ret;
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if(fifo->read == UART_FIFO_EMPTY){
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ret = 0xFFFF; //why not?
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}
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else{
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ret = fifo->buf[fifo->read++];
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if(fifo->read == UART_FIFO_DEPTH) fifo->read = 0;
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if(fifo->read == fifo->write){ //it is now empty
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fifo->read = UART_FIFO_EMPTY;
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fifo->write = UART_FIFO_EMPTY;
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}
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}
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return ret;
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}
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UInt16 pxa255uartPrvFifoPeekNth(UartFifo* fifo, UInt8 n){
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UInt16 ret;
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if(fifo->read == UART_FIFO_EMPTY){
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ret = 0xFFFF; //why not?
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}
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else{
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n += fifo->read;
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if(n >= UART_FIFO_DEPTH) n-= UART_FIFO_DEPTH;
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ret = fifo->buf[n];
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}
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return ret;
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}
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UInt16 pxa255uartPrvFifoPeek(UartFifo* fifo){
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return pxa255uartPrvFifoPeekNth(fifo, 0);
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}
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static void sendVal(Pxa255uart* uart, UInt16 v){
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if(uart->LSR & UART_LSR_TEMT){ //if transmit, put in shift register immediately if it's idle
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uart->transmitShift = v;
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uart->LSR &=~ UART_LSR_TEMT;
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}
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else if(uart->FCR & UART_FCR_TRFIFOE){ //put in tx fifo if in fifo mode
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pxa255uartPrvFifoPut(&uart->TX, v);
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if(pxa255uartPrvFifoUsed(&uart->TX) > UART_FIFO_DEPTH / 2){ //we go went below half-full buffer - set appropriate bit...
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uart->LSR &=~ UART_LSR_TDRQ;
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}
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}
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else if(uart->LSR & UART_LSR_TDRQ){ //send without fifo if in polled mode
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uart->transmitHolding = v;
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uart->LSR &=~ UART_LSR_TDRQ;
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}
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else{
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//nothing to do - buffer is full so we ignore this request
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}
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}
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static Boolean pxa255uartPrvMemAccessF(void* userData, UInt32 pa, UInt8 size, Boolean write, void* buf){
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Pxa255uart* uart = userData;
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Boolean DLAB = (uart->LCR & UART_LCR_DLAB) != 0;
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Boolean recalcValues = false;
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UInt8 t, val = 0;
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if(size != 4 && size != 1) {
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err_str(__FILE__ ": Unexpected ");
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// err_str(write ? "write" : "read");
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// err_str(" of ");
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// err_dec(size);
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// err_str(" bytes to 0x");
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// err_hex(pa);
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// err_str("\r\n");
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return true; //we do not support non-word accesses
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}
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pa = (pa - uart->baseAddr) >> 2;
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if(write){
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recalcValues = true;
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val = (size == 1) ? *(UInt8*)buf : *(UInt32*)buf;
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switch(pa){
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case 0:
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if(DLAB){ //if DLAB - set "baudrate"...
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uart->DLL = val;
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recalcValues = false;
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}
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else{
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sendVal(uart, val);
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}
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break;
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case 1:
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if(DLAB){
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uart->DLH = val;
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recalcValues = false;
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}
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else{
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t = uart->IER ^ val;
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if(t & UART_IER_DMAE){
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err_str("pxa255UART: DMA mode cannot be enabled");
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t &=~ UART_IER_DMAE; //undo the change
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}
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if(t & UART_IER_UUE){
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if(val & UART_IER_UUE){
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uart->LSR = UART_LSR_TEMT | UART_LSR_TDRQ;
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uart->MSR = UART_MSR_CTS;
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}
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}
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uart->IER ^= t;
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}
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break;
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case 2:
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t = uart->FCR ^ val;
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if(t & UART_FCR_TRFIFOE){
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if(val & UART_FCR_TRFIFOE){ //fifos are now on - perform other actions as requested
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if(val & UART_FCR_RESETRF){
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pxa255uartPrvFifoFlush(&uart->RX); //clear the RX fifo now
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}
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if(val & UART_FCR_RESETTF){
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pxa255uartPrvFifoFlush(&uart->TX); //clear the TX fifo now
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uart->LSR = UART_LSR_TEMT | UART_LSR_TDRQ;
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}
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uart->IIR = UART_IIR_FIFOES |UART_IIR_NOINT;
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}
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else{
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pxa255uartPrvFifoFlush(&uart->TX);
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pxa255uartPrvFifoFlush(&uart->RX);
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uart->LSR = UART_LSR_TEMT | UART_LSR_TDRQ;
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uart->IIR = UART_IIR_NOINT;
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}
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}
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uart->FCR = val;
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break;
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case 3:
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t = uart->LCR ^ val;
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if(t & UART_LCR_SB){
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if(val & UART_LCR_SB){ //break set (tx line pulled low)
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}
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else{ //break cleared (tx line released)
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sendVal(uart, UART_CHAR_BREAK);
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}
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}
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uart->LCR = val;
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break;
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case 4:
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uart->MCR = val;
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break;
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case 7:
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uart->SPR = val;
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break;
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case 8:
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uart->ISR = val;
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if(val & 3){
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err_str("UART: IrDA mode set on UART\n");
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}
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break;
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}
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}
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else{
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switch(pa){
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case 0:
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if(DLAB) val = uart->DLL;
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else if(!(uart->LSR & UART_LSR_DR)){ //no data-> too bad
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val = 0;
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}
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else if(uart->FCR & UART_FCR_TRFIFOE){ //fifo mode -> read fifo
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val = pxa255uartPrvFifoGet(&uart->RX);
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if(!pxa255uartPrvFifoUsed(&uart->RX)) uart->LSR &=~ UART_LSR_DR;
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recalcValues = true; //error bits might have changed
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}
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else{ //polled mode -> read rx polled reg
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val = uart->receiveHolding;
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uart->LSR &=~ UART_LSR_DR;
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}
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break;
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case 1:
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if(DLAB) val = uart->DLH;
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else val = uart->IER;
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break;
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case 2:
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val = uart->IIR;
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break;
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case 3:
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val = uart->LCR;
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break;
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case 4:
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val = uart->MCR;
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break;
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case 5:
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val = uart->LSR;
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break;
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case 6:
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val = uart->MSR;
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break;
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case 7:
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val = uart->SPR;
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break;
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case 8:
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val = uart->ISR;
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break;
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}
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if(size == 1) *(UInt8*)buf = val;
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else *(UInt32*)buf = val;
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}
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if(recalcValues) pxa255uartPrvRecalc(uart);
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return true;
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}
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void pxa255uartSetFuncs(Pxa255uart* uart, Pxa255UartReadF readF, Pxa255UartWriteF writeF, void* userData){
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if(!readF) readF = pxa255uartPrvDefaultRead; //these are special funcs since they get their own private data - the uart :)
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if(!writeF) writeF = pxa255uartPrvDefaultWrite;
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uart->readF = readF;
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uart->writeF = writeF;
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uart->accessFuncsData = userData;
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}
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Boolean pxa255uartInit(Pxa255uart* uart, ArmMem* physMem, Pxa255ic* ic, UInt32 baseAddr, UInt8 irq){
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__mem_zero(uart, sizeof(Pxa255uart));
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uart->ic = ic;
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uart->irq = irq;
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uart->baseAddr = baseAddr;
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uart->IIR = UART_IIR_NOINT;
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uart->IER = UART_IER_UUE | UART_IER_NRZE; //uart on
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uart->LSR = UART_LSR_TEMT | UART_LSR_TDRQ;
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uart->MSR = UART_MSR_CTS;
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pxa255uartPrvFifoFlush(&uart->TX);
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pxa255uartPrvFifoFlush(&uart->RX);
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pxa255uartSetFuncs(uart, NULL, NULL, NULL);
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return memRegionAdd(physMem, baseAddr, PXA255_UART_SIZE, pxa255uartPrvMemAccessF, uart);
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}
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void pxa255uartProcess(Pxa255uart* uart){ //send and rceive up to one character
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UInt8 t;
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UInt16 v;
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//first process sending (if any)
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if(!(uart->LSR & UART_LSR_TEMT)){
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pxa255uartPrvPutchar(uart, uart->transmitShift);
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if(uart->FCR & UART_FCR_TRFIFOE){ //fifo mode
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t = pxa255uartPrvFifoUsed(&uart->TX);
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if(t--){
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uart->transmitShift = pxa255uartPrvFifoGet(&uart->TX);
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if(t <= UART_FIFO_DEPTH / 2) uart->LSR |= UART_LSR_TDRQ; //above half full - clear TDRQ bit
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}
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else{
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uart->LSR |= UART_LSR_TEMT;
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}
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}
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else if (uart->LSR & UART_LSR_TDRQ){
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uart->LSR |= UART_LSR_TEMT;
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}
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else{
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uart->transmitShift = uart->transmitHolding;
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uart->LSR |= UART_LSR_TDRQ;
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}
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}
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//now process receiving
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v = pxa255uartPrvGetchar(uart);
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if(v != UART_CHAR_NONE){
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uart->cyclesSinceRecv = 0;
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uart->LSR |= UART_LSR_DR;
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if(uart->FCR & UART_FCR_TRFIFOE){ //fifo mode
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if(!pxa255uartPrvFifoPut(&uart->RX, v)){
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uart->LSR |= UART_LSR_OE;
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}
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}
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else{
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if(uart->LSR & UART_LSR_DR) uart->LSR |= UART_LSR_OE;
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else uart->receiveHolding = v;
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}
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}
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else if(uart->cyclesSinceRecv <= 4){
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uart->cyclesSinceRecv++;
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}
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pxa255uartPrvRecalc(uart);
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}
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static void pxa255uartPrvRecalcCharBits(Pxa255uart* uart, UInt16 c){
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if(c & UART_CHAR_BREAK) uart->LSR |= UART_LSR_BI;
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if(c & UART_CHAR_FRAME_ERR) uart->LSR |= UART_LSR_FE;
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if(c & UART_CHAR_PAR_ERR) uart->LSR |= UART_LSR_PE;
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|
}
|
|
|
|
static void pxa255uartPrvRecalc(Pxa255uart* uart){
|
|
|
|
Boolean errorSet = false;
|
|
UInt8 v;
|
|
|
|
uart->LSR &=~ UART_LSR_FIFOE;
|
|
uart->IIR &= UART_IIR_FIFOES; //clear all other bits...
|
|
uart->LSR &=~ (UART_LSR_BI | UART_LSR_FE | UART_LSR_PE);
|
|
|
|
if(uart->FCR & UART_FCR_TRFIFOE){ //fifo mode
|
|
|
|
|
|
//check rx fifo for errors
|
|
for(v = 0; v < pxa255uartPrvFifoUsed(&uart->RX); v++){
|
|
|
|
if((pxa255uartPrvFifoPeekNth(&uart->RX, v) >> 8) && (uart->IER & UART_IER_RLSE)){
|
|
|
|
uart->LSR |= UART_LSR_FIFOE;
|
|
uart->IIR |= UART_IIR_RECV_ERR;
|
|
errorSet = true;
|
|
break;
|
|
}
|
|
}
|
|
|
|
v = pxa255uartPrvFifoUsed(&uart->RX);
|
|
if(v){
|
|
pxa255uartPrvRecalcCharBits(uart, pxa255uartPrvFifoPeek(&uart->RX));
|
|
}
|
|
|
|
switch(uart->FCR & UART_FCR_ITL_MASK){
|
|
|
|
case UART_FCR_ITL_1:
|
|
v = v >= 1;
|
|
break;
|
|
|
|
case UART_FCR_ITL_8:
|
|
v = v >= 8;
|
|
break;
|
|
|
|
case UART_FCR_ITL_16:
|
|
v = v >= 16;
|
|
break;
|
|
|
|
case UART_FCR_ITL_32:
|
|
v = v >= 32;
|
|
break;
|
|
}
|
|
if(v && (uart->IER & UART_IER_RAVIE) && !errorSet){
|
|
|
|
errorSet = true;
|
|
uart->IIR |= UART_IIR_RECV_DATA;
|
|
}
|
|
if(pxa255uartPrvFifoUsed(&uart->RX) && uart->cyclesSinceRecv >= 4 && (uart->IER & UART_IER_RAVIE) && !errorSet){
|
|
|
|
errorSet = true;
|
|
uart->IIR |= UART_IIR_RCV_TIMEOUT;
|
|
}
|
|
}
|
|
else{ //polling mode
|
|
|
|
UInt16 c = uart->receiveHolding;
|
|
|
|
if(uart->LSR & UART_LSR_DR){
|
|
|
|
pxa255uartPrvRecalcCharBits(uart, c);
|
|
|
|
if((c >> 8) && !errorSet && (uart->IER & UART_IER_RLSE)){
|
|
|
|
uart->IIR |= UART_IIR_RECV_ERR;
|
|
errorSet = true;
|
|
}
|
|
else if(!errorSet && (uart->IER & UART_IER_RAVIE)){
|
|
|
|
uart->IIR |= UART_IIR_RECV_DATA;
|
|
errorSet = true;
|
|
}
|
|
}
|
|
}
|
|
|
|
if(uart->LSR & UART_LSR_TDRQ && !errorSet && (uart->IER & UART_IER_TIE)){
|
|
|
|
errorSet = true;
|
|
uart->IIR |= UART_IIR_SEND_DATA;
|
|
}
|
|
|
|
if(!errorSet) uart->IIR |= UART_IIR_NOINT;
|
|
pxa255uartPrvIrq(uart, errorSet);
|
|
}
|