472 lines
14 KiB
C
472 lines
14 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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#include "drmP.h"
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#include "radeon_reg.h"
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#include "radeon.h"
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#include "atom.h"
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/*
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* BIOS.
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*/
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/* If you boot an IGP board with a discrete card as the primary,
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* the IGP rom is not accessible via the rom bar as the IGP rom is
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* part of the system bios. On boot, the system bios puts a
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* copy of the igp rom at the start of vram if a discrete card is
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* present.
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*/
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static bool igp_read_bios_from_vram(struct radeon_device *rdev)
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{
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uint8_t __iomem *bios;
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resource_size_t vram_base;
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resource_size_t size = 256 * 1024; /* ??? */
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rdev->bios = NULL;
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vram_base = drm_get_resource_start(rdev->ddev, 0);
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bios = ioremap(vram_base, size);
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if (!bios) {
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return false;
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}
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if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
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iounmap(bios);
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return false;
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}
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rdev->bios = kmalloc(size, GFP_KERNEL);
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if (rdev->bios == NULL) {
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iounmap(bios);
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return false;
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}
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memcpy(rdev->bios, bios, size);
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iounmap(bios);
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return true;
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}
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static bool radeon_read_bios(struct radeon_device *rdev)
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{
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uint8_t __iomem *bios;
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size_t size;
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rdev->bios = NULL;
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/* XXX: some cards may return 0 for rom size? ddx has a workaround */
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bios = pci_map_rom(rdev->pdev, &size);
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if (!bios) {
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return false;
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}
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if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
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// pci_unmap_rom(rdev->pdev, bios);
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return false;
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}
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rdev->bios = kmalloc(size, GFP_KERNEL);
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if (rdev->bios == NULL) {
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// pci_unmap_rom(rdev->pdev, bios);
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return false;
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}
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memcpy(rdev->bios, bios, size);
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// pci_unmap_rom(rdev->pdev, bios);
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return true;
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}
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/* ATRM is used to get the BIOS on the discrete cards in
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* dual-gpu systems.
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*/
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static bool radeon_atrm_get_bios(struct radeon_device *rdev)
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{
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int ret;
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int size = 64 * 1024;
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int i;
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if (!radeon_atrm_supported(rdev->pdev))
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return false;
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rdev->bios = kmalloc(size, GFP_KERNEL);
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if (!rdev->bios) {
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DRM_ERROR("Unable to allocate bios\n");
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return false;
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}
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for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {
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ret = radeon_atrm_get_bios_chunk(rdev->bios,
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(i * ATRM_BIOS_PAGE),
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ATRM_BIOS_PAGE);
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if (ret <= 0)
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break;
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}
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if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
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kfree(rdev->bios);
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return false;
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}
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return true;
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}
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static bool r700_read_disabled_bios(struct radeon_device *rdev)
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{
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uint32_t viph_control;
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uint32_t bus_cntl;
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uint32_t d1vga_control;
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uint32_t d2vga_control;
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uint32_t vga_render_control;
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uint32_t rom_cntl;
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uint32_t cg_spll_func_cntl = 0;
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uint32_t cg_spll_status;
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bool r;
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viph_control = RREG32(RADEON_VIPH_CONTROL);
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bus_cntl = RREG32(RADEON_BUS_CNTL);
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d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
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d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
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vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
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rom_cntl = RREG32(R600_ROM_CNTL);
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/* disable VIP */
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WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
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/* enable the rom */
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WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
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/* Disable VGA mode */
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WREG32(AVIVO_D1VGA_CONTROL,
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(d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
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AVIVO_DVGA_CONTROL_TIMING_SELECT)));
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WREG32(AVIVO_D2VGA_CONTROL,
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(d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
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AVIVO_DVGA_CONTROL_TIMING_SELECT)));
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WREG32(AVIVO_VGA_RENDER_CONTROL,
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(vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
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if (rdev->family == CHIP_RV730) {
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cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);
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/* enable bypass mode */
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WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl |
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R600_SPLL_BYPASS_EN));
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/* wait for SPLL_CHG_STATUS to change to 1 */
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cg_spll_status = 0;
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while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
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cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
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WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
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} else
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WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
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r = radeon_read_bios(rdev);
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/* restore regs */
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if (rdev->family == CHIP_RV730) {
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WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
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/* wait for SPLL_CHG_STATUS to change to 1 */
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cg_spll_status = 0;
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while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
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cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
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}
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WREG32(RADEON_VIPH_CONTROL, viph_control);
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WREG32(RADEON_BUS_CNTL, bus_cntl);
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WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
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WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
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WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
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WREG32(R600_ROM_CNTL, rom_cntl);
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return r;
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}
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static bool r600_read_disabled_bios(struct radeon_device *rdev)
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{
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uint32_t viph_control;
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uint32_t bus_cntl;
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uint32_t d1vga_control;
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uint32_t d2vga_control;
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uint32_t vga_render_control;
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uint32_t rom_cntl;
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uint32_t general_pwrmgt;
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uint32_t low_vid_lower_gpio_cntl;
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uint32_t medium_vid_lower_gpio_cntl;
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uint32_t high_vid_lower_gpio_cntl;
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uint32_t ctxsw_vid_lower_gpio_cntl;
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uint32_t lower_gpio_enable;
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bool r;
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viph_control = RREG32(RADEON_VIPH_CONTROL);
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bus_cntl = RREG32(RADEON_BUS_CNTL);
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d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
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d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
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vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
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rom_cntl = RREG32(R600_ROM_CNTL);
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general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);
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low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);
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medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
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high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);
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ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
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lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
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/* disable VIP */
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WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
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/* enable the rom */
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WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
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/* Disable VGA mode */
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WREG32(AVIVO_D1VGA_CONTROL,
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(d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
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AVIVO_DVGA_CONTROL_TIMING_SELECT)));
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WREG32(AVIVO_D2VGA_CONTROL,
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(d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
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AVIVO_DVGA_CONTROL_TIMING_SELECT)));
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WREG32(AVIVO_VGA_RENDER_CONTROL,
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(vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
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WREG32(R600_ROM_CNTL,
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((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) |
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(1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) |
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R600_SCK_OVERWRITE));
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WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));
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WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,
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(low_vid_lower_gpio_cntl & ~0x400));
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WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,
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(medium_vid_lower_gpio_cntl & ~0x400));
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WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,
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(high_vid_lower_gpio_cntl & ~0x400));
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WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,
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(ctxsw_vid_lower_gpio_cntl & ~0x400));
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WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));
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r = radeon_read_bios(rdev);
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/* restore regs */
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WREG32(RADEON_VIPH_CONTROL, viph_control);
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WREG32(RADEON_BUS_CNTL, bus_cntl);
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WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
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WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
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WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
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WREG32(R600_ROM_CNTL, rom_cntl);
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WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);
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WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);
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WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);
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WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
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WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
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WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
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return r;
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}
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static bool avivo_read_disabled_bios(struct radeon_device *rdev)
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{
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uint32_t seprom_cntl1;
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uint32_t viph_control;
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uint32_t bus_cntl;
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uint32_t d1vga_control;
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uint32_t d2vga_control;
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uint32_t vga_render_control;
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uint32_t gpiopad_a;
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uint32_t gpiopad_en;
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uint32_t gpiopad_mask;
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bool r;
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seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
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viph_control = RREG32(RADEON_VIPH_CONTROL);
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bus_cntl = RREG32(RADEON_BUS_CNTL);
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d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
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d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
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vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
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gpiopad_a = RREG32(RADEON_GPIOPAD_A);
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gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
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gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);
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WREG32(RADEON_SEPROM_CNTL1,
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((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
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(0xc << RADEON_SCK_PRESCALE_SHIFT)));
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WREG32(RADEON_GPIOPAD_A, 0);
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WREG32(RADEON_GPIOPAD_EN, 0);
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WREG32(RADEON_GPIOPAD_MASK, 0);
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/* disable VIP */
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WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
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/* enable the rom */
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WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
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/* Disable VGA mode */
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WREG32(AVIVO_D1VGA_CONTROL,
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(d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
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AVIVO_DVGA_CONTROL_TIMING_SELECT)));
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WREG32(AVIVO_D2VGA_CONTROL,
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(d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
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AVIVO_DVGA_CONTROL_TIMING_SELECT)));
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WREG32(AVIVO_VGA_RENDER_CONTROL,
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(vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
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r = radeon_read_bios(rdev);
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/* restore regs */
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WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
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WREG32(RADEON_VIPH_CONTROL, viph_control);
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WREG32(RADEON_BUS_CNTL, bus_cntl);
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WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
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WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
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WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
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WREG32(RADEON_GPIOPAD_A, gpiopad_a);
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WREG32(RADEON_GPIOPAD_EN, gpiopad_en);
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WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);
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return r;
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}
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static bool legacy_read_disabled_bios(struct radeon_device *rdev)
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{
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uint32_t seprom_cntl1;
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uint32_t viph_control;
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uint32_t bus_cntl;
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uint32_t crtc_gen_cntl;
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uint32_t crtc2_gen_cntl;
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uint32_t crtc_ext_cntl;
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uint32_t fp2_gen_cntl;
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bool r;
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seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
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viph_control = RREG32(RADEON_VIPH_CONTROL);
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bus_cntl = RREG32(RADEON_BUS_CNTL);
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crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
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crtc2_gen_cntl = 0;
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crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
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fp2_gen_cntl = 0;
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if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
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fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
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}
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if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
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crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
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}
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WREG32(RADEON_SEPROM_CNTL1,
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((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
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(0xc << RADEON_SCK_PRESCALE_SHIFT)));
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/* disable VIP */
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WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
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/* enable the rom */
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WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
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/* Turn off mem requests and CRTC for both controllers */
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WREG32(RADEON_CRTC_GEN_CNTL,
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((crtc_gen_cntl & ~RADEON_CRTC_EN) |
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(RADEON_CRTC_DISP_REQ_EN_B |
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RADEON_CRTC_EXT_DISP_EN)));
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if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
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WREG32(RADEON_CRTC2_GEN_CNTL,
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((crtc2_gen_cntl & ~RADEON_CRTC2_EN) |
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RADEON_CRTC2_DISP_REQ_EN_B));
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}
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/* Turn off CRTC */
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WREG32(RADEON_CRTC_EXT_CNTL,
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((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) |
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(RADEON_CRTC_SYNC_TRISTAT |
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RADEON_CRTC_DISPLAY_DIS)));
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if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
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WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
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}
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r = radeon_read_bios(rdev);
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/* restore regs */
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WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
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WREG32(RADEON_VIPH_CONTROL, viph_control);
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WREG32(RADEON_BUS_CNTL, bus_cntl);
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WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
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if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
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WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
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}
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WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
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if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
|
|
WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
|
|
}
|
|
return r;
|
|
}
|
|
|
|
static bool radeon_read_disabled_bios(struct radeon_device *rdev)
|
|
{
|
|
if (rdev->flags & RADEON_IS_IGP)
|
|
return igp_read_bios_from_vram(rdev);
|
|
else if (rdev->family >= CHIP_RV770)
|
|
return r700_read_disabled_bios(rdev);
|
|
else if (rdev->family >= CHIP_R600)
|
|
return r600_read_disabled_bios(rdev);
|
|
else if (rdev->family >= CHIP_RS600)
|
|
return avivo_read_disabled_bios(rdev);
|
|
else
|
|
return legacy_read_disabled_bios(rdev);
|
|
}
|
|
|
|
|
|
bool radeon_get_bios(struct radeon_device *rdev)
|
|
{
|
|
bool r;
|
|
uint16_t tmp;
|
|
|
|
r = radeon_atrm_get_bios(rdev);
|
|
if (r == false)
|
|
r = igp_read_bios_from_vram(rdev);
|
|
if (r == false)
|
|
r = radeon_read_bios(rdev);
|
|
if (r == false) {
|
|
r = radeon_read_disabled_bios(rdev);
|
|
}
|
|
if (r == false || rdev->bios == NULL) {
|
|
DRM_ERROR("Unable to locate a BIOS ROM\n");
|
|
rdev->bios = NULL;
|
|
return false;
|
|
}
|
|
if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
|
|
printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]);
|
|
goto free_bios;
|
|
}
|
|
|
|
tmp = RBIOS16(0x18);
|
|
if (RBIOS8(tmp + 0x14) != 0x0) {
|
|
DRM_INFO("Not an x86 BIOS ROM, not using.\n");
|
|
goto free_bios;
|
|
}
|
|
|
|
rdev->bios_header_start = RBIOS16(0x48);
|
|
if (!rdev->bios_header_start) {
|
|
goto free_bios;
|
|
}
|
|
tmp = rdev->bios_header_start + 4;
|
|
if (!memcmp(rdev->bios + tmp, "ATOM", 4) ||
|
|
!memcmp(rdev->bios + tmp, "MOTA", 4)) {
|
|
rdev->is_atom_bios = true;
|
|
} else {
|
|
rdev->is_atom_bios = false;
|
|
}
|
|
|
|
DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM");
|
|
return true;
|
|
free_bios:
|
|
kfree(rdev->bios);
|
|
rdev->bios = NULL;
|
|
return false;
|
|
}
|