463 lines
11 KiB
C++
463 lines
11 KiB
C++
// DGen v1.10+
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// Megadrive C++ module saving and loading
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#include <stdio.h>
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#include <string.h>
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#include <stdlib.h>
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#include <stdint.h>
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#include "md.h"
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#include "system.h"
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void md::m68k_state_dump()
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{
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/*
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32 and 16-bit values must be stored LSB first even though M68K is
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big-endian for compatibility with other emulators.
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*/
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switch (cpu_emu) {
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#ifdef WITH_MUSA
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case CPU_EMU_MUSA:
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if (md_set_musa(true))
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md_set_musa_sync(false);
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md_set_musa(false);
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break;
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#endif
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#ifdef WITH_STAR
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case CPU_EMU_STAR:
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if (md_set_star(true))
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md_set_star_sync(false);
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md_set_star(false);
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break;
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#endif
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#ifdef WITH_CYCLONE
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case CPU_EMU_CYCLONE:
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if (md_set_cyclone(true))
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md_set_cyclone_sync(false);
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md_set_cyclone(false);
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break;
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#endif
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default:
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break;
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}
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}
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void md::m68k_state_restore()
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{
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/* 32 and 16-bit values are stored LSB first. */
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switch (cpu_emu) {
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#ifdef WITH_MUSA
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case CPU_EMU_MUSA:
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if (md_set_musa(true))
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md_set_musa_sync(true);
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md_set_musa(false);
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break;
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#endif
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#ifdef WITH_STAR
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case CPU_EMU_STAR:
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if (md_set_star(true))
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md_set_star_sync(true);
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md_set_star(false);
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break;
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#endif
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#ifdef WITH_CYCLONE
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case CPU_EMU_CYCLONE:
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if (md_set_cyclone(true))
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md_set_cyclone_sync(true);
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md_set_cyclone(false);
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break;
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#endif
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default:
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break;
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}
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}
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void md::z80_state_dump()
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{
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/* 16-bit values must be stored LSB first. */
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z80_state.irq_asserted = z80_st_irq;
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z80_state.irq_vector = z80_irq_vector;
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switch (z80_core) {
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#ifdef WITH_CZ80
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case Z80_CORE_CZ80:
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if (md_set_cz80(true))
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md_set_cz80_sync(false);
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md_set_cz80(false);
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break;
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#endif
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#ifdef WITH_MZ80
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case Z80_CORE_MZ80:
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if (md_set_mz80(true))
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md_set_mz80_sync(false);
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md_set_mz80(false);
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break;
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#endif
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#ifdef WITH_DRZ80
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case Z80_CORE_DRZ80:
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if (md_set_drz80(true))
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md_set_drz80_sync(false);
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md_set_drz80(false);
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break;
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#endif
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default:
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break;
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}
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}
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void md::z80_state_restore()
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{
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/* 16-bit values are stored LSB first. */
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switch (z80_core) {
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#ifdef WITH_CZ80
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case Z80_CORE_CZ80:
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if (md_set_cz80(true))
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md_set_cz80_sync(true);
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md_set_cz80(false);
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break;
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#endif
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#ifdef WITH_MZ80
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case Z80_CORE_MZ80:
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if (md_set_mz80(true))
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md_set_mz80_sync(true);
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md_set_mz80(false);
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break;
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#endif
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#ifdef WITH_DRZ80
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case Z80_CORE_DRZ80:
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if (md_set_drz80(true))
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md_set_drz80_sync(true);
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md_set_drz80(false);
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break;
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#endif
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default:
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break;
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}
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if (z80_state.irq_asserted)
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z80_irq(z80_state.irq_vector);
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else
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z80_irq_clear();
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}
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/*
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gs0 genecyst save file INfo
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GST\0 to start with
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80-9f = d0-d7 almost certain
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a0-bf = a0-a7 almost certain
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c8 = pc fairly certain
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d0 = sr fairly certain
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112 Start of cram len 0x80
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192 Start of vsram len 0x50
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1e2-474 UNKNOWN sound info?
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Start of z80 ram at 474 (they store 2000)
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Start of RAM at 2478 almost certain (BYTE SWAPPED)
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Start of VRAM at 12478
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end of VRAM
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*/
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/*
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2011-11-05 - Adapted from Gens' genecyst_save_file_format.txt:
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Range Size Description
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----------- ----- -----------
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00000-00002 3 "GST"
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00003-00004 2 "\x40\xe0" (Gens and new DGen format)
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00006-00007 2 "\xe0\x40" (old DGen format)
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00040-00043 4 Last VDP control data written
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00044-00044 1 Second write flag
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00045-00045 1 DMA fill flag
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00048-0004B 4 VDP write address
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00050-00050 1 Version
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00051-00051 1 Emulator ID
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00052-00052 1 System ID
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00060-0006F 16 PSG registers
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00080-000D9 90 M68K registers
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000FA-00111 24 VDP registers
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00112-00191 128 Color RAM
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00192-001E1 80 Vertical scroll RAM
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001E2-001E2 1 YM2612 part I address register (DGen)
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001E3-001E3 1 YM2612 part II address register (DGen)
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001E4-003E3 512 YM2612 registers
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00404-00437 52 Z80 registers
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00438-0043F 8 Z80 state
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00474-02473 8192 Z80 RAM
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02478-12477 65536 68K RAM
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12478-22477 65536 Video RAM
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M68K registers (stored little-endian for compatibility)
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--------------
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00080-0009F : D0-D7
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000A0-000BF : A0-A7
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000C8 : PC
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000D0 : SR
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000D2 : USP
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000D6 : SSP
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Z80 registers (little-endian)
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-------------
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00404 : AF
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00408 : BC
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0040C : DE
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00410 : HL
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00414 : IX
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00418 : IY
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0041C : PC
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00420 : SP
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00424 : AF'
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00428 : BC'
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0042C : DE'
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00430 : HL'
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00434 : I
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00435 : R (DGen)
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00436 : x x x x x IFF1 x IFF2 (Gens v5)
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00437 : IM (DGen)
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Z80 State
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---------
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00438 : Z80 RESET
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00439 : Z80 BUSREQ
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0043A : Unknown
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0043B : Unknown
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0043C : Z80 BANK (DWORD)
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Gens and Kega ADD
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-----------------
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00040 : last VDP Control data written (DWORD)
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00044 : second write flag (1 for second write)
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00045 : DMA Fill flag (1 mean next data write will cause a DMA fill)
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00048 : VDP write address (DWORD)
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00050 : Version (Genecyst=0; Kega=5; Gens=5; DGen=5)
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00051 : Emulator ID (Genecyst=0; Kega=0; Gens=1; DGen=9)
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00052 : System ID (Genesis=0; SegaCD=1; 32X=2; SegaCD32X=3)
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00060-0007F : PSG registers (DWORDs, little endian).
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*/
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static void *swap16cpy(void *dest, const void *src, size_t n)
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{
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size_t i;
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for (i = 0; (i != (n & ~1)); ++i)
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((uint8_t *)dest)[(i ^ 1)] = ((uint8_t *)src)[i];
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((uint8_t *)dest)[i] = ((uint8_t *)src)[i];
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return dest;
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}
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int md::import_gst(FILE *hand)
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{
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uint8_t (*buf)[0x22478] =
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(uint8_t (*)[sizeof(*buf)])malloc(sizeof(*buf));
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uint8_t *p;
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uint8_t *q;
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size_t i;
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uint32_t tmp;
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if ((buf == NULL) ||
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(fread((*buf), sizeof(*buf), 1, hand) != 1) ||
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/* GST header */
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((memcmp((*buf), "GST\x0\x0\0\xe0\x40", 8) != 0) &&
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(memcmp((*buf), "GST\x40\xe0", 5) != 0))) {
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fprintf(stderr,
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"%s: error: invalid save file header.\n",
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__func__);
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free(buf);
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return -1;
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}
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p = &(*buf)[0x50];
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if (p[2] != 0) {
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fprintf(stderr,
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"%s: error: this is not a Genesis/Mega Drive"
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" save file.\n",
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__func__);
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free(buf);
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return -1;
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}
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if (p[1] != 9) {
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fprintf(stderr,
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"%s: warning: save file was probably not generated by"
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" DGen/SDL.\n",
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__func__);
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}
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else if (p[0] != 5)
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fprintf(stderr,
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"%s: warning: unknown save file version.\n",
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__func__);
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/* Reset console first. */
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reset();
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/* FIXME: VDP stuff */
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/* PSG registers (8x16-bit, 16 bytes) */
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SN76496_restore(0, &(*buf)[0x60]);
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/* M68K registers (19x32-bit, 1x16-bit, 90 bytes (padding: 12)) */
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p = &(*buf)[0x80];
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q = &(*buf)[0xa0];
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for (i = 0; (i != 8); ++i, p += 4, q += 4) {
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memcpy(&m68k_state.d[i], p, 4);
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memcpy(&m68k_state.a[i], q, 4);
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}
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memcpy(&m68k_state.pc, &(*buf)[0xc8], 4);
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memcpy(&m68k_state.sr, &(*buf)[0xd0], 2);
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/*
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FIXME?
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memcpy(&m68k_state.usp, &(*buf)[0xd2], 4);
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memcpy(&m68k_state.ssp, &(*buf)[0xd6], 4);
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*/
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m68k_state_restore();
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/* VDP registers (24x8-bit VDP registers, not sizeof(vdp.reg)) */
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memcpy(vdp.reg, &(*buf)[0xfa], 0x18);
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memset(&vdp.reg[0x18], 0, (sizeof(vdp.reg) - 0x18));
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/* CRAM (64x16-bit registers, 128 bytes), swapped */
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swap16cpy(vdp.cram, &(*buf)[0x112], 0x80);
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/* VSRAM (40x16-bit words, 80 bytes), swapped */
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swap16cpy(vdp.vsram, &(*buf)[0x192], 0x50);
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/* YM2612 registers */
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p = &(*buf)[0x1e2];
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fm_sel[0] = p[0];
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fm_sel[1] = p[1];
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p = &(*buf)[0x1e4];
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YM2612_restore(0, p);
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fm_reg[0][0x24] = p[0x24];
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fm_reg[0][0x25] = p[0x25];
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fm_reg[0][0x26] = p[0x26];
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fm_reg[0][0x27] = p[0x27];
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dac_data[0] = p[0x2a];
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dac_enabled = (p[0x2b] >> 7);
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memset(fm_ticker, 0, sizeof(fm_ticker));
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/* Z80 registers (12x16-bit and 4x8-bit, 52 bytes (padding: 24)) */
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p = &(*buf)[0x404];
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for (i = 0; (i != 2); ++i, p = &(*buf)[0x424]) {
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memcpy(&z80_state.alt[i].fa, &p[0x0], 2);
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memcpy(&z80_state.alt[i].cb, &p[0x4], 2);
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memcpy(&z80_state.alt[i].ed, &p[0x8], 2);
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memcpy(&z80_state.alt[i].lh, &p[0xc], 2);
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}
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p = &(*buf)[0x414];
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memcpy(&z80_state.ix, &p[0x0], 2);
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memcpy(&z80_state.iy, &p[0x4], 2);
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memcpy(&z80_state.pc, &p[0x8], 2);
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memcpy(&z80_state.sp, &p[0xc], 2);
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p = &(*buf)[0x434];
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z80_state.i = p[0];
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z80_state.r = p[1];
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z80_state.iff = ((p[2] << 1) | p[2]); /* IFF2 = IFF1 */
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z80_state.im = ((p[3] == 0) ? 1 : p[3]);
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z80_state_restore();
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/* Z80 state (8 bytes) */
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p = &(*buf)[0x438];
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z80_st_reset = !p[0]; /* BUS RESET state */
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if (z80_st_reset) {
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z80_reset();
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fm_reset();
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}
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z80_st_busreq = (p[1] & 1); /* BUSREQ state */
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memcpy(&tmp, &(*buf)[0x43c], 4);
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z80_bank68k = le2h32(tmp);
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/* Z80 RAM (8192 bytes) */
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memcpy(z80ram, &(*buf)[0x474], 0x2000);
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/* RAM (65536 bytes), swapped */
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swap16cpy(ram, &(*buf)[0x2478], 0x10000);
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/* VRAM (65536 bytes) */
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memcpy(vdp.vram, &(*buf)[0x12478], 0x10000);
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/* Mark everything as changed */
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memset(vdp.dirt, 0xff, 0x35);
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free(buf);
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return 0;
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}
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int md::export_gst(FILE *hand)
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{
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uint8_t (*buf)[0x22478] =
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(uint8_t (*)[sizeof(*buf)])calloc(1, sizeof(*buf));
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uint8_t *p;
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uint8_t *q;
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size_t i;
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uint32_t tmp;
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if (buf == NULL)
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return -1;
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/* GST header */
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memcpy((*buf), "GST\x40\xe0", 5);
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/* FIXME: VDP stuff */
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/* Version */
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(*buf)[0x50] = 5;
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/* Emulator ID */
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(*buf)[0x51] = 9;
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/* System ID */
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(*buf)[0x52] = 0;
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/* PSG registers (8x16-bit, 16 bytes) */
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SN76496_dump(0, &(*buf)[0x60]);
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/* M68K registers (19x32-bit, 1x16-bit, 90 bytes (padding: 12)) */
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m68k_state_dump();
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p = &(*buf)[0x80];
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q = &(*buf)[0xa0];
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for (i = 0; (i != 8); ++i, p += 4, q += 4) {
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memcpy(p, &m68k_state.d[i], 4);
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memcpy(q, &m68k_state.a[i], 4);
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}
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memcpy(&(*buf)[0xc8], &m68k_state.pc, 4);
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memcpy(&(*buf)[0xd0], &m68k_state.sr, 2);
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/*
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FIXME?
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memcpy(&(*buf)[0xd2], &m68k_state.usp, 4);
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memcpy(&(*buf)[0xd6], &m68k_state.ssp, 4);
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*/
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/* VDP registers (24x8-bit VDP registers, not sizeof(vdp.reg)) */
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memcpy(&(*buf)[0xfa], vdp.reg, 0x18);
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/* CRAM (64x16-bit registers, 128 bytes), swapped */
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swap16cpy(&(*buf)[0x112], vdp.cram, 0x80);
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/* VSRAM (40x16-bit words, 80 bytes), swapped */
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swap16cpy(&(*buf)[0x192], vdp.vsram, 0x50);
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/* YM2612 registers */
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p = &(*buf)[0x1e2];
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p[0] = fm_sel[0];
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p[1] = fm_sel[1];
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p = &(*buf)[0x1e4];
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YM2612_dump(0, p);
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p[0x24] = fm_reg[0][0x24];
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p[0x25] = fm_reg[0][0x25];
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p[0x26] = fm_reg[0][0x26];
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p[0x27] = fm_reg[0][0x27];
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p[0x2a] = 0xff;
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p[0x2b] = (dac_enabled << 7);
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/* Z80 registers (12x16-bit and 4x8-bit, 52 bytes (padding: 24)) */
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z80_state_dump();
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p = &(*buf)[0x404];
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for (i = 0; (i != 2); ++i, p = &(*buf)[0x424]) {
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memcpy(&p[0x0], &z80_state.alt[i].fa, 2);
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memcpy(&p[0x4], &z80_state.alt[i].cb, 2);
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memcpy(&p[0x8], &z80_state.alt[i].ed, 2);
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memcpy(&p[0xc], &z80_state.alt[i].lh, 2);
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}
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p = &(*buf)[0x414];
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memcpy(&p[0x0], &z80_state.ix, 2);
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memcpy(&p[0x4], &z80_state.iy, 2);
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memcpy(&p[0x8], &z80_state.pc, 2);
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memcpy(&p[0xc], &z80_state.sp, 2);
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p = &(*buf)[0x434];
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p[0] = z80_state.i;
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p[1] = z80_state.r;
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p[2] = ((z80_state.iff >> 1) | z80_state.iff);
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p[3] = z80_state.im;
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/* Z80 state (8 bytes) */
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p = &(*buf)[0x438];
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p[0] = !z80_st_reset;
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p[1] = z80_st_busreq;
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tmp = h2le32(z80_bank68k);
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memcpy(&(*buf)[0x43c], &tmp, 4);
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/* Z80 RAM (8192 bytes) */
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memcpy(&(*buf)[0x474], z80ram, 0x2000);
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/* RAM (65536 bytes), swapped */
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swap16cpy(&(*buf)[0x2478], ram, 0x10000);
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/* VRAM (65536 bytes) */
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memcpy(&(*buf)[0x12478], vdp.vram, 0x10000);
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/* Output */
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i = fwrite((*buf), sizeof(*buf), 1, hand);
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free(buf);
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if (i != 1)
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return -1;
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return 0;
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}
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