809 lines
22 KiB
C
809 lines
22 KiB
C
//#include "../bitmap.h"
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#include <memory.h>
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#include <malloc.h>
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#include "sna.h"
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#include <pixlib2.h>
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static struct sna_fb sna_fb;
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static struct kgem_bo *mask_bo;
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static int mask_width, mask_height;
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typedef struct __attribute__((packed))
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{
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unsigned handle;
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unsigned io_code;
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void *input;
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int inp_size;
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void *output;
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int out_size;
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}ioctl_t;
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static int call_service(ioctl_t *io)
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{
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int retval;
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asm volatile("int $0x40"
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:"=a"(retval)
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:"a"(68),"b"(17),"c"(io)
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:"memory","cc");
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return retval;
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};
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static inline void get_proc_info(char *info)
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{
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__asm__ __volatile__(
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"int $0x40"
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:
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:"a"(9), "b"(info), "c"(-1));
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}
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const struct intel_device_info *
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intel_detect_chipset(struct pci_device *pci);
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//struct kgem_bo *create_bo(bitmap_t *bitmap);
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static bool sna_solid_cache_init(struct sna *sna);
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struct sna *sna_device;
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static void no_render_reset(struct sna *sna)
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{
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(void)sna;
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}
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void no_render_init(struct sna *sna)
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{
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struct sna_render *render = &sna->render;
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memset (render,0, sizeof (*render));
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render->prefer_gpu = PREFER_GPU_BLT;
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render->vertices = render->vertex_data;
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render->vertex_size = ARRAY_SIZE(render->vertex_data);
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// render->composite = no_render_composite;
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// render->copy_boxes = no_render_copy_boxes;
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// render->copy = no_render_copy;
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// render->fill_boxes = no_render_fill_boxes;
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// render->fill = no_render_fill;
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// render->fill_one = no_render_fill_one;
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// render->clear = no_render_clear;
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render->reset = no_render_reset;
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// render->flush = no_render_flush;
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// render->fini = no_render_fini;
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// sna->kgem.context_switch = no_render_context_switch;
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// sna->kgem.retire = no_render_retire;
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if (sna->kgem.gen >= 60)
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sna->kgem.ring = KGEM_RENDER;
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sna_vertex_init(sna);
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}
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void sna_vertex_init(struct sna *sna)
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{
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// pthread_mutex_init(&sna->render.lock, NULL);
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// pthread_cond_init(&sna->render.wait, NULL);
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sna->render.active = 0;
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}
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int sna_accel_init(struct sna *sna)
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{
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const char *backend;
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// list_init(&sna->deferred_free);
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// list_init(&sna->dirty_pixmaps);
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// list_init(&sna->active_pixmaps);
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// list_init(&sna->inactive_clock[0]);
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// list_init(&sna->inactive_clock[1]);
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// sna_accel_install_timers(sna);
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backend = "no";
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no_render_init(sna);
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if (sna->info->gen >= 0100) {
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} else if (sna->info->gen >= 070) {
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if (gen7_render_init(sna))
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backend = "IvyBridge";
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} else if (sna->info->gen >= 060) {
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if (gen6_render_init(sna))
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backend = "SandyBridge";
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} else if (sna->info->gen >= 050) {
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if (gen5_render_init(sna))
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backend = "Ironlake";
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} else if (sna->info->gen >= 040) {
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if (gen4_render_init(sna))
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backend = "Broadwater/Crestline";
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} else if (sna->info->gen >= 030) {
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if (gen3_render_init(sna))
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backend = "gen3";
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}
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DBG(("%s(backend=%s, prefer_gpu=%x)\n",
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__FUNCTION__, backend, sna->render.prefer_gpu));
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kgem_reset(&sna->kgem);
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// if (!sna_solid_cache_init(sna))
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// return false;
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sna_device = sna;
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return kgem_init_fb(&sna->kgem, &sna_fb);
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}
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int sna_init(uint32_t service)
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{
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ioctl_t io;
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static struct pci_device device;
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struct sna *sna;
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DBG(("%s\n", __FUNCTION__));
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sna = malloc(sizeof(*sna));
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if (sna == NULL)
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return 0;
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memset(sna, 0, sizeof(*sna));
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io.handle = service;
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io.io_code = SRV_GET_PCI_INFO;
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io.input = &device;
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io.inp_size = sizeof(device);
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io.output = NULL;
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io.out_size = 0;
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if (call_service(&io)!=0)
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{
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free(sna);
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return 0;
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};
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sna->PciInfo = &device;
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sna->info = intel_detect_chipset(sna->PciInfo);
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kgem_init(&sna->kgem, service, sna->PciInfo, sna->info->gen);
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/*
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if (!xf86ReturnOptValBool(sna->Options,
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OPTION_RELAXED_FENCING,
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sna->kgem.has_relaxed_fencing)) {
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xf86DrvMsg(scrn->scrnIndex,
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sna->kgem.has_relaxed_fencing ? X_CONFIG : X_PROBED,
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"Disabling use of relaxed fencing\n");
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sna->kgem.has_relaxed_fencing = 0;
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}
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if (!xf86ReturnOptValBool(sna->Options,
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OPTION_VMAP,
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sna->kgem.has_vmap)) {
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xf86DrvMsg(scrn->scrnIndex,
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sna->kgem.has_vmap ? X_CONFIG : X_PROBED,
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"Disabling use of vmap\n");
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sna->kgem.has_vmap = 0;
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}
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*/
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/* Disable tiling by default */
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sna->tiling = SNA_TILING_DISABLE;
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/* Default fail-safe value of 75 Hz */
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// sna->vblank_interval = 1000 * 1000 * 1000 / 75;
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sna->flags = 0;
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sna_accel_init(sna);
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delay(10);
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return sna->render.caps;
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}
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void sna_fini()
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{
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if( sna_device )
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{
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sna_device->render.fini(sna_device);
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kgem_bo_destroy(&sna_device->kgem, mask_bo);
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kgem_close_batches(&sna_device->kgem);
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kgem_cleanup_cache(&sna_device->kgem);
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};
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}
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#if 0
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static bool sna_solid_cache_init(struct sna *sna)
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{
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struct sna_solid_cache *cache = &sna->render.solid_cache;
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DBG(("%s\n", __FUNCTION__));
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cache->cache_bo =
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kgem_create_linear(&sna->kgem, sizeof(cache->color));
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if (!cache->cache_bo)
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return FALSE;
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/*
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* Initialise [0] with white since it is very common and filling the
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* zeroth slot simplifies some of the checks.
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*/
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cache->color[0] = 0xffffffff;
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cache->bo[0] = kgem_create_proxy(cache->cache_bo, 0, sizeof(uint32_t));
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cache->bo[0]->pitch = 4;
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cache->dirty = 1;
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cache->size = 1;
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cache->last = 0;
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return TRUE;
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}
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void
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sna_render_flush_solid(struct sna *sna)
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{
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struct sna_solid_cache *cache = &sna->render.solid_cache;
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DBG(("sna_render_flush_solid(size=%d)\n", cache->size));
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assert(cache->dirty);
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assert(cache->size);
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kgem_bo_write(&sna->kgem, cache->cache_bo,
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cache->color, cache->size*sizeof(uint32_t));
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cache->dirty = 0;
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cache->last = 0;
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}
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static void
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sna_render_finish_solid(struct sna *sna, bool force)
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{
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struct sna_solid_cache *cache = &sna->render.solid_cache;
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int i;
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DBG(("sna_render_finish_solid(force=%d, domain=%d, busy=%d, dirty=%d)\n",
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force, cache->cache_bo->domain, cache->cache_bo->rq != NULL, cache->dirty));
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if (!force && cache->cache_bo->domain != DOMAIN_GPU)
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return;
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if (cache->dirty)
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sna_render_flush_solid(sna);
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for (i = 0; i < cache->size; i++) {
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if (cache->bo[i] == NULL)
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continue;
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kgem_bo_destroy(&sna->kgem, cache->bo[i]);
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cache->bo[i] = NULL;
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}
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kgem_bo_destroy(&sna->kgem, cache->cache_bo);
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DBG(("sna_render_finish_solid reset\n"));
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cache->cache_bo = kgem_create_linear(&sna->kgem, sizeof(cache->color));
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cache->bo[0] = kgem_create_proxy(cache->cache_bo, 0, sizeof(uint32_t));
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cache->bo[0]->pitch = 4;
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if (force)
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cache->size = 1;
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}
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struct kgem_bo *
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sna_render_get_solid(struct sna *sna, uint32_t color)
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{
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struct sna_solid_cache *cache = &sna->render.solid_cache;
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int i;
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DBG(("%s: %08x\n", __FUNCTION__, color));
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// if ((color & 0xffffff) == 0) /* alpha only */
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// return kgem_bo_reference(sna->render.alpha_cache.bo[color>>24]);
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if (color == 0xffffffff) {
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DBG(("%s(white)\n", __FUNCTION__));
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return kgem_bo_reference(cache->bo[0]);
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}
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if (cache->color[cache->last] == color) {
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DBG(("sna_render_get_solid(%d) = %x (last)\n",
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cache->last, color));
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return kgem_bo_reference(cache->bo[cache->last]);
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}
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for (i = 1; i < cache->size; i++) {
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if (cache->color[i] == color) {
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if (cache->bo[i] == NULL) {
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DBG(("sna_render_get_solid(%d) = %x (recreate)\n",
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i, color));
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goto create;
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} else {
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DBG(("sna_render_get_solid(%d) = %x (old)\n",
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i, color));
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goto done;
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}
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}
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}
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sna_render_finish_solid(sna, i == ARRAY_SIZE(cache->color));
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i = cache->size++;
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cache->color[i] = color;
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cache->dirty = 1;
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DBG(("sna_render_get_solid(%d) = %x (new)\n", i, color));
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create:
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cache->bo[i] = kgem_create_proxy(cache->cache_bo,
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i*sizeof(uint32_t), sizeof(uint32_t));
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cache->bo[i]->pitch = 4;
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done:
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cache->last = i;
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return kgem_bo_reference(cache->bo[i]);
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}
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int sna_blit_copy(bitmap_t *src_bitmap, int dst_x, int dst_y,
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int w, int h, int src_x, int src_y)
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{
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struct sna_copy_op copy;
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struct _Pixmap src, dst;
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struct kgem_bo *src_bo;
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char proc_info[1024];
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int winx, winy;
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get_proc_info(proc_info);
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winx = *(uint32_t*)(proc_info+34);
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winy = *(uint32_t*)(proc_info+38);
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memset(&src, 0, sizeof(src));
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memset(&dst, 0, sizeof(dst));
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src.drawable.bitsPerPixel = 32;
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src.drawable.width = src_bitmap->width;
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src.drawable.height = src_bitmap->height;
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dst.drawable.bitsPerPixel = 32;
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dst.drawable.width = sna_fb.width;
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dst.drawable.height = sna_fb.height;
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memset(©, 0, sizeof(copy));
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src_bo = (struct kgem_bo*)src_bitmap->handle;
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if( sna_device->render.copy(sna_device, GXcopy,
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&src, src_bo,
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&dst, sna_fb.fb_bo, ©) )
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{
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copy.blt(sna_device, ©, src_x, src_y, w, h, winx+dst_x, winy+dst_y);
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copy.done(sna_device, ©);
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}
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kgem_submit(&sna_device->kgem);
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// __asm__ __volatile__("int3");
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};
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#endif
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int sna_create_bitmap(bitmap_t *bitmap)
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{
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struct kgem_bo *bo;
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bo = kgem_create_2d(&sna_device->kgem, bitmap->width, bitmap->height,
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32,I915_TILING_NONE, CREATE_CPU_MAP);
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if(bo == NULL)
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goto err_1;
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void *map = kgem_bo_map(&sna_device->kgem, bo);
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if(map == NULL)
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goto err_2;
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bitmap->handle = (uint32_t)bo;
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bitmap->pitch = bo->pitch;
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bitmap->data = map;
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return 0;
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err_2:
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kgem_bo_destroy(&sna_device->kgem, bo);
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err_1:
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return -1;
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};
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void sna_destroy_bitmap(bitmap_t *bitmap)
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{
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struct kgem_bo *bo;
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bo = (struct kgem_bo *)bitmap->handle;
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kgem_bo_destroy(&sna_device->kgem, bo);
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};
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void sna_lock_bitmap(bitmap_t *bitmap)
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{
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struct kgem_bo *bo;
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bo = (struct kgem_bo *)bitmap->handle;
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kgem_bo_sync__cpu(&sna_device->kgem, bo);
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};
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int sna_create_mask()
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{
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struct kgem_bo *bo;
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int width, height;
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int i;
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// printf("%s width %d height %d\n", __FUNCTION__, sna_fb.width, sna_fb.height);
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bo = kgem_create_2d(&sna_device->kgem, sna_fb.width, sna_fb.height,
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8,I915_TILING_NONE, CREATE_CPU_MAP);
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if(bo == NULL)
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goto err_1;
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int *map = kgem_bo_map(&sna_device->kgem, bo);
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if(map == NULL)
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goto err_2;
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memset(map, 0, bo->pitch * height);
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mask_bo = bo;
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mask_width = width;
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mask_height = height;
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return 0;
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err_2:
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kgem_bo_destroy(&sna_device->kgem, bo);
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err_1:
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return -1;
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};
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bool
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gen6_composite(struct sna *sna,
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uint8_t op,
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PixmapPtr src, struct kgem_bo *src_bo,
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PixmapPtr mask,struct kgem_bo *mask_bo,
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PixmapPtr dst, struct kgem_bo *dst_bo,
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int32_t src_x, int32_t src_y,
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int32_t msk_x, int32_t msk_y,
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int32_t dst_x, int32_t dst_y,
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int32_t width, int32_t height,
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struct sna_composite_op *tmp);
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#define MAP(ptr) ((void*)((uintptr_t)(ptr) & ~3))
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int sna_blit_tex(bitmap_t *src_bitmap, int dst_x, int dst_y,
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int w, int h, int src_x, int src_y)
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{
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// box.x1 = dst_x;
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// box.y1 = dst_y;
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// box.x2 = dst_x+w;
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// box.y2 = dst_y+h;
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// cop.box(sna_device, &cop, &box);
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struct drm_i915_mask_update update;
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struct sna_composite_op composite;
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struct _Pixmap src, dst, mask;
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struct kgem_bo *src_bo;
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char proc_info[1024];
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int winx, winy, winw, winh;
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get_proc_info(proc_info);
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winx = *(uint32_t*)(proc_info+34);
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winy = *(uint32_t*)(proc_info+38);
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winw = *(uint32_t*)(proc_info+42)+1;
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winh = *(uint32_t*)(proc_info+46)+1;
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VG_CLEAR(update);
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update.handle = mask_bo->handle;
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// update.bo_size = __kgem_bo_size(mask_bo);
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// update.bo_pitch = mask_bo->pitch;
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update.bo_map = (__u32)MAP(mask_bo->map);
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drmIoctl(sna_device->kgem.fd, SRV_MASK_UPDATE, &update);
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mask_bo->pitch = update.bo_pitch;
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memset(&src, 0, sizeof(src));
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memset(&dst, 0, sizeof(dst));
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memset(&mask, 0, sizeof(dst));
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src.drawable.bitsPerPixel = 32;
|
|
src.drawable.width = src_bitmap->width;
|
|
src.drawable.height = src_bitmap->height;
|
|
|
|
dst.drawable.bitsPerPixel = 32;
|
|
dst.drawable.width = sna_fb.width;
|
|
dst.drawable.height = sna_fb.height;
|
|
|
|
mask.drawable.bitsPerPixel = 8;
|
|
mask.drawable.width = update.width;
|
|
mask.drawable.height = update.height;
|
|
|
|
memset(&composite, 0, sizeof(composite));
|
|
|
|
src_bo = (struct kgem_bo*)src_bitmap->handle;
|
|
|
|
|
|
if( sna_device->render.blit_tex(sna_device, PictOpSrc,
|
|
&src, src_bo,
|
|
&mask, mask_bo,
|
|
&dst, sna_fb.fb_bo,
|
|
src_x, src_y,
|
|
dst_x, dst_y,
|
|
winx+dst_x, winy+dst_y,
|
|
w, h,
|
|
&composite) )
|
|
{
|
|
struct sna_composite_rectangles r;
|
|
|
|
r.src.x = src_x;
|
|
r.src.y = src_y;
|
|
r.mask.x = dst_x;
|
|
r.mask.y = dst_y;
|
|
r.dst.x = winx+dst_x;
|
|
r.dst.y = winy+dst_y;
|
|
r.width = w;
|
|
r.height = h;
|
|
|
|
composite.blt(sna_device, &composite, &r);
|
|
composite.done(sna_device, &composite);
|
|
};
|
|
|
|
kgem_submit(&sna_device->kgem);
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
static const struct intel_device_info intel_generic_info = {
|
|
.gen = -1,
|
|
};
|
|
|
|
static const struct intel_device_info intel_i915_info = {
|
|
.gen = 030,
|
|
};
|
|
static const struct intel_device_info intel_i945_info = {
|
|
.gen = 031,
|
|
};
|
|
|
|
static const struct intel_device_info intel_g33_info = {
|
|
.gen = 033,
|
|
};
|
|
|
|
static const struct intel_device_info intel_i965_info = {
|
|
.gen = 040,
|
|
};
|
|
|
|
static const struct intel_device_info intel_g4x_info = {
|
|
.gen = 045,
|
|
};
|
|
|
|
static const struct intel_device_info intel_ironlake_info = {
|
|
.gen = 050,
|
|
};
|
|
|
|
static const struct intel_device_info intel_sandybridge_info = {
|
|
.gen = 060,
|
|
};
|
|
|
|
static const struct intel_device_info intel_ivybridge_info = {
|
|
.gen = 070,
|
|
};
|
|
|
|
static const struct intel_device_info intel_valleyview_info = {
|
|
.gen = 071,
|
|
};
|
|
|
|
static const struct intel_device_info intel_haswell_info = {
|
|
.gen = 075,
|
|
};
|
|
|
|
#define INTEL_DEVICE_MATCH(d,i) \
|
|
{ 0x8086, (d), PCI_MATCH_ANY, PCI_MATCH_ANY, 0x3 << 16, 0xff << 16, (intptr_t)(i) }
|
|
|
|
|
|
static const struct pci_id_match intel_device_match[] = {
|
|
|
|
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_I915_G, &intel_i915_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_E7221_G, &intel_i915_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_I915_GM, &intel_i915_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_I945_G, &intel_i945_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_I945_GM, &intel_i945_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_I945_GME, &intel_i945_info ),
|
|
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_PINEVIEW_M, &intel_g33_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_PINEVIEW_G, &intel_g33_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_G33_G, &intel_g33_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_Q33_G, &intel_g33_info ),
|
|
/* Another marketing win: Q35 is another g33 device not a gen4 part
|
|
* like its G35 brethren.
|
|
*/
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_Q35_G, &intel_g33_info ),
|
|
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_I965_G, &intel_i965_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_G35_G, &intel_i965_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_I965_Q, &intel_i965_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_I946_GZ, &intel_i965_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_I965_GM, &intel_i965_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_I965_GME, &intel_i965_info ),
|
|
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_GM45_GM, &intel_g4x_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_G45_E_G, &intel_g4x_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_G45_G, &intel_g4x_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_Q45_G, &intel_g4x_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_G41_G, &intel_g4x_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_B43_G, &intel_g4x_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_B43_G1, &intel_g4x_info ),
|
|
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_IRONLAKE_D_G, &intel_ironlake_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_IRONLAKE_M_G, &intel_ironlake_info ),
|
|
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT1, &intel_sandybridge_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT2, &intel_sandybridge_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT2_PLUS, &intel_sandybridge_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT1, &intel_sandybridge_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT2, &intel_sandybridge_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS, &intel_sandybridge_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_S_GT, &intel_sandybridge_info ),
|
|
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_M_GT1, &intel_ivybridge_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_M_GT2, &intel_ivybridge_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_D_GT1, &intel_ivybridge_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_D_GT2, &intel_ivybridge_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_S_GT1, &intel_ivybridge_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_S_GT2, &intel_ivybridge_info ),
|
|
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT1, &intel_haswell_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT2, &intel_haswell_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT2_PLUS, &intel_haswell_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT1, &intel_haswell_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT2, &intel_haswell_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT2_PLUS, &intel_haswell_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT1, &intel_haswell_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT2, &intel_haswell_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT2_PLUS, &intel_haswell_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT1, &intel_haswell_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT2, &intel_haswell_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT2_PLUS, &intel_haswell_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT1, &intel_haswell_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT2, &intel_haswell_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT2_PLUS, &intel_haswell_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT1, &intel_haswell_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT2, &intel_haswell_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT2_PLUS, &intel_haswell_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT1, &intel_haswell_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT2, &intel_haswell_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT2_PLUS, &intel_haswell_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT1, &intel_haswell_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT2, &intel_haswell_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT2_PLUS, &intel_haswell_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT1, &intel_haswell_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT2, &intel_haswell_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT2_PLUS, &intel_haswell_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT1, &intel_haswell_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT2, &intel_haswell_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT2_PLUS, &intel_haswell_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT1, &intel_haswell_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT2, &intel_haswell_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT2_PLUS, &intel_haswell_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT1, &intel_haswell_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT2, &intel_haswell_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT2_PLUS, &intel_haswell_info ),
|
|
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_PO, &intel_valleyview_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_1, &intel_valleyview_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_2, &intel_valleyview_info ),
|
|
INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_3, &intel_valleyview_info ),
|
|
|
|
INTEL_DEVICE_MATCH (PCI_MATCH_ANY, &intel_generic_info ),
|
|
|
|
{ 0, 0, 0 },
|
|
};
|
|
|
|
const struct pci_id_match *PciDevMatch(uint16_t dev,const struct pci_id_match *list)
|
|
{
|
|
while(list->device_id)
|
|
{
|
|
if(dev==list->device_id)
|
|
return list;
|
|
list++;
|
|
}
|
|
return NULL;
|
|
}
|
|
|
|
const struct intel_device_info *
|
|
intel_detect_chipset(struct pci_device *pci)
|
|
{
|
|
const struct pci_id_match *ent = NULL;
|
|
const char *name = NULL;
|
|
int i;
|
|
|
|
ent = PciDevMatch(pci->device_id, intel_device_match);
|
|
|
|
if(ent != NULL)
|
|
return (const struct intel_device_info*)ent->match_data;
|
|
else
|
|
return &intel_generic_info;
|
|
|
|
#if 0
|
|
for (i = 0; intel_chipsets[i].name != NULL; i++) {
|
|
if (DEVICE_ID(pci) == intel_chipsets[i].token) {
|
|
name = intel_chipsets[i].name;
|
|
break;
|
|
}
|
|
}
|
|
if (name == NULL) {
|
|
xf86DrvMsg(scrn->scrnIndex, X_WARNING, "unknown chipset\n");
|
|
name = "unknown";
|
|
} else {
|
|
xf86DrvMsg(scrn->scrnIndex, from,
|
|
"Integrated Graphics Chipset: Intel(R) %s\n",
|
|
name);
|
|
}
|
|
|
|
scrn->chipset = name;
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
int drmIoctl(int fd, unsigned long request, void *arg)
|
|
{
|
|
ioctl_t io;
|
|
|
|
io.handle = fd;
|
|
io.io_code = request;
|
|
io.input = arg;
|
|
io.inp_size = 64;
|
|
io.output = NULL;
|
|
io.out_size = 0;
|
|
|
|
return call_service(&io);
|
|
}
|
|
|
|
|
|
|